Commit Graph

70847 Commits

Author SHA1 Message Date
Marek Olšák 77a78c65f8 softpipe,llvmpipe: fix PIPE_SHADER_CAP_MAX_INPUTS value
PIPE_MAX_SHADER_INPUTS was recently bumped to 80 because of tessellation.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91099
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91101

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2015-06-25 09:00:23 +02:00
Ben Widawsky d1663ccb4c i965/bxt: Add basic Broxton infrastructure
The thread counts and URB information are all speculative numbers that were
based on some CHV numbers at the time.

v2:
Originally this patch had PCI IDs. I've moved that to a new patch at the end of
the series.
Remove is_cherryview hack.
Add PCI ids. These match the ones defined in the kernel. The only one tested by
us is 0x0a84.
Capitalize the hex string (Mark)

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Tested-by: "Lecluse, Philippe" <Philippe.Lecluse@intel.com>
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
2015-06-24 16:37:12 -07:00
Ian Romanick 9f261dc18d radeon: Advertise correct GL_QUERY_COUNTER_BITS/GL_SAMPLES_PASSED value
Commit b765119c changed the default value of all the counter bits to
64.  However, older hardware only has 32 counter bits.

This has only been build-tested.  We don't have any tests that verify
the advertised value against implementation behavior, so I don't know
what additional testing could be done.

NOTE: It appears that many Gallium drivers (at least r300 and i915g)
have the same problem, but I don't see a way for the state-tracker to
determine the counter size.  Marek says, "For Gallium, a new PIPE_CAP or
new get_xxx_param function will be needed."

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
2015-06-24 16:33:32 -07:00
Jason Ekstrand b2c6ba0c4b i965/fs_live_variables: Do liveness analysis bottom-to-top
From Muchnick's Advanced Compiler Design and Implementation:

"To determine which variables are live at each point in a flowgraph, we
perform a backward data-flow analysis"

Previously, we were walking the blocks forwards and updating the livein and
then the liveout.  However, the livein calculation depends on the liveout
and the liveout depends on the successor blocks.  The net result is that it
takes one full iteration to go from liveout to livein and then another
full iteration to propagate to the predecessors.  This works out to an
O(n^2) computation where n is the number of blocks.  If we run things in
the other order, it's O(nl) where l is the maximum loop depth which is
practically bounded by 3.

On my HSW desktop, one particular shadertoy test gets a 20% improvement in
compile times:

N           Min           Max        Median           Avg        Stddev
x  10        15.965        16.884        16.026       16.1822    0.34736846
+  10        12.813        13.052        12.876       12.8891    0.06913666
Difference at 95.0% confidence
        -3.2931 +/- 0.235316
        -20.3501% +/- 1.45417%
        (Student's t, pooled s = 0.250444)

Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-06-24 13:11:30 -07:00
Tapani Pälli 104c8fc2c2 i965: Delete linked GLSL IR when using NIR.
This is based on Kenneth's patch to delete 'most of the IR'. Due to
linker changes to clone variables, we can now free all of IR.

Saves 58MB of memory when replaying a Dota 2 trace on Broadwell.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
2015-06-24 12:03:41 -07:00
Tapani Pälli c2ff3485b3 glsl: clone inputs and outputs during linking
This increases memory pressure during linking but makes it easier
for backend to free IR after it is not needed anymore.

v2: use resource list as ralloc context in case of relink (Kenneth)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
2015-06-24 12:01:21 -07:00
Chris Wilson 4b35ab9bdb i965: Rename intel_emit* to reflect their new location in brw_pipe_control
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-06-24 10:35:04 -07:00
Chris Wilson 9d4b9f1e0c i965: Transplant PIPE_CONTROL routines to brw_pipe_control
Start trimming the fat from intel_batchbuffer.c. First by moving the set
of routines for emitting PIPE_CONTROLS (along with the lore concerning
hardware workarounds) to a separate brw_pipe_control.c

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-06-24 10:35:04 -07:00
Kenneth Graunke 147cdb53ec nir: Use a switch statement for detecting move-like operations.
Suggested by Jason Ekstrand.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
2015-06-24 10:35:04 -07:00
Brian Paul e31bce4041 svga: silence warnings about unexpected shader type
Trivial.
2015-06-24 10:42:19 -06:00
Brian Paul c1de7df6d4 st/mesa: remove unneeded pipe_surface_release() in st_render_texture()
This caused us to always free the pipe_surface for the renderbuffer.
The subsequent call to st_update_renderbuffer_surface() would typically
just recreate it.  Remove the call to pipe_surface_release() and let
st_update_renderbuffer_surface() take care of freeing the old surface
if it needs to be replaced (because of change to mipmap level, etc).

This can save quite a few calls to pipe_context::create_surface() and
surface_destroy().

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2015-06-24 07:14:56 -06:00
Emil Velikov a552c897ca st/wgl: add stw_nopfuncs.h to the sources lists
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-06-24 13:43:44 +01:00
Julien Isorce 30d67d3824 loader: move loader_open_device out of HAVE_LIBUDEV block
Fixes the following build issue, when building without libudev.

CCLD   libGL.la
./.libs/libglx.a(dri2_glx.o): In function `dri2CreateScreen':
src/glx/dri2_glx.c:1186: undefined reference to `loader_open_device'
collect2: ld returned 1 exit status

CCLD     libEGL.la
Undefined symbols for architecture x86_64:
"_loader_open_device", referenced from:
  _dri2_initialize_x11_dri2 in libegl_dri2.a(platform_x11.o)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91077
Signed-off-by: Julien Isorce <j.isorce@samsung.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-06-24 13:43:44 +01:00
Grigori Goronzy 390f94e358 winsys/radeon: reduce BO cache timeout
1000 ms is an extreme value for typical interactive loads. A large
cache has some disadvantages. Search for reusable BOs can take a long
time and memory might get exhausted.

Let's be rather conservative and use half of the old value,
500ms. This is beneficial to some loads on my test system and there
are no regressions.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2015-06-24 14:33:40 +02:00
Grigori Goronzy 29aaab2b5f winsys/radeon: align BO size to page size
This is the basic granularity for BO allocations. The alignment also
helps with BO reuse by the cached bufmgr.

This results in a huge 45% speedup in Metro 2033 Redux on my test
system. The game relies on buffer orphaning with very small buffers
(hundreds of bytes in size) and that did not work efficiently
before. This change may also affect other applications and games.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2015-06-24 14:33:14 +02:00
Tapani Pälli 32a220f1f6 glsl: remove cross validation of interpolation qualifier with GLSL 4.40
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Timothy Arceri <t_arceri@yahoo.com.au>
2015-06-24 10:06:32 +03:00
Kenneth Graunke 23132cd13b i965: Fix whitespace error in gen8_depth_state.c
Trivial.
2015-06-23 23:31:17 -07:00
Kenneth Graunke c8b8e8b29b i965: Don't count NIR instructions for shader-db.
Matt, Jason, and I haven't found this useful in a long time.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-06-23 23:31:17 -07:00
Michel Dänzer 7796e8889a winsys/radeon: Unmap GPU VM address range when destroying BO
But only when doing so is safe according to the
RADEON_INFO_VA_UNMAP_WORKING kernel query.

This avoids kernel GPU VM address range conflicts when the BO has other
references than the GEM handle being closed, e.g. when the BO is shared.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90537
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90873

Cc: "10.5 10.6" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Christian König <christian.koenig@amd.com>
2015-06-24 15:11:55 +09:00
Eric Anholt 3fd4c80b32 vc4: Also dump VC4_PACKET_LOAD_TILE_BUFFER_GENERAL. 2015-06-23 18:40:50 -07:00
Eric Anholt 5458ac01ae vc4: Add dumping for VC4_PACKET_LOAD/STORE_FULL_RES_TILE_BUFFER. 2015-06-23 18:40:50 -07:00
Eric Anholt 997f677841 vc4: Don't try to CSE color reads.
It returns a new value for each sample in the TLB.  We've already avoided
trying to get the same index's color multiple times at the vc4_program.c
level, so we're not losing anything by doing this.
2015-06-23 18:40:50 -07:00
Eric Anholt 0f69d59b1c vc4: Make a helper for TLB color writes, too.
We've done so for all the other QIR instruction generation in this file.
2015-06-23 18:40:50 -07:00
Eric Anholt af83eb2581 vc4: Pull the blending operation out to a separate function.
It's fairly separate from the rest of the TLB operations at frag end time,
and we'll need to run it multiple times to support MSAA blending.
2015-06-23 18:40:50 -07:00
Eric Anholt 76851f49a5 vc4: Clarify size calculation for Z/S writes.
It's the same value for loads and stores, because they're basically the
same packet.
2015-06-23 18:40:50 -07:00
Eric Anholt 8fbcabc41a vc4: Add an "args" temporary for RCL setup. 2015-06-23 18:40:50 -07:00
Eric Anholt 19056d0429 vc4: Reuse (and extend) the packet.h sizes for dumping. 2015-06-23 18:40:50 -07:00
Eric Anholt fc0da629b5 vc4: Fix printfs for blit fallbacks. 2015-06-23 18:40:50 -07:00
Eric Anholt e70f5617f1 tgsi_to_nir: Fix translation of TXF on MSAA targets.
Noticed while trying to add GL_ARB_texture_multisample support to vc4.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-06-23 18:40:50 -07:00
Jason Ekstrand 6844d6b7f8 i965/fs: Get rid of an unused variable in emit_barrier()
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2015-06-23 17:06:05 -07:00
Jason Ekstrand 40801295d5 i965: Remove the brw_context from the visitors
As of this commit, nothing actually needs the brw_context.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2015-06-23 15:36:13 -07:00
Jason Ekstrand bcaf4a3f07 i965/vec4_vs: Add an explicit use_legacy_snorm_formula flag
This way we can stop doing is_gles3 checks inside of the compiler.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2015-06-23 15:35:01 -07:00
Jason Ekstrand 924b15d7de i965/vec4: Turn some _mesa_problem calls into asserts
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2015-06-23 15:35:00 -07:00
Jason Ekstrand 663f8d121d i965/vs: Pass the current set of clip planes through run() and run_vs()
Previously, these were pulled out of the GL context conditionally based on
whether we were running ff/ARB or a GLSL program.  Now, we just pass them
in so that the visitor doesn't have to grab them itself.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2015-06-23 15:35:00 -07:00
Jason Ekstrand 4af62c0f5c i965/fs: Add a do_rep_send flag to run_fs
Previously, we were pulling it from brw->do_rep_send

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2015-06-23 15:35:00 -07:00
Jason Ekstrand 1b0f6ffa15 i965: Pull calls to get_shader_time_index out of the visitor
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2015-06-23 15:34:59 -07:00
Jason Ekstrand c7893dc3c5 i965: Use a single index per shader for shader_time.
Previously, each shader took 3 shader time indices which were potentially
at arbirary points in the shader time buffer.  Now, each shader gets a
single index which refers to 3 consecutive locations in the buffer.  This
simplifies some of the logic at the cost of having a magic 3 a few places.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2015-06-23 15:33:16 -07:00
Jason Ekstrand 6e255a3299 i965: Add compiler options to brw_compiler
This creates the options at screen cration time and then we just copy them
into the context at context creation time.  We also move is_scalar to the
brw_compiler structure.

We also end up manually setting some values that the core would have set by
default for us.  Fortunately, there are only two non-zero shader compiler
option defaults that we aren't overriding anyway so this isn't a big deal.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2015-06-23 14:28:09 -07:00
Jason Ekstrand 073294d3ef i965/fs: Plumb compiler debug logging through brw_compiler
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2015-06-23 14:28:08 -07:00
Jason Ekstrand 3fd457c9dd i965/fs: Do the no16 perf logging directly in fs_visitor::no16()
While we're at it, we'll drop the note about 10-20% performance loss.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2015-06-23 14:28:08 -07:00
Jason Ekstrand f45bf97f30 i965/fs: Make no16 non-variadic
We never used the fact that it was variadic anyway.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-06-23 14:28:08 -07:00
Jason Ekstrand 1bc3b62d4a i965: Move INTEL_DEBUG variable parsing to screen creation time
v2: Do bufmgr set_debug and set_aub_dump at screen time as well.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-06-23 14:28:08 -07:00
Jason Ekstrand d7565b7d65 i965: Remove the dependance on brw_context from the generators
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-06-23 14:28:08 -07:00
Jason Ekstrand e639a6f68e i965: Plumb compiler debug logging through a function pointer in brw_compiler
v2 (Ken): Make shader_debug_log a printf-like function.
v3 (Jason): Add a void * to pass the brw_context through

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-06-23 14:28:08 -07:00
Kenneth Graunke b0ad3ce4e7 mesa: Add a va_args variant of _mesa_gl_debug().
This will be useful for wrapper functions.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2015-06-23 14:28:08 -07:00
Jason Ekstrand 630764407a i965: Replace some instances of brw->gen with devinfo->gen 2015-06-23 14:28:08 -07:00
Matt Turner ae097580ac i965: Initialize backend_shader::mem_ctx in its constructor.
We were initializing it in each subclasses' constructors for some
reason.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2015-06-23 12:24:42 -07:00
Matt Turner d8eeb4917c i965: Assert that the GL primitive isn't out of range.
Coverity sees the if (mode >= BRW_PRIM_OFFSET (128)) test and assumes
that the else-branch might execute for mode to up 127, which out be out
of bounds.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2015-06-23 12:24:42 -07:00
Matt Turner 4d93a07c45 i965/cfg: Assert that cur_do/while/if pointers are non-NULL.
Coverity sees that the functions immediately below the new assertions
dereference these pointers, but is unaware that an ENDIF always follows
an IF, etc.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2015-06-23 12:24:42 -07:00
Matt Turner 04758d25b4 mesa: Delete unused ICEIL().
Can't find any uses of it in git history.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2015-06-23 12:24:42 -07:00