Commit Graph

75975 Commits

Author SHA1 Message Date
Nicolai Hähnle 761c7d59c4 vbo: disable the minmax cache when the hit rate is low
When applications stream their index buffers, the caches for those BOs become
useless and add overhead, so we want to disable them. The tricky part is
coming up with the right heuristic for *when* to disable them.

The first question is which hit rate to aim for. Since I'm not aware of any
interesting borderline applications that do something like "draw two or three
times for each upload", I just kept it simple.

The second question is how soon we should give up on the caching. Applications
might have a warm-up phase where they fill a buffer gradually but then keep
reusing it. For this reason, I count the number of indices that hit and miss
(instead of the number of calls that hit or miss), since comparing that to
the size of the buffer makes sense.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-02-03 14:04:06 +01:00
Nicolai Hähnle 115c643b16 mesa: add USAGE_DISABLE_MINMAX_CACHE flag to buffer UsageHistory
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-02-03 14:03:59 +01:00
Nicolai Hähnle 6b057f8ecc vbo: cache/memoize the result of vbo_get_minmax_indices (v3)
Some games developers are unaware that an index buffer in a VBO still needs
to be read by the CPU if some varying data comes from a user pointer (unless
glDrawRangeElements and friends are used). This is particularly bad when
they tell us that the index buffer should live in VRAM.

This cache helps, e.g. lifting This War Of Mine (a particularly bad
offender) from under 10fps to slightly over 20fps on a Carrizo.

Note that there is nothing prohibiting a user from rendering from multiple
threads simultaneously with the same index buffer, hence the locking. (The
internal buffer map taken for the buffer still leads to a race, but at least
the locks are a move in the right direction.)

v2: disable the cache on USAGE_TEXTURE_BUFFER as well (Chris Forbes)

v3:
- use bool instead of GLboolean for MinMaxCacheDirty (Ian Romanick)
- replace the sticky USAGE_PERSISTENT_WRITE_MAP bit by a direct
  AccessFlags check

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> (v2)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-02-03 14:03:49 +01:00
Nicolai Hähnle 1a570d96a6 vbo: move vbo_get_minmax_indices into its own source file
We will add more code for caching/memoization. Moving the existing code
into its own file helps keep things modular.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-02-03 14:03:48 +01:00
Nicolai Hähnle 46b7a526f5 mesa/main: bail earlier for size == 0 in _mesa_clear_buffer_sub_data
Note that the conversion of the clear data (when data != NULL) can fail due
to an out of memory condition, but it does not check any error conditions
mandated by the spec. Therefore, it is safe to skip when size == 0.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-02-03 14:03:46 +01:00
Nicolai Hähnle fd7229b437 mesa/main: add USAGE_PIXEL_PACK_BUFFER flag to buffer UsageHistory
We will want to disable minmax index caching for buffers that are used in this
way.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-02-03 14:03:45 +01:00
Nicolai Hähnle 54c4a9803b mesa/main: add USAGE_TRANSFORM_FEEDBACK_BUFFER flag to buffer UsageHistory
We will want to disable minmax index caching for buffers that are used in this
way.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-02-03 14:03:41 +01:00
Nicolai Hähnle 55fb921d69 util/hash_table: add _mesa_hash_table_num_entries
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-02-03 14:03:35 +01:00
Nicolai Hähnle 8b11d8cfbf util/hash_table: add _mesa_hash_table_clear (v4)
v4: coding style change (Matt Turner)

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v3)
2016-02-03 14:03:25 +01:00
Leo Liu 6ad2e55a14 st/omx/dec/h264: fix corruption when scaling matrix present flag set
The scaling list should be filled out with zig zag scan

v2: integrate zig zag scan for list 4x4 to vl(Christian)
v3: move list determination out from the loop(Ilia)

Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2016-02-02 20:29:47 -05:00
Leo Liu 4f598f2173 vl: add zig zag scan for list 4x4
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2016-02-02 20:29:43 -05:00
Roland Scheidegger 848a023c05 llvmpipe: use scissor_planes_needed helper function
So it doesn't get out of sync in multiple places.
2016-02-03 01:25:45 +01:00
Jordan Justen 141ef75569 i965/gen8: Initialize aux_mode to GEN8_SURFACE_AUX_MODE_NONE
GEN8_SURFACE_AUX_MODE_NONE is 0, so this is a no-op.

Yet, this also makes it clear that we can compare aux_mode to the
other GEN8_SURFACE_AUX_MODE_ values. We will want to compare to
GEN8_SURFACE_AUX_MODE_HIZ.

v2: Some very minor cherry-pick conflicts due to moving it around in the series.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
2016-02-02 15:44:18 -08:00
Ilia Mirkin 18f688d62a mesa: use default geometry's samples when there are no attachments
Whether multisampling is turned on depends, in part, on whether
attachments are themselves multisample surfaces. However when there are
no attachments, we should rely on the default geometry for this.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-02-02 17:08:46 -05:00
Ilia Mirkin 095da3b550 mesa: invalidate framebuffer when changing parameters
This fixes dEQP-GLES31.functional.fbo.completeness.no_attachments

When the width or height are 0, the framebuffer is incomplete. We may
also not have been passing the new state down to the driver when the
widths/heights/etc changed. Make sure to dirty the state so that the
framebuffer state is revalidated at draw time.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2016-02-02 17:08:46 -05:00
Ilia Mirkin beac7b1b8b mesa: use geometric helper for computing min samples
In case we have a draw buffer without attachments, we should be looking
at the default number of samples.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2016-02-02 17:08:46 -05:00
Ilia Mirkin 2d4976fa19 mesa: the _mesa_geometric_* functions require full types from mtypes.h
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2016-02-02 17:08:46 -05:00
Niels Ole Salscheider fb44cfadce winsys/radeon: Do not deinit the pb cache if it was not initialized
This fixes a crash in pb_cache_release_all_buffers.

Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2016-02-02 21:11:15 +01:00
Marek Olšák 84a6d2d7d6 tgsi/scan: add tgsi_shader_info::reads_samplemask 2016-02-02 21:04:52 +01:00
Marek Olšák 0d68b91220 radeonsi: rework RB+ for Stoney
This fixes it.

States which also need to be taken into account:
- SPI color formats - each down-conversion format supports only a limited set
  of SPI formats
- whether MSAA resolving and logic op are enabled

These need special handling:
- blending
- disabled channels

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-02 21:03:19 +01:00
Marek Olšák 066d76c2f4 radeonsi: rename cb_target_mask state to cb_render_state
and rename a variable in the function.

SX_PS_DOWNCONVERT will be emitted here.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-02 21:03:19 +01:00
Marek Olšák 5f0f9a5619 radeonsi: treat intensity render targets exactly like red
The motivation is to simplify the Stoney RB+ code.
Intensity is already treated as red except here.

No piglit regressions.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-02 21:03:18 +01:00
Marek Olšák f96f94966d tgsi: set correct src type for UP2H
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2016-02-02 21:02:26 +01:00
Connor Abbott 19db71807f util/hash_table: don't compare deleted entries
The equivalent of the last patch for the hash table. I'm not aware of
any issues this fixes.

v2:
- use entry_is_deleted (Timothy)

Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
2016-02-02 14:42:40 -05:00
Connor Abbott 8fc2f652a2 util/set: don't compare against deleted entries
When we delete entries in the hash set, we mark them "deleted" by
setting their key to the deleted_key, which points to a dummy
deleted_key_value. When searching for an entry, we normally skip over
those, but set_add() had some code for searching for duplicate entries
which forgot to skip over deleted entries. This led to a segfault inside
the NIR vectorization pass, since its key comparison function
interpreted the memory where deleted_key_value resides as a pointer and
tried to dereference it.

v2:
- add better commit message (Timothy)
- use entry_is_deleted (Timothy)

Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
2016-02-02 14:42:32 -05:00
Jordan Justen bd97b62525 glsl: Disable tree grafting optimization for shared variables
Fixes:
 * dEQP-GLES31.functional.compute.basic.shared_atomic_op_multiple_groups
 * dEQP-GLES31.functional.compute.basic.shared_atomic_op_multiple_invocation
 * dEQP-GLES31.functional.compute.basic.shared_atomic_op_single_group
 * dEQP-GLES31.functional.compute.basic.shared_atomic_op_single_invocation

From https://android.googlesource.com/platform/external/deqp

Reported-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Tested-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-02-02 10:50:40 -08:00
Jordan Justen afef1422cb glsl: Enable debug prints for do_common_optimization
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-02-02 10:50:40 -08:00
Roland Scheidegger 5e090079e1 Revert "i965: Provide sse2 version for rgba8 <-> bgra8 swizzle"
This reverts commit ab30426e33.

Apparently the memory isn't quite as aligned when this gets called
as it should be, causing crashes. (Albeit this looks independent
from this code, should crash just as well if ssse3 is enabled when
compiling without this patch.)
https://bugs.freedesktop.org/show_bug.cgi?id=93962
2016-02-02 15:45:59 +01:00
Dave Airlie e7a27f70b9 virgl: mark function as static
This is fallout from the previous changes.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93961

Signed-off-by: Dave Airlie <airlied@redhat.com>
2016-02-02 17:55:40 +10:00
Roland Scheidegger 7221b8aec6 gallivm: add PK2H/UP2H support
Add support for these opcodes, the conversion functions were already
there albeit need some new packing stuff.
Just like the tgsi version, piglit won't like it for all the same
reasons, so it's disabled (UP2H passes piglit arb_shader_language_packing
tests, albeit since PK2H won't due to those rounding differences I don't
know if that one works or not as the piglit test is rather difficult to
deal with).

Reviewed-by: Brian Paul <brianp@vmware.com>
2016-02-02 05:58:20 +01:00
Roland Scheidegger 5171ec9ca9 gallivm: add PK2H/UP2H support
Add support for these opcodes, the conversion functions were already
there albeit need some new packing stuff.
Just like the tgsi version, piglit won't like it for all the same
reasons, so it's disabled (UP2H passes piglit arb_shader_language_packing
tests, albeit since PK2H won't due those rounding differences I don't
know if that one works or not as the piglit test is rather difficult to
deal with).
2016-02-02 05:58:19 +01:00
Roland Scheidegger dc16086e3b tgsi: add PK2H/UP2H support
The util functions handle the half-float conversion.
Note that piglit won't like it much due to:
a) The util functions use magic float mul conversion but when run inside
softpipe/llvmpipe, denorms are flushed to zero, therefore when the conversion
is from/to f16 denorm the result will be zero. This is a bug which should be
fixed in these functions (should not rely on denorms being available), but
will happen elsewhere just the same (e.g. conversion to f16 render targets).
b) The util functions use trunc round mode rather than round-to-nearest. This
is NOT a bug (as it is a d3d10 requirement). This will result of rounding not
representable finite values to MAX_F16 rather than INFINITY. My belief is the
piglit tests are wrong here but it's difficult to tell (generally glsl
rounding mode is undefined, however I'm not sure if rounding mode might need
to be consistent for different operations). Nevertheless, for gl it would be
better to use round-to-nearest, but using different rounding for GL and d3d10
is an unsolved problem (as it affects things like conversion to f16 render
targets, clear colors, this shader opcode).

Hence for now don't enable the cap bit (so the code is unused).
(Code is from imirkin, comment from sroland)

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Roland Scheidegger <sroland@vmvware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2016-02-02 05:58:19 +01:00
Roland Scheidegger 99bd96abbb llvmpipe: drop scissor planes early if the tri is fully inside them
If the tri is fully inside a scissor edge (or rather, we just use the
bounding box of the tri for the comparison), then we can drop these
additional scissor "planes" early. We do not even need to allocate
space for them in the tri.

The math actually appears to be slightly iffy due to bounding boxes
being rounded, but it doesn't matter in the end.

Those scissor rects are costly - the 4 planes from the scissor are
already more expensive to calculate than the 3 planes from the tri itself,
and it also prevents us from using the specialized raster code for small
tris.

This helps openarena performance by about 8% or so. Of course, it helps
there that while openarena often enables scissoring (and even moves the
scissor rect around) I have not seen a single tri actually hit the
scissor rect, ever.

v2: drop individual scissor edges, and do it earlier, not even allocating
space for them.
v3: help the compiler a bit with simpler code, suggested by Brian.

Reviewed-by: Brian Paul <brianp@vmware.com>
2016-02-02 05:58:19 +01:00
Roland Scheidegger 9d2a34e105 llvmpipe: minor cleanup of sse2 for calc_fixed_position
Just slightly simpler assembly.

Reviewed-by: Brian Paul <brianp@vmware.com>
2016-02-02 05:58:19 +01:00
Roland Scheidegger 8aa168eb8f llvmpipe: use vector loads for (optimized) tri raster funcs
When we switched to 64bit rasterization, we could no longer use straight
aligned loads for loading the plane data. However, what the code actually
does for loading 3 planes, is 12 scalar loads + 9 unpacks, and then there's
another 8 unpacks for the transpose we need (!).

It would be possible to do the (scalar) loads of course already transposed
(at least saving the additional unpacks), however instead just use
(un)aligned vector loads, and recalculate the eo values, which is much less
instructions (note in case of the triangle_32_3_4 case, the eo values are
not even used, making the scalar loads + unpacks for them all the more
pointless).

This drops execution time of the triangle_32_3_4 function considerably,
albeit it doesn't really make a measurable difference (for small tris we're
essentially limited by vertex throughput in any case), for triangle_32_3_16
it's essentially noise (the loop is more costly than the initial code there).

(I'm thinking about just ditching storing the eo values in the plane data,
so could switch back to using aligned planes, however right now they are
still used in the other raster functions dealing with planes with scalar
code. Also not touching the ppc code, might not be that bad there in any
case.)

Reviewed-by: Brian Paul <brianp@vmware.com>
2016-02-02 05:58:19 +01:00
Roland Scheidegger ab30426e33 i965: Provide sse2 version for rgba8 <-> bgra8 swizzle
The existing code used ssse3, and because it isn't compiled in a separate
file compiled with that, it is usually not used (that, of course, could
be fixed...), whereas sse2 is always present at least with 64bit builds.
This should be pretty much as fast as the pshufb version, albeit those
code paths aren't really used on chips without llc in any case.

v2: fix andnot argument order, add comments
v3: use pshuflw/hw instead of shifts (suggested by Matt Turner), cut comments

Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-02-02 05:58:19 +01:00
Roland Scheidegger 116e4dc995 mesa: fix typo in python scripts
Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-02-02 05:58:19 +01:00
Rob Herring f0f4259324 virgl: also build vtest for Android
Enabling swrast on Android causes a link error because vtest is missing.

Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2016-02-02 09:58:51 +10:00
Rob Herring 2d3301e4d5 virgl: fix reference counting of prime handles
The virgl reference counting of buffers is broken for prime fd buffers.
Each prime fd passed into virgl_drm_winsys_resource_create_handle creates
a new resource. The solution requires creating a separate hash table to
track flink names separately from prime handles.

Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2016-02-02 09:58:29 +10:00
Rob Herring f87330dbce virgl: reuse screen when fd is already open
It is necessary to share the screen between mesa and gralloc to
properly ref count resources. This implements a hash lookup on
the file description to re-use an already created screen. This is
a similar implementation as freedreno and radeon.

Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2016-02-02 09:58:29 +10:00
Mauro Rossi 6711592c2f nouveau/video: wrap assertion within #ifndef NDEBUG
The change is necessary to avoid the following building error in android:

external/mesa/src/gallium/drivers/nouveau/nouveau_vp3_video_bsp.c: In function 'nouveau_vp3_bsp_next':
external/mesa/src/gallium/drivers/nouveau/nouveau_vp3_video_bsp.c:269:14: error: 'bsp_bo' undeclared (first use in this function)
       assert(bsp_bo->size >= str_bsp->w0[0] + num_bytes[i]);
              ^
This matches the declaration of the variables in question.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-02-01 17:45:19 -05:00
Ilia Mirkin 047b917718 st/mesa: treat a write as a read for range purposes
We use this logic to detect live ranges and then do plain renaming
across the whole codebase. As such, to prevent WaW hazards, we have to
treat a write as if it were also a read.

For example, the following sequence was observed before this patch:

 13: UIF TEMP[6].xxxx :0
 14:   ADD TEMP[6].x, CONST[6].xxxx, -IN[3].yyyy
 15:   RCP TEMP[7].x, TEMP[3].xxxx
 16:   MUL TEMP[3].x, TEMP[6].xxxx, TEMP[7].xxxx
 17:   ADD TEMP[6].x, CONST[7].xxxx, -IN[3].yyyy
 18:   RCP TEMP[7].x, TEMP[3].xxxx
 19:   MUL TEMP[4].x, TEMP[6].xxxx, TEMP[7].xxxx

While after this patch it becomes:

 13: UIF TEMP[7].xxxx :0
 14:   ADD TEMP[7].x, CONST[6].xxxx, -IN[3].yyyy
 15:   RCP TEMP[8].x, TEMP[3].xxxx
 16:   MUL TEMP[4].x, TEMP[7].xxxx, TEMP[8].xxxx
 17:   ADD TEMP[7].x, CONST[7].xxxx, -IN[3].yyyy
 18:   RCP TEMP[8].x, TEMP[3].xxxx
 19:   MUL TEMP[5].x, TEMP[7].xxxx, TEMP[8].xxxx

Most importantly note that in the first example, the second RCP is done
on the result of the MUL while in the second, the second RCP should have
the same value as the first. Looking at the GLSL source, it is apparent
that both of the RCP's should have had the same source.

Looking at what's going on, the GLSL looks something like

  float tmin_8;
  float tmin_10;
  tmin_10 = tmin_8;
... lots of code ...
  tmin_8 = tmpvar_17;
... more code that never looks at tmin_8 ...

And so we end up with a last_read somewhere at the beginning, and a
first_write somewhere at the bottom. For some reason DCE doesn't remove
it, but even if that were fixed, DCE doesn't handle 100% of cases, esp
including loops.

With the last_read somewhere high up, we overwrite the previously
correct (and large) last_read with a low one, and then proceed to decide
to merge all kinds of junk onto this temp. Even if that weren't the
case, and there were just some writes after the last read, then we might
still overwrite a merged value with one of those.

As a result, we should treat a write as a last_read for the purpose of
determining the live range.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Cc: mesa-stable@lists.freedesktop.org
2016-02-01 17:40:18 -05:00
Matt Turner 75c9def8ee i965/gen7+: Use NIR for lowering of pack/unpack opcodes.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-02-01 10:43:57 -08:00
Matt Turner f4952421cd i965/vec4: Implement nir_op_pack_uvec2_to_uint.
And mark nir_op_pack_uvec4_to_uint unreachable, since it's only produced
by lowering pack[SU]norm4x8 which the vec4 backend does not need.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-02-01 10:43:57 -08:00
Matt Turner 955d052058 nir: Add lowering support for unpacking opcodes.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-02-01 10:43:57 -08:00
Matt Turner 9b8786eba9 nir: Add lowering support for packing opcodes.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-02-01 10:43:57 -08:00
Matt Turner 1dc312e295 i965/fs: Implement support for extract_word.
The vec4 backend will lower it.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-02-01 10:43:57 -08:00
Matt Turner 68f8c5730b nir: Add opcodes to extract bytes or words.
The uint versions zero extend while the int versions sign extend.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-02-01 10:43:57 -08:00
Matt Turner 8709dc0713 glsl: Remove 2x16 half-precision pack/unpack opcodes.
i965/fs was the only consumer, and we're now doing the lowering in NIR.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-02-01 10:43:57 -08:00
Matt Turner 1a53a4fc7a i965/fs: Switch from GLSL IR to NIR for un/packHalf2x16 scalarizing.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-02-01 10:43:57 -08:00