The current DCE pass hits issue around phi nodes. These need to be
solved properly eventually, but for now workaround them by doing
something obviously correct (but suboptimal compile time).
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
We need to insert parallel copies at the logical end of blocks, before branches.
Add a pseudo instruction signaling that. Cribbed from ACO.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Lifted from ir3. Algorithm is the same; the data structures and interface are
lightly modified to decouple from ir3's IR.
Sequentializing parallel copies after RA is tricky. ir3's implementation works
well enough, so I use that one.
Original implementation by Connor Abbott.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Rather than using builder magic (implicitly lowered on emit), add actual pseudo
operations (explicitly lowered before encoding). In theory this is slower, I
doubt it matters. This makes the instruction aliases first-class for IR prining
and machine inspection, which will make optimization passes easier to write.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Lifted from Bifrost. Add some basic optimizer tests (they pass!) to show the
compiler is ready to be unit tested. Given we can't have hardware CI for Asahi
yet -- and dEQP is still pretty janky -- unit testing should prove quite useful.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Instructions, bytes, and registers -- this should hold us over until we
can reverse the underlying uarch and get proper cycle estimations.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
We usually use pdevice for "physical device" and not "device pointer".
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16259>
This changes the intel_device_info calculation to call an additional
DRM query requesting the geometry topology from the kernel, which may
differ from the result of the current topology query on XeHP+
platforms with compute-only and 3D-only DSSes. This seems more
reliable than the current guesswork done in intel_device_info.c trying
to figure out which DSSes are available for the render CS.
Cc: 22.1 <mesa-stable>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14143>
The glsl-to-tgsi code generation and GLSL IR linker is is going away
(!8044), so we need to make the call on whether to use nir-to-tgsi (See
!15932 and !15541), or switch over to the NIR code generator. The NIR
backend should reduce the compile time regression while providing more
direct control over the IR we receive than going through NTT, while still
providing the optimization that NIR-to-TGSI was bringing us.
nv92 shader-db:
total local in shared programs: 2048 -> 1988 (-2.93%)
local in affected programs: 2048 -> 1988 (-2.93%)
total gpr in shared programs: 688468 -> 724705 (5.26%)
gpr in affected programs: 437159 -> 473396 (8.29%)
total instructions in shared programs: 6115978 -> 5874401 (-3.95%)
instructions in affected programs: 5038041 -> 4796464 (-4.80%)
total loops in shared programs: 1361 -> 835 (-38.65%)
loops in affected programs: 538 -> 12 (-97.77%)
total bytes in shared programs: 42389752 -> 40480416 (-4.50%)
bytes in affected programs: 36311616 -> 34402280 (-5.26%)
LOST: 0
GAINED: 1 (pixmark-piano)
nv120 shader-db:
total local in shared programs: 4416 -> 1988 (-54.98%)
local in affected programs: 4416 -> 1988 (-54.98%)
total gpr in shared programs: 870534 -> 893490 (2.64%)
gpr in affected programs: 564210 -> 587166 (4.07%)
total instructions in shared programs: 6379402 -> 6243210 (-2.13%)
instructions in affected programs: 5430790 -> 5294598 (-2.51%)
total bytes in shared programs: 68184224 -> 66729672 (-2.13%)
bytes in affected programs: 58013544 -> 56558992 (-2.51%)
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15949>
nvc0 aligns to 0x10 in setting up its rogram header, but nv50 TLS
allocation expects the incoming value to be aligned already (like TGSI
always did). Avoids regression in
KHR-GL33.shaders.arrays.declaration.dynamic_expression_array_access_* with
the nir backend.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15949>
Alyssa Rosenzweig
Alyssa Rosenzweig
Rob Clark
Konstantin Seurer
Yiwei Zhang
Francisco Jerez
Emma Anholt
Karol Herbst