Commit Graph

652 Commits

Author SHA1 Message Date
Samuel Pitoiset 5ee5c73d2d radv: implement PS epilogs
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17485>
2022-07-18 18:40:02 +00:00
Samuel Pitoiset df8fb721a5 radv,aco: rename radv_aco_build_prolog to radv_aco_build_shader_part
Will be re-used for PS epilogs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17485>
2022-07-18 18:40:02 +00:00
Samuel Pitoiset 6517a2b926 radv: fix dumping VS prologs assembly
This got removed by mistake and broke
RADV_DEBUG=shaders,nocache,prologs.

Fixes: 9fe2b6b748 ("aco/radv: provide a vs prolog callback from aco to radv.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17413>
2022-07-08 10:58:33 +00:00
Rhys Perry 48578713b7 radv,aco,ac/llvm: use nir_op_f{sin,cos}_amd
This lets NIR optimize the multiplication, particularly sin/cos(a * #b).

fossil-db (Sienna Cichlid):
Totals from 12306 (7.58% of 162293) affected shaders:
MaxWaves: 224814 -> 224834 (+0.01%)
Instrs: 17365273 -> 17338758 (-0.15%); split: -0.16%, +0.00%
CodeSize: 93478488 -> 93354912 (-0.13%); split: -0.14%, +0.01%
VGPRs: 752080 -> 752072 (-0.00%); split: -0.00%, +0.00%
SpillSGPRs: 8440 -> 8410 (-0.36%)
Latency: 200402154 -> 200279405 (-0.06%); split: -0.06%, +0.00%
InvThroughput: 37588077 -> 37545545 (-0.11%); split: -0.11%, +0.00%
VClause: 293863 -> 293874 (+0.00%); split: -0.03%, +0.03%
SClause: 619539 -> 619064 (-0.08%); split: -0.09%, +0.01%
Copies: 1151591 -> 1151641 (+0.00%); split: -0.04%, +0.05%
Branches: 506434 -> 506437 (+0.00%); split: -0.00%, +0.00%
PreSGPRs: 877609 -> 877517 (-0.01%); split: -0.01%, +0.00%
PreVGPRs: 711938 -> 711940 (+0.00%); split: -0.00%, +0.00%

fossil-db (LLVM, Sienna Cichlid):
Totals from 4377 (3.59% of 121873) affected shaders:
SGPRs: 358960 -> 359176 (+0.06%); split: -0.18%, +0.25%
VGPRs: 319832 -> 319720 (-0.04%); split: -0.18%, +0.15%
SpillSGPRs: 46983 -> 47007 (+0.05%); split: -0.99%, +1.04%
CodeSize: 30872812 -> 30764512 (-0.35%); split: -0.39%, +0.04%
MaxWaves: 73814 -> 73904 (+0.12%); split: +0.25%, -0.13%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10587>
2022-07-07 22:18:08 +00:00
Timur Kristóf ff13fc381d radv: Use NIR optimization to move discards to the top.
Fossil stats on Sienna Cichlid:

Totals from 1988 (1.55% of 128653) affected shaders:
VGPRs: 68096 -> 67928 (-0.25%); split: -0.61%, +0.36%
CodeSize: 5391936 -> 5391312 (-0.01%); split: -0.11%, +0.10%
MaxWaves: 53020 -> 52946 (-0.14%); split: +0.05%, -0.19%
Instrs: 992413 -> 992509 (+0.01%); split: -0.10%, +0.11%
Latency: 8643141 -> 8789295 (+1.69%); split: -0.31%, +2.00%
InvThroughput: 1680195 -> 1680605 (+0.02%); split: -0.04%, +0.07%
SClause: 50886 -> 51318 (+0.85%); split: -0.73%, +1.57%
Copies: 57017 -> 56741 (-0.48%); split: -1.28%, +0.80%
PreSGPRs: 66766 -> 67048 (+0.42%); split: -0.24%, +0.66%
PreVGPRs: 56832 -> 56935 (+0.18%); split: -0.44%, +0.62%

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13037>
2022-07-01 18:55:53 +00:00
Dave Airlie 9fe2b6b748 aco/radv: provide a vs prolog callback from aco to radv.
Avoid building the radv binary in aco, just callback with the
necessary info.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16445>
2022-07-01 01:34:19 +00:00
Dave Airlie 2dce77c239 aco/radv: provide a callback from aco shader building to build binary
This moves the radv specific code into radv, and calls back from
aco into radv.

This should allow easier radeonsi integration later.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16445>
2022-07-01 01:34:19 +00:00
Daniel Schürmann def3690447 radv: use callback for nir_lower_to_scalar
Now uses nir_lower_alu_width.
This avoids scalarization and re-vectorization of 16bit instructions.

Totals from 289 (0.21% of 134913) affected shaders: (GFX10.3)
VGPRs: 12864 -> 13072 (+1.62%); split: -0.50%, +2.11%
SpillSGPRs: 609 -> 505 (-17.08%)
SpillVGPRs: 946 -> 1145 (+21.04%)
CodeSize: 2537024 -> 2576976 (+1.57%); split: -0.10%, +1.67%
Scratch: 89088 -> 113664 (+27.59%)
MaxWaves: 7150 -> 7134 (-0.22%)
Instrs: 458352 -> 460830 (+0.54%); split: -0.45%, +0.99%
Latency: 6615279 -> 6844092 (+3.46%); split: -0.08%, +3.54%
InvThroughput: 1929504 -> 2044989 (+5.99%); split: -0.22%, +6.21%
VClause: 7186 -> 7338 (+2.12%); split: -0.08%, +2.20%
SClause: 13144 -> 13116 (-0.21%)
Copies: 46152 -> 50127 (+8.61%); split: -0.11%, +8.73%
Branches: 16530 -> 16572 (+0.25%); split: -0.02%, +0.27%
PreSGPRs: 14903 -> 14905 (+0.01%); split: -0.01%, +0.03%
PreVGPRs: 11806 -> 11730 (-0.64%); split: -1.83%, +1.19%

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15176>
2022-06-27 15:07:27 +00:00
Qiang Yu e9f1f115fa ac/nir: add triangle_strip_adjacency_fix to gs input lower
From radeonsi.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
2022-06-27 11:32:43 +08:00
Qiang Yu 109eb378e5 ac/nir: change es output lower param to esgs_itemsize
radeonsi may add extra dword to the stride, so let's pass it
directly.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
2022-06-27 11:32:34 +08:00
Qiang Yu 8b5e8b2af7 ac/nir: remove unused param num_reserved_es_outputs from gs input lower
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
2022-06-27 11:32:30 +08:00
Qiang Yu d00845faf4 ac/nir: add no_input_lds_space param to hs output lower
This is used by radeonsi to save some lds space when all LS output
is passed by register.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu ae9b02b4d0 ac/nir: add wave_size parameter to ac_nir_lower_hs_outputs_to_mem
Used by radeonsi and radv to reflect true wave size used, not minimal size.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu 18d51831a8 ac/nir: add pass_tessfactors_by_reg param to hs output lower
radeonsi won't emit tess factor in the lower pass, need to keep
the output for llvm backend to pass it as parameter. This is used
by radeonsi for an optimization to save LDS write.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu 6ccb9634de ac/nir: use nir_intrinsic_load_hs_out_patch_data_offset_amd in tess lower
radeonsi load this from SGPR arg, can't use static value because TCS output
and TES input may not match (TCS output is not a key for TES) and
determined in runtime.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu 2ba6d2b107 ac/nir: remove unused parameter in tes input lower
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu 3aa70d92ce radv: no need to do gs_alloc_req for newer chips in ngg vs/tes
Copy from radeonsi.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17130>
2022-06-27 02:12:13 +00:00
Bas Nieuwenhuizen e75f11625d radv: Deal with derefs from opaque types in function parameters.
Needs more copy propagation before nir_opt_derefs picks it up.

Note that the full general problem of opaque types stored in
intermediate variables is still open, but that seems like a whole
can of worms, and no sense to have gfxbench stay broken during the
time it takes to solve that.

Cc: mesa-stable
Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5945
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17012>
2022-06-27 01:23:43 +00:00
Samuel Pitoiset 6cab999d6a radv,aco: rename radv_prolog_binary/radv_shader_prolog to shader_part
The same structures and functions will be re-used for PS epilogs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17084>
2022-06-21 08:04:50 +00:00
Timur Kristóf b243e94f07 radv: Lower mesh shader 3D workgroup ID to 1D index.
This allows future mesh shaders to use a 3D workgroup ID.
Also changes how the NV_mesh_shader first_task is emulated.
The new code moves the responsibility from ac_nir into radv.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17023>
2022-06-15 18:28:58 +00:00
Samuel Pitoiset fe57fe1fd8 ac/nir/ngg: count the number of generated primitives for VS and TES
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15639>
2022-06-09 08:02:39 +00:00
Georg Lehmann 5ebb014bdf radv, aco: Round texture array layer in NIR.
Foz-DB Navi21:
Totals from 9100 (6.75% of 134913) affected shaders:
VGPRs: 609912 -> 610104 (+0.03%); split: -0.01%, +0.05%
SpillSGPRs: 1459 -> 1489 (+2.06%)
CodeSize: 66705920 -> 66620288 (-0.13%); split: -0.13%, +0.00%
MaxWaves: 148546 -> 148518 (-0.02%); split: +0.00%, -0.02%
Instrs: 12278485 -> 12255821 (-0.18%); split: -0.19%, +0.00%
Latency: 277414916 -> 277261192 (-0.06%); split: -0.08%, +0.02%
InvThroughput: 48431180 -> 48394637 (-0.08%); split: -0.11%, +0.03%
VClause: 250866 -> 251062 (+0.08%); split: -0.04%, +0.11%
SClause: 498377 -> 498173 (-0.04%); split: -0.08%, +0.04%
Copies: 652835 -> 655371 (+0.39%); split: -0.09%, +0.48%
Branches: 284367 -> 284371 (+0.00%); split: -0.00%, +0.00%
PreSGPRs: 498580 -> 498477 (-0.02%)
PreVGPRs: 558436 -> 558709 (+0.05%); split: -0.01%, +0.06%

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16871>
2022-06-08 20:57:22 +00:00
Konstantin Seurer d5dd0df65f radv: ray cull mask
Lower the cull_mask system value to rt variable
load and advertise the corresponding capability.

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16430>
2022-06-08 20:20:21 +00:00
Timur Kristóf 0280b526d5 radv: Implement mesh shader scratch ring.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16737>
2022-06-08 08:43:51 +00:00
Timur Kristóf b664279755 ac/nir/ngg: Use mesh shader scratch ring when outputs don't fit LDS.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16737>
2022-06-08 08:43:51 +00:00
Timur Kristóf ac5ab8d227 ac: Add task shader ring information.
Similarly to tessellation rings information, move the task
rings info to ac_gpu_info.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16737>
2022-06-08 08:43:51 +00:00
Georg Lehmann d8493e5310 radv, aco: Lower txf offset in NIR.
Foz-DB Navi21:
Totals from 384 (0.28% of 134913) affected shaders:
VGPRs: 29736 -> 29536 (-0.67%)
CodeSize: 2455796 -> 2452652 (-0.13%); split: -0.13%, +0.01%
MaxWaves: 6350 -> 6358 (+0.13%)
Instrs: 457743 -> 456273 (-0.32%); split: -0.33%, +0.01%
Latency: 6680266 -> 6730612 (+0.75%); split: -0.03%, +0.78%
InvThroughput: 1562936 -> 1599375 (+2.33%); split: -0.05%, +2.38%
VClause: 9258 -> 9291 (+0.36%); split: -0.14%, +0.50%
SClause: 15713 -> 15707 (-0.04%); split: -0.08%, +0.04%
Copies: 26878 -> 27021 (+0.53%); split: -0.03%, +0.56%
PreVGPRs: 27259 -> 27230 (-0.11%); split: -0.11%, +0.01%

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16869>
2022-06-08 08:13:01 +00:00
Timur Kristóf f7f2770e72 ac/nir: Add remappability to tess and ESGS I/O lowering passes.
This will be used for radeonsi to map common I/O location to fixed
slots agreed by different shader stages.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16418>
2022-06-07 01:40:14 +00:00
Qiang Yu 6a95452ddf ac/nir: use nir_intrinsic_load_lshs_vertex_stride_amd
For radeonsi which pass this value by argument.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16418>
2022-06-07 01:40:14 +00:00
Samuel Pitoiset 5af1409c1b radv: fix lowering GS intrinsics if NGG is disabled per pipeline
If NGG is disabled per pipeline for extreme (or suboptimal) geometry
or with transform feedback, make sure to not lower GS intrinsics that
are only needed for NGG GS. This means we have to lower GS intrinsics
later in the compilation process to effectively know if the pipeline
uses NGG.

fossils-db (Navi21):
Totals from 8 (0.01% of 134913) affected shaders:
VGPRs: 512 -> 520 (+1.56%)
CodeSize: 58180 -> 65080 (+11.86%); split: -0.04%, +11.90%
MaxWaves: 128 -> 126 (-1.56%)
Instrs: 10525 -> 11779 (+11.91%); split: -0.05%, +11.96%
Latency: 62941 -> 49428 (-21.47%); split: -21.59%, +0.12%
InvThroughput: 16121 -> 12950 (-19.67%); split: -19.96%, +0.29%
VClause: 122 -> 123 (+0.82%); split: -0.82%, +1.64%
SClause: 130 -> 143 (+10.00%)
Copies: 566 -> 596 (+5.30%); split: -0.35%, +5.65%
Branches: 200 -> 208 (+4.00%)
PreSGPRs: 424 -> 422 (-0.47%)
PreVGPRs: 430 -> 424 (-1.40%); split: -1.63%, +0.23%

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15885>
2022-06-02 09:42:54 +02:00
Georg Lehmann aa9d2d8893 radv: Enable VK_INTEL_shader_integer_functions2.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
2022-06-01 17:09:25 +00:00
Georg Lehmann 4e6667ea87 radv: Lower hadd/hradd.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
2022-06-01 17:09:25 +00:00
Georg Lehmann cc3f03b757 radv: Lower mul_32x16.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
2022-06-01 17:09:25 +00:00
Jason Ekstrand 7003ff2e3a radv: Use nir_gather_xfb_info
Instead of gathering XFB info over and over again every time we even
want to know if the shader uses XFB, gather it once when we compile the
shader and refer to the copy in the NIR.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16750>
2022-05-31 23:09:30 +00:00
Timur Kristóf c69b771e35 radv, ac/nir: Fix multiview layer export for mesh shaders.
Unfortunately, radv_lower_multiview is not suitable for mesh shaders
because it can't know the mapping between API mesh shader
invocations and output primitives.

Additionally, when lowering view id to layer, it must be created
as a per-primitive PS input.

Fixes: d32656bc65
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16504>
2022-05-31 07:58:29 +00:00
Samuel Pitoiset f7b1ad7c06 radv: update VRS rates on GFX11
GFX11 uses enum instead of 2-bit integer numbers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
iReviewed-by: Timur Kristóf <timur.kristof@gmail.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16557>
2022-05-26 07:43:38 +00:00
Samuel Pitoiset 35af86af8c radv: move HS info and task_num_entries to the physical device
They are not logical device properties.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16688>
2022-05-25 11:39:20 +00:00
Samuel Pitoiset fc3717df0c radv: cleanup using device/physical_device during pipeline creation
This removes a TON of pipeline->device occurences which were a mess.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16603>
2022-05-23 07:32:56 +00:00
Rhys Perry 75c80be484 radv: add missing NIR_PASS() and switch from NIR_PASS_V()
Unlike NIR_PASS_V(), NIR_PASS() can skip printing the shader when
NIR_DEBUG=print.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5244
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12448>
2022-05-19 13:37:20 +00:00
Rhys Perry d98b7817fc radv: call nir_metadata_preserve in various lowering passes
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12448>
2022-05-19 13:37:20 +00:00
Marek Olšák 2443054932 amd: rename fishes to Navi21, Navi22, Navi23, Navi24, and Rembrandt
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16604>
2022-05-19 11:55:50 +00:00
Samuel Pitoiset 8e1085c19a radv: do not try to dump the NIR of the trap handler shader
There is no NIR at all.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16553>
2022-05-18 07:19:20 +00:00
Samuel Pitoiset 9207d791af radv: rename shader compile functions to spirv_to_nir/nir_to_asm
For better clarity.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16553>
2022-05-18 07:19:20 +00:00
Samuel Pitoiset 2d02e210b5 radv: do not align VGPRS to 8 or 16 on GFX11
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
2022-05-17 10:08:17 +00:00
Dave Airlie a179e1aede aco/radv: drop radv_nir_compiler_options from aco.
Add a new aco input and options structs, then convert from radv
pieces on submit.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16521>
2022-05-17 06:15:25 +00:00
Dave Airlie 8198900071 ac/radv: drop info pointer from the ac and radv shader structs
This was being used for one bool, just pass the bool.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16521>
2022-05-17 06:15:25 +00:00
Marek Olšák 39800f0fa3 amd: change chip_class naming to "enum amd_gfx_level gfx_level"
This aligns the naming with PAL.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pellou-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16469>
2022-05-13 14:56:22 -04:00
Samuel Pitoiset 42ef89e8db radv,aco: use the new TCS WaveID SGPR to compute vs_rel_patch_id on GFX11
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16369>
2022-05-12 15:46:20 +00:00
Timur Kristóf 0d0165db8e radv: Print task shader stage name before disasm.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14929>
2022-05-12 00:29:51 +00:00
Timur Kristóf 8dbde92659 radv: Lower shared and task_payload variables in task/mesh shaders.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14929>
2022-05-12 00:29:51 +00:00