Commit Graph

147971 Commits

Author SHA1 Message Date
Caio Oliveira 58c4a95320 intel/compiler: Use a struct for brw_compile_gs parameters
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14139>
2021-12-13 01:08:16 +00:00
Caio Oliveira acf2d3c78b intel/compiler: Use a struct for brw_compile_tes parameters
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14139>
2021-12-13 01:08:16 +00:00
Caio Oliveira 7372a48a4a intel/compiler: Use a struct for brw_compile_tcs parameters
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14139>
2021-12-13 01:08:16 +00:00
Dave Airlie 76da456954 crocus: cleanup bo exports for external objects
This might have led to a leak in firefox/webrender/webgl scenarios

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Fixes: f3630548f1 ("crocus: initial gallium driver for Intel gfx 4-7")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14167>
2021-12-13 10:31:12 +10:00
Marek Olšák 9ff086052a radeonsi: unroll loops of up to 128 iterations
It's not exactly 128 because longer loop bodies scale the number down.

This improves perf for VP13/Creo and Piano. Most other tests either didn't
show any difference or are CPU-bound.

v2:
- The lowering passes had to be moved to the optimization loop because unrolling creates lowerable variables.
- Piano has some pattern that looks like corruption and the pattern changed with loop unrolling.
  The pattern is present on other drivers as well.

v3:
- I removed the Piano test from CI traces because the image is random. The output was wrong even before
  this MR, and now it's randomly wrong.

|   PERCENTAGE DELTAS    |  Shaders |    SGPRs |    VGPRs |SpillSGPR |SpillVGPR | PrivVGPR |  Scratch | CodeSize | MaxWaves |
|------------------------|----------|----------|----------|----------|----------|----------|----------|----------|----------|
| alien_isolation        |      2936|    .     |    0.02 %|    .     |    .     |    .     |    .     |    0.83 %|    .     |
| deadcore               |        76|   18.47 %|    .     |    .     |    .     |    .     |    .     |  167.69 %|    .     |
| deus_ex_mankind_div..  |      1410|    0.10 %|    0.15 %|    .     |    .     |    .     |    .     |    1.70 %|    .     |
| f1-2015                |       775|    0.37 %|    0.16 %|    .     |    .     |    .     |    .     |    3.25 %|   -0.07 %|
| hitman                 |      1413|    0.10 %|   -0.03 %|    6.45 %|    .     |    .     |    .     |    0.61 %|    0.03 %|
| metro_2033_redux       |      2670|    .     |    .     |    .     |    .     |    .     |    .     |    0.13 %|    0.01 %|
| pixmark-piano-0.7.0    |         2|    .     |   14.29 %| -100.00 %|    .     |    .     |    .     |   78.07 %|   -4.76 %|
| reflections_subway     |        98|   -0.53 %|    .     |    .     |    .     |    .     |    .     |    7.64 %|    .     |
| thea                   |       172|    0.12 %|   -0.81 %|    .     |    .     |    .     |    .     |    0.65 %|    0.15 %|
| ubershaders            |        54|    .     |    .     |    .     |    .     |    .     |    .     |   61.13 %|    .     |
| ue4_effects_cave       |       290|    0.05 %|    .     |    .     |    .     |    .     |    .     |    2.62 %|    .     |
| vp13-creo              |        26|   -3.38 %|   -4.20 %|    .     |    .     |    .     |    .     |   88.56 %|    2.62 %|
| vp13-sw                |       100|   -0.36 %|   -9.14 %|    .     | -100.00 %|    .     | -100.00 %|  -17.97 %|    0.39 %|
| vp20-creo              |        22|   -0.82 %|   -3.33 %|    .     |    .     |    .     |    .     |   81.59 %|    1.51 %|
| vp20-sw                |       296|   -4.51 %|   -0.63 %|    .     |    .     |    .     |    .     |   58.93 %|    0.20 %|
|------------------------|----------|----------|----------|----------|----------|----------|----------|----------|----------|
| All affected           |       189|    3.05 %|   -2.87 %|  500.00 %| -100.00 %|    .     | -100.00 %|  135.61 %|    1.32 %|
|------------------------|----------|----------|----------|----------|----------|----------|----------|----------|----------|
| Total                  |     57794|    0.01 %|   -0.02 %|    0.27 %|   -3.13 %|    .     |   -2.89 %|    1.73 %|    .     |

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> (v1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13966>
2021-12-11 20:07:35 +00:00
Marek Olšák af9ec3c45d radeonsi: add shader profiles that disable binning
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13966>
2021-12-11 20:07:35 +00:00
Marek Olšák 4fd8171f64 radeonsi: print more stats for shader-db
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13966>
2021-12-11 20:07:35 +00:00
Marek Olšák b3b2f97f2e radeonsi: add Wave32 heuristics and shader profiles
This generally works well.

There are new cases that select Wave32, and there are shader profiles
which adjust that.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13966>
2021-12-11 20:07:35 +00:00
Marek Olšák e2a1883337 glsl: fix setting compiled_source_sha1 without a shader cache
We need to set it even if Cache == NULL.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13966>
2021-12-11 20:07:35 +00:00
Marek Olšák 2785141c16 nir: add nir_has_divergent_loop function
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13966>
2021-12-11 20:07:35 +00:00
Marek Olšák 26b522eae5 nir: serialize divergent fields
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13966>
2021-12-11 20:07:35 +00:00
Marek Olšák 6eb3fe2d4f nir: disable a NIR test due to undebuggable & locally unreproducible CI failures
debian-vulkan but not any other CI pipeline consistently fails with:
    FileNotFoundError: [Errno 2] No such file or directory: 'nir_tests.xml'

I have to assume that either debian-vulkan is broken, or the NIR test
infrastructure is broken. That's not all. I got the same failure when
I wanted to add a new test, which means the CI is preventing us from adding
new NIR tests, which is a very serious problem with the CI or NIR tests.
The python error doesn't imply that it's a test failure, so something else
is broken. If you don't want such commits to happen again, print better
error messages.

See also the discussion in the MR.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13966>
2021-12-11 20:07:35 +00:00
Marek Olšák 2ab310b78b nir: handle more intrinsics in divergence analysis
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13966>
2021-12-11 20:07:35 +00:00
Italo Nicola f0eb163ae0 drisw: do an MSAA resolve when copying the backbuffer
When calling glXCopySubBuffer, we must resolve the backbuffer before
copying it the frontbuffer.

Fixes piglit's glx/glx-copy-sub-buffer on virgl.

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11714>
2021-12-11 17:49:00 +00:00
Italo Nicola 6740f34568 virgl: flush cmd buffer when flushing frontbuffer
When a resource is multisampled, we usually submit a multisampling
resolving blit before we present it or use it in some other way, but
currently we don't always flush the cmd buffer before flushing the
frontbuffer, this commit fixes that.

Fixes piglit's glx/glx-copy-sub-buffer MSAA cases on vtest, in
conjunction with other commits of this series.

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11714>
2021-12-11 17:49:00 +00:00
Italo Nicola 0577a142de virgl/vtest: implement resource_create_front
This is required for glXCopySubBufferMESA to work.

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11714>
2021-12-11 17:49:00 +00:00
Italo Nicola b6d0447027 virgl/vtest: use correct resource stride in flush_frontbuffer
The displaytarget's resource stride is alignment is currently 64-bytes,
where the shared resource stride is unaligned.

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11714>
2021-12-11 17:49:00 +00:00
Caio Oliveira a235e02787 util: Use ralloc for strings in cache test
Also avoid warnings about asprintf result not being checked.

Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14054>
2021-12-11 08:06:10 +00:00
Caio Oliveira 51351760c2 util: Convert cache test to use gtest
Replace a bunch of helper functions for checking results with ones
from GTest.

Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14054>
2021-12-11 08:06:10 +00:00
Jason Ekstrand 88e97d75d0 intel/dev: Add gtt_size to devinfo
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13647>
2021-12-11 05:05:19 +00:00
Jason Ekstrand 1f559930b6 anv: Stop doing too much per-sample shading
We were setting anv_pipeline::sample_shading_enable based on
sampleShadingEnable without looking at minSampleShading.  We would then
pass this value into nir_lower_wpos_center which would add sample_pos to
frag_coord.  Then the back-end compiler picks up on the existence of
sample_pos and forces persample dispatch.  This leads to doing
per-sample dispatch whenever sampleShadingEnable = VK_TRUE regardless of
the value of minSampleShading.  This is almost certainly costing us
perf somewhere.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14022>
2021-12-11 04:40:20 +00:00
Nanley Chery 5197809302 iris: Update the initial CCS state on XeHP
We can't map the CCS on this platform to initialize it into the
PASS_THROUGH state. This can cause issues with optimizations in the
driver that rely on this state.

For example, after rendering to a surface with AUX_NONE, we can then
render to it with AUX_CCS_E without an ambiguate in between (if the CCS
in the PASS_THROUGH state). If that state was incorrect and the aux was
actually compressed, there can be rendering corruption because the
contents may be misinterpreted on the second render.

Use a more accurate initial aux state to avoid these issues.

One notable change in behavior here is that aux surfaces can be created
with fast-cleared blocks even though the caller may specify a modifier
that doesn't support fast clears. This should be fine, so long as all HW
units that can access these surfaces can handle that bit-pattern. We
haven't seen an applicable restriction yet.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>
2021-12-11 04:14:20 +00:00
Nanley Chery eef4399afd iris: Modify the comment about zeroing CCS
Among other changes, we highlight the fact that we'll map the CCS -
something we can't do on XeHP.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>
2021-12-11 04:14:20 +00:00
Nanley Chery cba6d6cad3 iris: Don't assert a NULL aux BO during aux config
The assert was introduced in a function that allocated an auxiliary
surface BO, iris_resource_alloc_aux. After refactors, the function it's
in now, iris_resource_configure_aux, no longer does this allocation.
Drop the assert because its purpose is unclear and it's no longer
relevant for CCS on XeHP.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>
2021-12-11 04:14:20 +00:00
Nanley Chery 7d3200a37d iris: Don't allocate and initialize CCS on XeHP
The memory for CCS on XeHP can't be mapped by the CPU.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>
2021-12-11 04:14:20 +00:00
Nanley Chery 656d34a811 iris: Drop row pitch param from iris_get_ccs_surf
This parameter won't be used for XeHP, because we can't directly control
the row pitch of the CCS independently from the main surface.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>
2021-12-11 04:14:20 +00:00
Nanley Chery 7d57c9959e iris: Don't allocate a clear color BO for some Z/S
The only depth/stencil aux usage that can actually use the BO is
ISL_AUX_USAGE_HIZ_CCS_WT. Even with that aux usage, iris may disable
sampling depending on the surface configuration.

Allocate the clear color BO when it'd be usable, not just when the
auxiliary surface size is non-zero on ICL+. This prepares for CCS on
XeHP, which won't have an auxiliary surface.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>
2021-12-11 04:14:20 +00:00
Nanley Chery fecd6ae38e iris: Simplify iris_get_aux_clear_color_state_size
isl_dev.ss.clear_color_state_size is already zero on BDW and SKL. Drop
the redundant platform check and return the field directly.

We're going to have this function return zero more often and it will do
so uniformly using if-statements. We choose to remove the redundant
expression instead of adding a redundant if-statement.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>
2021-12-11 04:14:20 +00:00
Nanley Chery 4027337004 iris: Move some BO setup to iris_resource_init_aux_buf
To ease verification, place the assignment and reference of the aux BO
right before the same operations are done for the clear color BO. Also,
move the call to map_aux_addresses that's in the same if-block.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>
2021-12-11 04:14:20 +00:00
Nanley Chery 9acf0316ec iris: Use the aux BO and surf less during init
res->aux.bo and res->aux.surf will be NULL and zeroed, respectively, for
CCS on XeHP. Move and modify iris_resource_init_aux_buf to support this.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>
2021-12-11 04:14:20 +00:00
Nanley Chery 02bbdb0e92 iris: Change a param of iris_resource_init_aux_buf
Have iris_resource_init_aux_buf compute the clear color state size
(with an iris_screen struct) instead of passing it in directly.

We're going to move the function call soon. This keeps us from having to
move a passed in variable along with it.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>
2021-12-11 04:14:20 +00:00
Nanley Chery 18231fc548 intel/blorp: Modify get_fast_clear_rect for XeHP
The alignment and scale down values have changed on this platform.

To support drivers that won't use a CCS surface on this platform, this
patch computes the CCS fast clear rectangle using the main surface.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>
2021-12-11 04:14:20 +00:00
Nanley Chery c35b8a2889 intel/blorp: Modify the SKL+ CCS resolve rectangle
According to Bspec 2424, "Render Target Resolve":

   The Resolve Rectangle size is same as Clear Rectangle size from SKL+.

Use get_fast_clear_rect in blorp_ccs_resolve for SKL+.

Note that the Bspec differs from Vol7 of the Sky Lake PRM, which only
specifies aligning by the scaledown factors.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>
2021-12-11 04:14:20 +00:00
Nanley Chery 91128b1a0f intel/isl: Require aux map for some 64K alignment
The comment states that 64K alignment of surfaces is required when an
aux map is present on the platform. However, the code checks for GFX12
instead of dev->info->has_aux_map. Update the code to match the comment.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>
2021-12-11 04:14:20 +00:00
Jesse Natalie 46ef1e8389 ci/windows: Remove line numbers from assertions in spirv2dxil tests
Reviewed-by: Enrico Galli <enrico.galli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14156>
2021-12-11 03:43:11 +00:00
Lucas Stach fc17f79f2c etnaviv: fix alpha blend with dither on older GPUs
While setting up DITHER_MODE allows alpha blending to work properly
together with dithering on new GPUs (those with PE_DITHER_FIX), older
cores still change the render target. As dithering is optional and
implementation defined we can simply disable it on the affected GPUs,
when alpha blending is enabled to work around this bug.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13396>
2021-12-11 03:06:15 +00:00
Emma Anholt d199d65c3a nir/nir_opt_move,sink: Include load_ubo_vec4 as a load_ubo instr.
We weren't doing much motion in nir-to-tgsi because we considered all our
lowered load-ubos as unmovable.

softpipe shader-db:

total temps in shared programs: 563942 -> 563136 (-0.14%)
temps in affected programs: 9833 -> 9027 (-8.20%)

r300 shader-db:

instructions in affected programs: 22858 -> 23575 (3.14%)
temps in affected programs: 2039 -> 1813 (-11.08%)

(NIR had given r300 -19% instrs for +40% temps, so this feels like a
worthwhile trade back).

Reivewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14138>
2021-12-11 02:12:27 +00:00
Erico Nunes 013900c4d2 mesa: fix GL_MAX_SAMPLES with GLES2
EXT_multisampled_render_to_texture on GLES2 allows the
GL_MAX_SAMPLES_EXT enum to be used.

Move the condition from the GLES3 section to the GLES2 one so
that it stops returning GL_INVALID_ENUM in that case.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13967>
2021-12-11 01:31:59 +00:00
Silvestrs Timofejevs c02b75d22e egl: add config debug printout
Feature to print out EGL returned configs for debug purposes.

'eglChooseConfig' and 'eglGetConfigs' debug information printout is
enabled when the log level equals '_EGL_DEBUG'. The configs are
printed, and if any of them are "chosen" they are marked with their
index in the chosen configs array.

v2:
   a) re-factor the code in line with review comments
   b) rename function _snprintfStrcat, split it out and put into the
      src/util/u_string.h, make it a separate patch.
v3:
   remove unnecessary 'const' qualifiers from the function prototype
v4:
   a) re-factor the code in line with review comments
   b) move util_strnappend from utils back to eglconfigdebug.c. In my
      opinion this function is the best way of achieving the desired
      result, so it still used but made private to eglconfigdebug.c.
v5:
   a) drop unused parameter from function signature
   b) more const annotations
   c) directly access config parameters instead of going
      through _eglGetConfigKey

Signed-off-by: Silvestrs Timofejevs <silvestrs.timofejevs@imgtec.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13705>
2021-12-11 00:25:04 +00:00
Silvestrs Timofejevs f927a5c3d2 egl: introduce a log level getter function
Being able to retrieve the log level can be useful to enable/disable
debug code. The alternative, which is calling 'getenv' function every
time to retrieve the log level, is more "expensive".

Signed-off-by: Silvestrs Timofejevs <silvestrs.timofejevs@imgtec.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13705>
2021-12-11 00:25:04 +00:00
Jordan Justen fd2a558bf8 intel/l3: Make DG1 urb-size exception more generic
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14136>
2021-12-11 00:09:50 +00:00
Rhys Perry c7fa15b381 aco: improve clrx disassembly
- remove uninteresting lines of output
- remove binary offset before instructions, for easier diffing
- replace generated labels with block numbers
- add encoded instructions at the end of lines, like LLVM dissaembly
- print constant data instead of trying to disassemble it

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14042>
2021-12-10 23:46:30 +00:00
Jesse Natalie 11eb03c44e microsoft/compiler: Remove algebaric pass for inot
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14140>
2021-12-10 23:23:29 +00:00
Jesse Natalie 45354be410 microsoft/compiler: Implement inot
Fixes: cb283616 ("nir/algebraic: Small optimizations for SpvOpFOrdNotEqual and SpvOpFUnordEqual")
Reviewed-by: Enrico Galli <enrico.galli@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14140>
2021-12-10 23:23:29 +00:00
Khem Raj 249556dad8 v3dv: account for 64bit time_t on 32bit arches
This makes is a bit more portable, especially on 32bit architectures
with 64bit time_t defaults. Especially on musl its a must.

Fixes
../mesa-21.3.0/src/broadcom/vulkan/v3dv_bo.c:71:15: error: format specifies type 'long' but the argument has type 'time_t' (aka 'long long') [-Werror,-Wformat]
              time.tv_sec);
              ^~~~~~~~~~~

Also reported here [1]

[1] https://github.com/agherzan/meta-raspberrypi/issues/969

Signed-off-by: Khem Raj <raj.khem@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14118>
2021-12-10 22:26:56 +00:00
Samuel Pitoiset e2ad92eb22 radv: do not perform depth/stencil resolves for suspended render pass
From the Vulkan spec:

    "Store and resolve operations are only performed at the end of a
     render pass instance that does not specify the
     VK_RENDERING_SUSPENDING_BIT_KHR flag."

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14112>
2021-12-10 22:03:00 +00:00
Samuel Pitoiset c27348a3f7 Revert "radv: Add bufferDeviceAddressMultiDevice support."
This was a workaround for fixing a crash with Baldur's Gate 3 at start
but the game fixed it since.

This reverts commit 1fe375e7cf.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14134>
2021-12-10 21:38:00 +00:00
Jason Ekstrand b8d04863e2 intel/fs: Drop high_quality_derivatives
We've never bothered to hook it up in crocus or iris.  If we do in the
future, it should probably be a NIR pasa anyway.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14056>
2021-12-10 21:20:47 +00:00
Jason Ekstrand 6dc9958bf3 intel/compiler: Get rid of wm_prog_key::frag_coord_adds_sample_pos
This hasn't actually done anything for a while.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14056>
2021-12-10 21:20:47 +00:00
Jason Ekstrand 278d12f991 intel/fs,vec4: Drop prog_data binding tables
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14056>
2021-12-10 21:20:47 +00:00