Commit Graph

111885 Commits

Author SHA1 Message Date
Caio Marcelo de Oliveira Filho 4b0bc664a5 gallium: Remove unused util_ringbuffer
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-06-17 13:02:44 -07:00
Caio Marcelo de Oliveira Filho 397d1a18ef llvmpipe: Don't use u_ringbuffer for lp_scene_queue
Inline the ring buffer and signal logic into lp_scene_queue instead of
using a u_ringbuffer.  The code ends up simpler since there's no need
to handle serializing data from / to packets.

This fixes a crash when compiling Mesa with LTO, that happened because
of util_ringbuffer_dequeue() was writing data after the "header
packet", as shown below

    struct scene_packet {
       struct util_packet header;
       struct lp_scene *scene;
    };

    /* Snippet of old lp_scene_deque(). */
    packet.scene = NULL;
    ret = util_ringbuffer_dequeue(queue->ring,
                                  &packet.header,
                                  sizeof packet / 4,
    return packet.scene;

but due to the way aliasing analysis work the compiler didn't
considered the "&packet->header" to alias with "packet->scene".  With
the aggressive inlining done by LTO, this would end up always
returning NULL instead of the content read by
util_ringbuffer_dequeue().

Issue found by Marco Simental and iThiago Macieira.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110884
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-06-17 13:02:44 -07:00
Alyssa Rosenzweig 390126e70a panfrost/midgard: Simplify 2D array logic
It shouldn't matter if we stick a z in for non-arrays, anyway.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-17 12:52:51 -07:00
Alyssa Rosenzweig a3ae3cb8e9 panfrost/midgard: Handle non-zero component in store
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-17 12:52:51 -07:00
Alyssa Rosenzweig 2c9e124f81 panfrost/midgard: Apply writemask to LUTs
Fixes LUT instructions with NIR registers.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-17 12:52:50 -07:00
Marek Olšák eba932ea43 amd: update addrlib
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-06-17 15:14:55 -04:00
Nicolai Hähnle d15cc1f55a radeonsi: reduce MAX_GEOMETRY_OUTPUT_VERTICES
This fixes piglit spec@glsl-1.50@gs-max-output on gfx9.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-06-17 15:14:51 -04:00
Alyssa Rosenzweig aef01dd2e5 panfrost: Cleanup default blend mode
Just encode the Mali magic number for `replace` rather than awkwardly
forcing Gallium structures through.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-17 10:45:52 -07:00
Alyssa Rosenzweig fbbb29aa5b panfrost: Don't accidentally include blend shader
Some residual dirty state can leak through across frames; zero this out.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-17 10:45:52 -07:00
Alyssa Rosenzweig 565c446dab panfrost/midgard: Use typeless moves internally
We switch all fmov to (i)mov, following the NIR switch. This simplifies
some code surrounding blend shaders and should have no functional
changes elsewhere.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-17 10:45:52 -07:00
Chia-I Wu 1fece5fa5f virgl: better support for PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
When the resource to be mapped is busy and the backing storage can
be discarded, reallocate the backing storage to avoid waiting.

In this new path, we allocate a new buffer, emit a state change,
write, and add the transfer to the queue .  In the
PIPE_TRANSFER_DISCARD_RANGE path, we suballocate a staging buffer,
write, and emit a copy_transfer (which may allocate, memcpy, and
blit internally).  The win might not always be clear.  But another
win comes from that the new path clears res->valid_buffer_range and
does not clear res->clean_mask.  This makes it much more preferable
in scenarios such as

  access = enough_space ? GL_MAP_UNSYNCHRONIZED_BIT :
                          GL_MAP_INVALIDATE_BUFFER_BIT;
  glMapBufferRange(..., GL_MAP_WRITE_BIT | access);
  memcpy(...); // append new data
  glUnmapBuffer(...);

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
2019-06-17 09:36:31 -07:00
Chia-I Wu 9975a0a84c virgl: add virgl_rebind_resource
We are going support reallocating the HW resource for a
virgl_resource.  When that happens, the virgl_resource needs to be
rebound to the context.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
2019-06-17 09:36:31 -07:00
Chia-I Wu 7e0508d9aa virgl: save virgl_hw_res in virgl_transfer
When PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE is properly supported,
virgl_transfer might refer to a different virgl_hw_res than
virgl_resource does.  We need to save the virgl_hw_res and use the
saved one.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
2019-06-17 09:36:31 -07:00
Chia-I Wu ad1ef35dc1 virgl: add resource_reference to virgl_winsys
It works similar to pipe_resource_reference but is for virgl_hw_res.
It can also replace resource_unref.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
2019-06-17 09:36:31 -07:00
Alyssa Rosenzweig 73bf669e3f panfrost/midgard: Add rounding mode specific opcodes
This adds a set of opcodes for performing moves and type conversions
with respect to particular rounding modes, required for OpenCL.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-17 09:32:31 -07:00
Alyssa Rosenzweig 9865b79a88 panfrost: Drop draws with complete scissor
The hardware support for scissoring requires minimally 1 pixel to be
drawn. If the scissor culls *everything*, we need to drop the draw
entirely early on.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-17 09:29:09 -07:00
Alyssa Rosenzweig 3a9b7692f1 panfrost: Disable pipelining temporarily
Pipelined rendering is important for performance but is not working
right these days. Disable it for correctness until the panfrost_job
refactor is enabled and we can do it right.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-17 09:25:52 -07:00
Alyssa Rosenzweig d4aed00214 panfrost/mfbd: Handle rendering to linear mipmap
In anticipation of more general mipmapping support, we implemented
support for rendering to linear mipmaps (a very simple case).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-17 08:42:54 -07:00
Alyssa Rosenzweig 531715431f panfrost: Implement sampling from non-zero initial levels
In preparation for more complex mipmap operations. glGenerateMipmap() in
particular, as implemented by u_blitter, requires reading from non-zero
initial mip levels.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-17 08:42:54 -07:00
Alyssa Rosenzweig a5f5b0640c panfrost: Resource management for linear 2D texture arrays
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-17 08:36:15 -07:00
Alyssa Rosenzweig dabfc71d36 panfrost/midgard: Adjust swizzles for 2D arrays
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-17 08:36:14 -07:00
Alyssa Rosenzweig 67a34acd00 panfrost: Set array_size to permit array textures
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-17 08:36:14 -07:00
Alyssa Rosenzweig bdf169abb3 panfrost: Decode array textures
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-17 08:36:14 -07:00
Alyssa Rosenzweig 0ae6bbe8a9 panfrost: Implement 3D texture resource management
Passes dEQP-GLES3.functional.texture.format.unsized.*3d*

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-17 08:36:14 -07:00
Alyssa Rosenzweig 36a7b2b018 panfrost: Specify 3D in texture descriptor
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-17 08:28:13 -07:00
Alyssa Rosenzweig 8429beef5e panfrost/midgard: Fix 3D texture masks/swizzles
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-17 08:28:13 -07:00
Alyssa Rosenzweig 56f9b47efd panfrost/midgard: Add swizzle_of/mask_of helpers
These make manipulating vectors in the Midgard compiler easier.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-17 08:28:13 -07:00
Alyssa Rosenzweig 8d1adc091b panfrost: Enable helper invocations when texturing
it turns out we have explicit control over helper invocations; if a
particular bit in the fragment shader descriptor is set, helper
invocations are launched; if it clear, they are not. Helper invocations
are required whenever computing derivatives, whether explicitly
(dFdx/dFdy) *or* implicitly (any texturing). Accordingly, we set this
bit when texturing to fix edge case behaviour (literally, haha).

Thank you to Jason Ekstrand and Ilia Mirkin for pointing out the
representative dEQP test failed along triangle edges and for suggesting
helper invocations / derivatives as a list of suspect pieces (which led
to discovering the helper invocations enable bit in the first place).

Ideally we would use the new NIR analysis pass for this, but that hasn't
landed quite yet.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-17 08:22:37 -07:00
Alyssa Rosenzweig 0219b99500 panfrost: Handle missing texture case
In some cases, Gallium can give us bad info about the texture count,
counting some NULL textures. We pass Gallium's info to the hardware
blindly, which can confuse the hardware in edge cases. This patch
adjusts accordingly.
2019-06-17 07:59:14 -07:00
Alyssa Rosenzweig 443f9ae0ad panfrost: Remove forced flush on clears
This worked around a bug in oooold versions of Panfrost. Nowadays, its
presence is, at best, *creating* bugs. Let's wack it.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-17 07:59:14 -07:00
Alyssa Rosenzweig 6460442049 panfrost: Flush scanout too
In a poorly coded app, the framebuffer can be partially drawn, an FBO
switched, switch back to the framebuffer and keep drawing, etc.
Reordering would fix this, but for now we need to just be careful about
flushing scanout too.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-17 07:59:14 -07:00
Alyssa Rosenzweig fc3f57bd7f panfrost: Improve viewport (clipping) robustness
On more complex apps (possibly using desktop GL specific extensions?),
our viewport code was getting wacky results for unclear reasons. Let's
be a little less wacky.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-17 07:59:14 -07:00
Alyssa Rosenzweig f9ecca2ff0 panfrost: Disable the tiler for clear-only jobs
To do so, we route some basic information through to the FBD creation
routines (currently just a binary toggle of "has draws?"). Eventually,
more refactoring will enable dynamic hierarchy mask selection, but right
now we do the most basic.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-17 07:59:14 -07:00
Alyssa Rosenzweig ac68946d9d panfrost: Identify and decode mfbd_flags
Previously known as the unk3 field.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-17 07:59:14 -07:00
Alyssa Rosenzweig 12d4289bf9 panfrost: Stub out hierarchy mask selection
Quite a bit of refactoring in the main driver will be necessary to make
use of this effectively, so the implementation is incomplete.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-17 07:59:14 -07:00
Alyssa Rosenzweig 6434f5c494 panfrost: Rename misc_0 -> tiler_polygon_list
Just for readability.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-17 07:59:14 -07:00
Alyssa Rosenzweig e2c2ccd5b8 panfrost: Sanity check tiler polygon list size
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-17 07:59:14 -07:00
Alyssa Rosenzweig 953cc4b540 panfrost: Compute and use polygon list body size
This is a bit of a hack, but it gets the point across.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-17 07:59:14 -07:00
Alyssa Rosenzweig b660953733 panfrost: Use polygon list header size computation
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-17 07:59:14 -07:00
Alyssa Rosenzweig edfba9bee2 panfrost: Calculate polygon list header size
As per the notes at the beginning of pan_tiler.c, we implement a routine
to calculate the size of the polygon list header given the framebuffer
dimensions and the provided hierarchy mask.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-17 07:59:14 -07:00
Alyssa Rosenzweig e88ff9ad85 panfrost: Add pan_tiler.h header
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-17 07:47:49 -07:00
Alyssa Rosenzweig 21eb411d2f panfrost: Document tile size heuristic
I'm not sure how the blob does it, but this seems to be a dead simple
test and roughly corresponds to what I've noticed from the blob, so
maybe it's good enough.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-17 07:47:49 -07:00
Alyssa Rosenzweig 7f26bb3553 panfrost: Rename tiler fields per tiler research
Following the research into Midgard's hierarchical tiling
infrastructure, we now understand (in broad stokes) the purpose of each
tiler field in the MFBD. Additionally, we understand more of the tiling
fields in the SFBD and in Bifrost's structures, although this knowledge
is still incomplete.

Update the names, decoder, and comments to reflect this new
understanding.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-17 07:47:49 -07:00
Alyssa Rosenzweig 8d6fb66e3a panfrost: Add notes about the tiler allocations
This explains how the polygon list is allocated, updating the headers
appropiately to sync the terminology.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-17 07:47:49 -07:00
Alyssa Rosenzweig 85e745f2b4 panfrost: Integrate kernel names for tiler FBD
These names are from the replay workaround in kbase; they begin to shine
some light on the meaning of these fields. In particular, we now
understand why the "tiler_meta" field has the effect it does on
performance in certain scenes (controlling tile granularity).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-17 07:47:49 -07:00
Bas Nieuwenhuizen 1a7caac9e9 radv: Add asserts that buffer descriptors are created with valid buffer formats.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-06-17 10:56:50 +00:00
Bas Nieuwenhuizen 4107590911 radv: Decompress DCC when the image format is not allowed for buffers.
Otherwise the buffer loads/stores in the bufimage meta operations fail.

If we decompress DCC then we can use the "canonical" format compatible
with the not-supported format.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-06-17 10:56:50 +00:00
Samuel Pitoiset e9875fc0b6 radv: make sure to init the DCC decompress compute path state
This fixes a segfault when forcing DCC decompressions on compute
because internal meta objects are not created since the on-demand
stuff.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-06-17 11:30:49 +02:00
Samuel Pitoiset 4c7ef1b02e ac: make ac_compute_cmask() a static function
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-By: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-06-17 11:30:47 +02:00
Samuel Pitoiset cf77d3abf1 radv: rely on ac_compute_cmask() for CMASK info
Instead of re-computing in the driver. The 3d and cube flags
are correctly set, so the same values should returned by
ac_compute_surface().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-06-17 11:30:44 +02:00