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154174 Commits

Author SHA1 Message Date
Marek Olšák 1fdc3b0fde radeonsi: move CS preamble emission into the winsys 
The preamble will be skipped by the kernel if there is no context switch.

Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
 2022-05-17 10:27:04 +00:00
Marek Olšák 32c7805ccc radeonsi: merge all preamble states into one 
Tess registers are appended. GS registers are appended or overwritten
if they are already set. There are separate TMZ and non-TMZ preambles.

The preamble will be passed to the kernel as an IB to execute on a context
switch only.

Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
 2022-05-17 10:27:04 +00:00
Marek Olšák f46cd73e29 radeonsi/gfx11: optimize attribute stores 
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
 2022-05-17 10:27:04 +00:00
Marek Olšák 9b20120d57 radeonsi/gfx11: fix VM faults due to the attribute ring 
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
 2022-05-17 10:27:04 +00:00
Marek Olšák c74d854348 Revert "radeonsi/gfx11: limit MSAA color buffers to the RGBA channel order" 
This reverts commit 54d85700a1.

It's an LLVM bug. If you disable AMDGPUImageIntrinsicOptimizer in LLVM,
MSAA is fixed. There is no LLVM command line option to disable it from Mesa.

Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
 2022-05-17 10:27:04 +00:00
Marek Olšák a529e4f7ad radeonsi/gfx11: fix the value of VGT_GS_OUT_PRIM_TYPE at the beginning of IBs 
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
 2022-05-17 10:27:04 +00:00
Marek Olšák a8d2ef8bd6 radeonsi/gfx11: don't insert shader code for GS_PIPELINE_STATS_EMU 
GS_PIPELINE_STATS_EMU is always false, so the branches were never entered.

Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
 2022-05-17 10:27:04 +00:00
Marek Olšák fcaa9f5096 radeonsi/gfx11: fix alpha-to-coverage with stencil or samplemask export 
We can't use UINT16_ABGR for the alpha channel. Always use 32_ABGR.

Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
 2022-05-17 10:27:04 +00:00
Marek Olšák ba02ed91a6 ac/gfx11: fix the scratch buffer 
We didn't use the value that we computed.

Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
 2022-05-17 10:27:04 +00:00
Marek Olšák af880e591e radeonsi: remove GFX9_MERGED_NUM_USER_SGPR definition 
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
 2022-05-17 10:27:04 +00:00
Marek Olšák 0eb48fa4e9 ac/gpu_info: silence a valgrind warning due to amdgpu_query_hw_ip_info 
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
 2022-05-17 10:27:04 +00:00
Samuel Pitoiset 9b4c346029 radv: more register changes on GFX11 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
 2022-05-17 10:08:17 +00:00
Samuel Pitoiset 7f31917119 radv: limit CP DMA to max 32KB sizes on GFX11 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
 2022-05-17 10:08:17 +00:00
Samuel Pitoiset 533df65e85 radv: apply a workaround for CB perf counters on GFX11 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
 2022-05-17 10:08:17 +00:00
Bas Nieuwenhuizen 0ce2401144 radv: update the initialization of SGPR0/1 registers for HS and GS on GFX11 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
 2022-05-17 10:08:17 +00:00
Samuel Pitoiset 31ec1ecc12 radv: update VRS registers on GFX11 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
 2022-05-17 10:08:17 +00:00
Samuel Pitoiset ab21ce46a6 radv: update TF_RING_size to a per-SE size on GFX11 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
 2022-05-17 10:08:17 +00:00
Samuel Pitoiset 995ab9a505 radv: do not emit FLUSH_AND_INV_DB_META on GFX11 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
 2022-05-17 10:08:17 +00:00
Samuel Pitoiset 2e3aec1633 radv: do not emit non-existent CP_COHER_START_DELAY on GFX11 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
 2022-05-17 10:08:17 +00:00
Samuel Pitoiset dcb324eb53 radv: configure DB_RENDER_CONTROL on GFX11 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
 2022-05-17 10:08:17 +00:00
Samuel Pitoiset 66882363b3 radv: use PIXEL_PIPE_STATE_DUMP event instead of ZPASS_DONE on GFX11 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
 2022-05-17 10:08:17 +00:00
Samuel Pitoiset 6026cf43b3 radv: update image descriptor registers on GFX11 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
 2022-05-17 10:08:17 +00:00
Samuel Pitoiset ef59e5b193 radv: update buffer descriptor registers on GFX11 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
 2022-05-17 10:08:17 +00:00
Samuel Pitoiset ebca4f2b3d radv: update sampler registers on GFX11 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
 2022-05-17 10:08:17 +00:00
Bas Nieuwenhuizen 670ee6023d radv: Disable transform feedback for gfx11. 
Until we implement it.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
 2022-05-17 10:08:17 +00:00
Bas Nieuwenhuizen c7f5da6829 radv: Add gfx11 DCC fast clear support. 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
 2022-05-17 10:08:17 +00:00
Bas Nieuwenhuizen cc2b3f3924 radv: Adjust for new SWIZZLE_ENABLE. 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
 2022-05-17 10:08:17 +00:00
Bas Nieuwenhuizen e96a35e6db radv: gfx11 register changes. 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
 2022-05-17 10:08:17 +00:00
Bas Nieuwenhuizen 9c391fe47e radv: Mark all formats as DCC compatible with each other on gfx11. 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
 2022-05-17 10:08:17 +00:00
Bas Nieuwenhuizen eb117a4711 radv: always enable NGG on GFX11 
The legacy path is removed.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
 2022-05-17 10:08:17 +00:00
Samuel Pitoiset 278e533ec9 radv: update scratch buffer registers on GFX11 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
 2022-05-17 10:08:17 +00:00
Samuel Pitoiset 6e4d9729cc radv: use the new format table on GFX11 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
 2022-05-17 10:08:17 +00:00
Samuel Pitoiset 2d02e210b5 radv: do not align VGPRS to 8 or 16 on GFX11 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
 2022-05-17 10:08:17 +00:00
Tomeu Vizoso 9e031426be panvk/ci: Disable CI for a while 
We have been hitting OOM conditions quite often and this is making ti
hard to get stuff merged.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16554>
 2022-05-17 09:16:21 +00:00
Tomeu Vizoso e5acf8016d lima/ci: Disable lima-mali450-piglit-gpu:arm64 
Due to a kernel regression, these jobs fail most of the time with the
backtrace below.

Disable while we get a fix in our kernel.

2022-05-17 08:00:15.428691: [  374.755841] ------------[ cut here ]------------
2022-05-17 08:00:15.428778: [  374.755883] kernel BUG at kernel/irq_work.c:235!
2022-05-17 08:00:15.429011: [  374.759409] Internal error: Oops - BUG: 0 [#1] PREEMPT SMP
2022-05-17 08:00:15.429077: [  374.764842] Modules linked in: ipv6
2022-05-17 08:00:15.429233: [  374.768294] CPU: 3 PID: 18210 Comm: vp-bad-program Not tainted 5.16.12linux-v5.16-for-mesa-ci-991fec6622591.tar.bz2 #1
2022-05-17 08:00:15.429386: [  374.778900] Hardware name: Libre Computer AML-S805X-AC (DT)
2022-05-17 08:00:15.429536: [  374.784421] pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
2022-05-17 08:00:15.429714: [  374.791320] pc : irq_work_run_list+0x64/0x70
2022-05-17 08:00:15.429780: [  374.795546] lr : irq_work_run+0x38/0x50
2022-05-17 08:00:15.429927: [  374.799342] sp : ffff80000801bf30
2022-05-17 08:00:15.430097: [  374.802618] x29: ffff80000801bf30 x28: ffff000003398e00 x27: ffff00000ed3e400
2022-05-17 08:00:15.430158: [  374.809691] x26: ffff800009678750 x25: ffff0000030d8900 x24: ffff800008846fa0
2022-05-17 08:00:15.430316: [  374.816763] x23: ffff800009909f80 x22: 0000000000000006 x21: ffff00000101e780
2022-05-17 08:00:15.430411: [  374.823836] x20: ffff800009d7c408 x19: ffff8000099089c8 x18: 0000000000000000
2022-05-17 08:00:15.430547: [  374.830908] x17: ffff8000252e9000 x16: ffff80000801c000 x15: 0000000000004000
2022-05-17 08:00:15.430735: [  374.837981] x14: 0000000000000000 x13: 0000000000000000 x12: 0000000000000001
2022-05-17 08:00:15.430797: [  374.845054] x11: 0000000000000001 x10: ffff8000252e9000 x9 : ffff00002ebf90e0
2022-05-17 08:00:15.430962: [  374.852126] x8 : fffffc00000eda08 x7 : ffff000003398e00 x6 : 0000000000001000
2022-05-17 08:00:15.431029: [  374.859199] x5 : 0000000000000000 x4 : ffff00002ebfc910 x3 : ffff00000ed3e430
2022-05-17 08:00:15.431194: [  374.866271] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff00002ebf19c8
2022-05-17 08:00:15.431261: [  374.873345] Call trace:
2022-05-17 08:00:15.431409: [  374.875761]  irq_work_run_list+0x64/0x70
2022-05-17 08:00:15.431557: [  374.879641]  ipi_handler+0x98/0x15c
2022-05-17 08:00:15.431726: [  374.883091]  handle_percpu_devid_irq+0x88/0x140
2022-05-17 08:00:15.431795: [  374.887576]  generic_handle_domain_irq+0x40/0x60
2022-05-17 08:00:15.431958: [  374.892147]  gic_handle_irq+0x48/0xd0
2022-05-17 08:00:15.432025: [  374.895769]  call_on_irq_stack+0x2c/0x60
2022-05-17 08:00:15.432211: [  374.899651]  do_interrupt_handler+0x80/0x84
2022-05-17 08:00:15.432364: [  374.903791]  el1_interrupt+0x34/0x84
2022-05-17 08:00:15.432432: [  374.907327]  el1h_64_irq_handler+0x1c/0x30
2022-05-17 08:00:15.432616: [  374.911380]  el1h_64_irq+0x78/0x7c
2022-05-17 08:00:15.432764: [  374.914744]  irq_work_queue+0x70/0x80
2022-05-17 08:00:15.432832: [  374.918367]  drm_sched_entity_fini+0x290/0x320
2022-05-17 08:00:15.433043: [  374.922766]  lima_sched_context_fini+0x18/0x24
2022-05-17 08:00:15.433161: [  374.927164]  lima_ctx_free+0x7c/0x114
2022-05-17 08:00:15.433228: [  374.930787]  lima_ioctl_ctx_free+0x28/0x40
2022-05-17 08:00:15.433362: [  374.934840]  drm_ioctl_kernel+0xc4/0x170
2022-05-17 08:00:15.433522: [  374.938721]  drm_ioctl+0x21c/0x440
2022-05-17 08:00:15.433587: [  374.942085]  __arm64_sys_ioctl+0xac/0xf0
2022-05-17 08:00:15.433748: [  374.945966]  invoke_syscall+0x48/0x114
2022-05-17 08:00:15.433814: [  374.949675]  el0_svc_common.constprop.0+0x44/0xec
2022-05-17 08:00:15.433977: [  374.954332]  do_el0_svc+0x28/0x90
2022-05-17 08:00:15.434041: [  374.957609]  el0_svc+0x20/0x60
2022-05-17 08:00:15.434204: [  374.960629]  el0t_64_sync_handler+0x1a8/0x1b0
2022-05-17 08:00:15.434269: [  374.964941]  el0t_64_sync+0x1a0/0x1a4
2022-05-17 08:00:15.434492: [  374.968568] Code: a8c27bfd d50323bf d65f03c0 d65f03c0 (d4210000)
2022-05-17 08:00:15.434612: [  374.974607] ---[ end trace 74ef9d6ff9457a3f ]---
2022-05-17 08:00:15.434676: [  374.979174] Kernel panic - not syncing: Oops - BUG: Fatal exception in interrupt
2022-05-17 08:00:15.434888: [  374.986505] SMP: stopping secondary CPUs
2022-05-17 08:00:15.435011: [  374.990391] Kernel Offset: 0x80000 from 0xffff800008000000
2022-05-17 08:00:15.435079: [  374.995818] PHYS_OFFSET: 0x0
2022-05-17 08:00:15.435243: [  374.998665] CPU features: 0x00,00004802,00000846
2022-05-17 08:00:15.435313: [  375.003236] Memory Limit: none
2022-05-17 08:00:15.435488: [  375.006258] ---[ end Kernel panic - not syncing: Oops - BUG: Fatal exception in interrupt ]---

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16554>
 2022-05-17 09:16:21 +00:00
Kenneth Graunke b637f6c3db intel/decoder: Fix binding table pointer decoding with large offsets 
XeHP supports a 20:5 pointer format, so the offset can legitimately
be more than UINT16_MAX.  Likewise, with 256B binding table mode on
Icelake/Tigerlake, we might have 18:8 pointers that exceed UINT16_MAX.

Thanks to Felix DeGrood for catching this!

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16538>
 2022-05-17 08:52:00 +00:00
Pierre-Eric Pelloux-Prayer 8779a5b84c glx: set max values for pbuffer width / height 
Without this change the values are always 0. This breaks
Maya which uses this value to create a pbuffer (and then
fails).

This commit is based on b91e1e38e8 which does the same
for EGL.

Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16496>
 2022-05-17 07:21:34 +00:00
David Heidelberg d22eeb5ae0 ci/iris: skqp: remove flaking atlastext for TGL 
Example:
 - https://gitlab.freedesktop.org/mesa/mesa/-/jobs/22380389#L4349
 - https://mesa.pages.freedesktop.org/-/mesa/-/jobs/22380389/artifacts///results/gles/report.html

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6460
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16407>
 2022-05-17 06:57:19 +00:00
David Heidelberg 317496ba8a ci/iris: skqp: add default GLES rendertests for TGL 
Import the intact whole rendertest file from skqp (branch
android-cts-12.1_r1) to be able remove the offending test line in the
following commit.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16407>
 2022-05-17 06:57:19 +00:00
Dave Airlie a179e1aede aco/radv: drop radv_nir_compiler_options from aco. 
Add a new aco input and options structs, then convert from radv
pieces on submit.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16521>
 2022-05-17 06:15:25 +00:00
Dave Airlie 8198900071 ac/radv: drop info pointer from the ac and radv shader structs 
This was being used for one bool, just pass the bool.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16521>
 2022-05-17 06:15:25 +00:00
Mike Blumenkrantz 55845409f2 zink: add tu baseline for a630 
oof

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16549>
 2022-05-17 06:04:31 +00:00
Mike Blumenkrantz fffafa3635 zink: move get_timestamp to screen 
this doesn't need to use a particular context

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16529>
 2022-05-17 03:46:56 +00:00
Mike Blumenkrantz 0befc259a6 zink: use copy context to eliminate dependency on EXT_calibrated_timestamps 
this is unsupported by a surprising number of drivers

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16529>
 2022-05-17 03:46:56 +00:00
Mike Blumenkrantz 9d30d82a9a zink: fix init with MESA_SHADER_CACHE_DISABLE enabled 
Fixes: ba2f5cb20a ("zink: check for error when initializing util_queue")

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16533>
 2022-05-17 03:31:10 +00:00
Mike Blumenkrantz e303898258 zink: manually validate shaders in debug builds 
VVL is great, but there's actually cases where it doesn't catch critical
spirv errors, so add in our own validation pass to make sure things are
okay

this is especially useful for running on nvidia, as their compiler will
either crash on or silently drop illegal instructions

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16462>
 2022-05-17 02:55:20 +00:00
Mike Blumenkrantz 8c8e6e953f spirv: fix barrier scope assert 
glslang generates barriers with QueueFamily, so this is totally legal

cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16462>
 2022-05-17 02:55:20 +00:00
Mike Blumenkrantz 5f83571f92 lavapipe: fix pipeline handling for dynamic render zs state with pipeline library 
this is slightly more nuanced: if this is ONLY a fragment state,
pDepthStencilState must exist, but if it's BOTH fragment and output,
then pDepthStencilState must only exist if zs attachment is used

Fixes: d4d5a7abba ("lavapipe: implement EXT_graphics_pipeline_library")

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16457>
 2022-05-17 02:44:01 +00:00
Mike Blumenkrantz 0b2d383316 lavapipe: ignore depth/stencil states if attachment is not present 
depth and stencil states should only be set if the corresponding attachment
is present, otherwise they should be ignored. this is different from
ignoring the entire VkPipelineDepthStencilStateCreateInfo struct, as
it's possible that only depth or only stencil may be present

cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16457>
 2022-05-17 02:44:01 +00:00
Timothy Arceri 77392e4983 vc4: disable GLSL IR loop unrolling 
NIR loop unrolling is already enabled so just let it do its job.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16543>
 2022-05-17 02:12:21 +00:00