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153131 Commits

Author SHA1 Message Date
Lionel Landwerlin 44e93b4c6f anv: fix clflush usage on utrace copy batch 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: cc5843a573 ("anv: implement u_trace support")
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15780>
 2022-05-02 12:07:01 +00:00
Pierre-Eric Pelloux-Prayer 529f316d87 radeonsi: fix VS kill_outputs handling 
981bd8cbe2 moved outputs removing handling to NIR, but instead of
applying it only to the last stage before the FS this now applies
it to both the GS and the VS.

This commit fixes this by clearing the kill_outputs field for
the VS when using a ES-GS shader.

Fixes: 981bd8cbe2 ("radeonsi: apply key.ge.opt.kill_{outputs,pointsize,clipdistance} in NIR")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16249>
 2022-05-02 13:41:39 +02:00
Rhys Perry 8a525c0fa5 radv: consider radix sort shaders to be internal/meta 
Cleans up RADV_DEBUG=shaders

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16198>
 2022-05-02 10:19:23 +00:00
Iago Toral Quiroga c9f68361a8 v3dv: ignore barriers for image layout transitions from undefined layouts 
Layout transitions are not relevant to us, we only care about barriers
that involve a sync point between read/write actions on the image across
GPU jobs.

Image transitions from undefined layout can only happen before the image
is ever used by the GPU, which means they are never relevant to our
implementation.

This improves performance in vkQuake.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16235>
 2022-05-02 08:04:13 +02:00
Iago Toral Quiroga a44d498287 v3dv: document Vulkan requirements for signaling operations 
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16235>
 2022-05-02 08:04:13 +02:00
Iago Toral Quiroga 0273f661e6 v3dv: don't emit final noop job if we don't have anything to signal 
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16235>
 2022-05-02 08:04:13 +02:00
Iago Toral Quiroga de0d4d671a v3dv: drop obsolete comment 
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16235>
 2022-05-02 08:04:13 +02:00
Iago Toral Quiroga c367bd0ee3 v3dv: ignore no-op barriers 
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16235>
 2022-05-02 08:04:13 +02:00
Alyssa Rosenzweig 31fd926334 agx: Lower mediump flat shading 
This isn't supported by the hardware. Fixes

dEQP-GLES2.functional.shaders.constants.float_uniform_vertex

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig 18ef9398de agx: Remove nir_register support 
We don't use it anymore, now that we can handle SSA form. Gets rid of
the most gross hack in the compiler.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig 3927a9e911 agx: Remove has_liveness 
Given we do no metadata tracking, this is an accident waiting to happen.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig 1c6bd0357f agx: Update RA comment 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig 6b22bbab36 agx: Add validation pass 
For now, just check that we didn't botch the structure of the block,
since this just bit me.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig 4498799822 agx: Remove identity moves 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig c712043b9c agx: Unit test parallel copy lowering 
It's pretty tricky.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig 6a4d742369 agx: Always use hash table for extracts 
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig 860832e41b agx: Split up RA from post-RA lowering 
This allows us to validate results in the middle.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig ea065537cb agx: Lower phi nodes to parallel copies 
Now we have an SSA RA :-)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig ccb0210761 agx: Don't lower phis in NIR 
We're ready for them now! Just scalarize.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig a8da17f628 agx: Copy prop into phi nodes 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig 8ff0a29baf agx: Translate phi nodes 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig 4791dc9125 agx: Make DCE dumber 
The current DCE pass hits issue around phi nodes. These need to be
solved properly eventually, but for now workaround them by doing
something obviously correct (but suboptimal compile time).

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig 606d9340f3 agx: Adapt liveness analysis for SSA 
Lifted from nir_liveness.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig 590df764d6 agx: Introduce worklist infrastructure 
Using the common NIR stuff.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig e414a8c16f agx: Add agx_after_block_logical helper 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig a2a947031a agx: Mark the logical ends of blocks 
We need to insert parallel copies at the logical end of blocks, before branches.
Add a pseudo instruction signaling that. Cribbed from ACO.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig 5be26e8624 agx: Add predecessor index helper 
To order phi sources.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig 3f1e926bf4 agx: Use a dynarray for predecessors 
This imposes a fixed ordering, allowing phi sources to be implicitly ordered.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig d02e913e95 agx: Remove else optimization 
It will conflict with SSA-based RA and needs to be rewritten to happen
late.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig 4d79f6ca76 agx: Use extract helper for tex internally 
Allows better optimization.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig 4f78141c77 agx: Emit splits for intrinsics 
This allows optimizing the extracts.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig d06394095b agx: Optimize p_split(kill) specially 
Let's make sure these are allocated optimally.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig e16ad8f443 agx: Lower p_split after RA 
Using existing regalloc infrastructure.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig 4fc023ed42 agx: Use a transfer graph for parallel copies 
Lifted from ir3. Algorithm is the same; the data structures and interface are
lightly modified to decouple from ir3's IR.

Sequentializing parallel copies after RA is tricky. ir3's implementation works
well enough, so I use that one.

Original implementation by Connor Abbott.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig 330ec4260d agx: Add helper to emit splits 
This should be used for vector destinations, to facilitate the extraction
optimization.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 21:58:29 -04:00
Alyssa Rosenzweig b30c718a57 agx: Add helper to emit combines 
...in such a way that subsequent extracts will be optimized.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 21:58:29 -04:00
Alyssa Rosenzweig 5bc65ef963 agx: Add a hash table for vector extracts 
This will allow us to introduce splits gradually, giving a graceful fallback.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 21:58:29 -04:00
Alyssa Rosenzweig d285c63417 agx: Add phi pseudo instruction 
For SSA.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 21:58:29 -04:00
Alyssa Rosenzweig 2a4a8a8902 agx: Add p_split pseudoinstruction 
Easier on RA for extracts.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 21:58:29 -04:00
Alyssa Rosenzweig bb1fb0a9db agx: Dynamically allocate agx_instr->src 
Required for phi nodes.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 21:58:29 -04:00
Alyssa Rosenzweig d39b1c3426 agx: Implement simple copyprop 
Cleans up some of the mess.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 21:58:29 -04:00
Alyssa Rosenzweig 7d38bcb7ee agx: Use pseudo ops for mov/not/and/xor/or 
Rather than using builder magic (implicitly lowered on emit), add actual pseudo
operations (explicitly lowered before encoding). In theory this is slower, I
doubt it matters. This makes the instruction aliases first-class for IR prining
and machine inspection, which will make optimization passes easier to write.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 21:58:29 -04:00
Alyssa Rosenzweig 3d8c2f2693 agx: Add unit test infrastructure 
Lifted from Bifrost. Add some basic optimizer tests (they pass!) to show the
compiler is ready to be unit tested. Given we can't have hardware CI for Asahi
yet -- and dEQP is still pretty janky -- unit testing should prove quite useful.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 21:58:29 -04:00
Alyssa Rosenzweig 43c701424b agx: Wrap compiler header in extern "C" 
So we can use it from GTest.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 21:58:29 -04:00
Alyssa Rosenzweig f0a973081f agx: Use correct types for some IR enums 
Otherwise there are implicit int->enum casts which prevent us from building as
C++ (with -fpermissive).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 21:58:29 -04:00
Alyssa Rosenzweig b87ce10210 agx: Match order for designated initializers 
Required to compile our headers with C++, to allow us to use GTest unit tests.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 21:58:29 -04:00
Alyssa Rosenzweig ff660dd637 agx: Track write registers more accurately 
We may not write a full 32-bit vec4, don't be so pessimistic.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 21:58:29 -04:00
Alyssa Rosenzweig 0c82b5c99c agx: Note that RA proceeds in dominance-order 
This is an important invariant for SSA-based RA to work.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 21:58:29 -04:00
Alyssa Rosenzweig 81477f3809 agx: Implement some shader-db stats 
Instructions, bytes, and registers -- this should hold us over until we
can reverse the underlying uarch and get proper cycle estimations.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 21:58:29 -04:00
Alyssa Rosenzweig 31b3f56813 asahi: Workaround broken GLSL compiler 
https://gitlab.freedesktop.org/mesa/mesa/-/issues/6075 still hasn't been
fixed (despite the bug being known for a year now..)

Workaround the brokenness.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 21:56:21 -04:00