Commit Graph

155097 Commits

Author SHA1 Message Date
Martin Roukala (né Peres) e58c455ca9 radv/ci: bump the timeout of vangogh/renoir
The execution time of vkcts has drastically changed with the latest
update, especially for APUs. This commit bumps the timeout to give
them a chance to finish.

Fixes: 836ce97f5e (ci: bump VK-GL-CTS to 1.3.2.0)
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16810>
2022-06-02 08:29:31 +00:00
Samuel Pitoiset 5af1409c1b radv: fix lowering GS intrinsics if NGG is disabled per pipeline
If NGG is disabled per pipeline for extreme (or suboptimal) geometry
or with transform feedback, make sure to not lower GS intrinsics that
are only needed for NGG GS. This means we have to lower GS intrinsics
later in the compilation process to effectively know if the pipeline
uses NGG.

fossils-db (Navi21):
Totals from 8 (0.01% of 134913) affected shaders:
VGPRs: 512 -> 520 (+1.56%)
CodeSize: 58180 -> 65080 (+11.86%); split: -0.04%, +11.90%
MaxWaves: 128 -> 126 (-1.56%)
Instrs: 10525 -> 11779 (+11.91%); split: -0.05%, +11.96%
Latency: 62941 -> 49428 (-21.47%); split: -21.59%, +0.12%
InvThroughput: 16121 -> 12950 (-19.67%); split: -19.96%, +0.29%
VClause: 122 -> 123 (+0.82%); split: -0.82%, +1.64%
SClause: 130 -> 143 (+10.00%)
Copies: 566 -> 596 (+5.30%); split: -0.35%, +5.65%
Branches: 200 -> 208 (+4.00%)
PreSGPRs: 424 -> 422 (-0.47%)
PreVGPRs: 430 -> 424 (-1.40%); split: -1.63%, +0.23%

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15885>
2022-06-02 09:42:54 +02:00
Dylan Baker a5549ebe5b docs: update calendar and link releases notes for 22.0.5
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16828>
2022-06-01 16:55:58 -07:00
Dylan Baker 7bd8efb74f docs: update sha256 for 22.0.5
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16828>
2022-06-01 16:55:22 -07:00
Dylan Baker a6e546ab51 docs: add release notes for 22.0.5
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16828>
2022-06-01 16:55:21 -07:00
Dylan Baker 67280a4019 docs: update calendar and link releases notes for 22.1.1
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16828>
2022-06-01 16:55:17 -07:00
Dylan Baker 27a1c477c9 docs: Add sh256sums for 22.1.1
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16828>
2022-06-01 16:55:11 -07:00
Dylan Baker 3e4de308a5 docs: add release notes for 22.1.1
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16828>
2022-06-01 16:55:09 -07:00
Jesse Natalie 1ef329b825 wgl, d3d12: Handle front buffer writes for double-buffered MSAA surfaces backed by swapchains
We don't need to go as far as the fake front thing when MSAA is being used, because the
swapchain (single-sampled) is already decoupled from the app render buffers. But we do
need to direct the frontbuffer flush to the single-sampled back buffer, and then present
the back buffer. We also need to swap the buffers when we do this, so the next blit
targets the former front buffer.

Reviewed-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16227>
2022-06-01 16:18:12 -07:00
Emma Anholt 49dc60efa1 freedreno/ir3: Fold 16-bit conversions into image load/store src/dsts.
Shaves 5 instructions off of one manhattan31 shader.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16616>
2022-06-01 22:19:44 +00:00
Emma Anholt f005a2d786 freedreno/ir3: Fix validation of half-precision image store values.
ce1a381e57 ("turnip: enable VK_KHR_16bit_storage on A650") determined
that the type of the instr decided the type of the value being stored in
the ".b" case.  But it would be surprising if image stores had the type
determine the coordinates' precision instead of the value's, and once we
turned on image instruction precision lowering we ran into asserts.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16616>
2022-06-01 22:19:44 +00:00
Matt Turner 003327dd95 freedreno/ir3: Pass 16-bit sampler coordinates when possible.
shader-db highlights from Rob's android shaders:

total instructions in shared programs: 769641 -> 767536 (-0.27%)
instructions in affected programs: 151139 -> 149034 (-1.39%)
total last-baryf in shared programs: 55908 -> 55607 (-0.54%)
last-baryf in affected programs: 35219 -> 34918 (-0.85%)
total sstall in shared programs: 67074 -> 65767 (-1.95%)
total full in shared programs: 36115 -> 36080 (-0.10%)
full in affected programs: 203 -> 168 (-17.24%)
sstall in affected programs: 9510 -> 8203 (-13.74%)
total (ss) in shared programs: 14380 -> 14239 (-0.98%)
(ss) in affected programs: 2965 -> 2824 (-4.76%)
total systall in shared programs: 92425 -> 91522 (-0.98%)
systall in affected programs: 13146 -> 12243 (-6.87%)
total (sy) in shared programs: 4330 -> 4314 (-0.37%)
(sy) in affected programs: 167 -> 151 (-9.58%)
total waves in shared programs: 71580 -> 71584 (<.01%)
waves in affected programs: 12 -> 16 (33.33%)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16616>
2022-06-01 22:19:44 +00:00
Emma Anholt ac24c49c37 freedreno/ir3: Make the types of tex coord padding match.
Required for lowering of coords to be 16-bit.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16616>
2022-06-01 22:19:44 +00:00
Matt Turner edb0904775 freedreno/ir3: Move the texture array coord fixup to nir
We're going to optimize sampler coordinates to FP16, so we'll need to
add the appropriately typed 0.5. Move this to NIR where that information
is readily available.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16616>
2022-06-01 22:19:44 +00:00
Emma Anholt bf49d4a084 freedreno/ir3: Enable load/store vectorization for SSBO access, too.
Saves a few ldib/stib instructions in gfxbench vk-5-normal compute shaders
by grouping vec4 accesses together.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16616>
2022-06-01 22:19:44 +00:00
Emma Anholt 6e087f96c9 nir_lower_mediump: Drop assertion about not containing movs.
A 1D texture operation may need to do a mov to turn a reference to a
channel of an SSA value into a scalar value to be passed as the texture
coordinate (since texture srcs can't do swizzles).  Seen in
amnesia-the-dark-descent/low/46.shader_test() for example, where a 1D
texture is used to remap each of r,g,b from a previous texture result.

Besides, the nir_op_is_vec() case will (perhaps surprisingly) look through
a mov, anyway.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16616>
2022-06-01 22:19:44 +00:00
Emma Anholt 5f64bc7a3e ci/turnip: Add missing xfails for a618 full VK run
Fixes: 836ce97f5e ("ci: bump VK-GL-CTS to 1.3.2.0")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16616>
2022-06-01 22:19:44 +00:00
Yiwei Zhang 1c63a0beaf venus: resolve AHARDWAREBUFFER_FORMAT_Y8Cb8Cr8_420 to external format
This is to work around ANGLE yuv support.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16759>
2022-06-01 20:25:47 +00:00
Alyssa Rosenzweig bc4d42023d pan/bi: Respect swizzles in nir_op_pack_64_2x32_split
Triggered a BIR validation error, which made debugging a breeze. That validation
pass (dimensionality checks) gets a lot of use, it seems :-)

Fixes:

   dEQP-VK.ssbo.layout.2_level_array.std430.row_major_mat4x2_comp_access_store_cols

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16724>
2022-06-01 20:08:42 +00:00
Alyssa Rosenzweig 7831508740 panvk: Use vk_image_subresource_*_count for clears
This handles VK_REMAINING_* for us, instead of underflowing and clearing no
levels/layers.

Fixes dEQP-VK.api.image_clearing.core.clear_color_image.2d.linear.single_layer.*

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16724>
2022-06-01 20:08:42 +00:00
Alyssa Rosenzweig 9ddfcbfbc6 panfrost: Allow 2D AFBC on Valhall
2D AFBC should be working now, flip the switch. 3D AFBC needs more research to
get right, honestly it's not clear how 3D AFBC on Bifrost is working...

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16800>
2022-06-01 19:44:31 +00:00
Alyssa Rosenzweig 82d3eb7f18 panfrost: Handle texturing from AFBC on Valhall
We need to pack special AFBC-specific plane descriptors instead of the generic
plane descriptor. Nothing too fancy here, though.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16800>
2022-06-01 19:44:31 +00:00
Alyssa Rosenzweig 9afa8cc555 panfrost: Support rendering to AFBC on Valhall
Add the required handling when packing render target and depth buffer
descriptors on Valhall. This is mostly equivalent to Bifrost.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16800>
2022-06-01 19:44:31 +00:00
Alyssa Rosenzweig c2207d27c2 panfrost: Add pan_afbc_compression_mode on Valhall
Map a canonical format (a hardware-independent pipe_format) to a compression
mode (Valhall-specific hardware enum defined in GenXML). To be used for packing
plane descriptors and render target descriptors when AFBC is in use on Valhall.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16800>
2022-06-01 19:44:31 +00:00
Alyssa Rosenzweig 87dcdbdad6 panfrost: Pass arch instead of dev into afbc_format
For callers that have a device object, it's easy to pass dev->arch instead of
dev. But this requires callers to have a reference to the device, which is
tricky for callers that only have the arch via PAN_ARCH. Pass dev->arch instead
of dev to accommodate them.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16800>
2022-06-01 19:44:31 +00:00
Alyssa Rosenzweig 2cc2f217d4 panfrost: Fix XML for AFBC header on v9
Misnamed field due to copy/paste fail from Bifrost.

Fixes: c011ea6c26 ("panfrost: Shuffle render target AFBC for Valhall")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16800>
2022-06-01 19:44:31 +00:00
Alyssa Rosenzweig e596a0423b pan/mdg: Print outmods when printing IR
In particular, this lets us distinguish mul_high from regular mul.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16798>
2022-06-01 14:24:10 -04:00
Alyssa Rosenzweig a099834b97 pan/mdg: Distinguish SSA vs reg when printing IR
This makes it easy to match the printed IR with the indices in the NIR.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16798>
2022-06-01 14:24:10 -04:00
Alyssa Rosenzweig 520204ae18 pan/mdg: Only print 1 source for moves
This makes the printed IR easier to read at a glance.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16798>
2022-06-01 14:24:10 -04:00
Alyssa Rosenzweig 0ee24c46e0 pan/mdg: Only print 2 sources for ALU
..and assert the other sources are null. The one place this might fail in the
future is for real FMA, but we don't support that for GL.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16798>
2022-06-01 14:24:10 -04:00
Alyssa Rosenzweig 9c9db27e3c pan/mdg: Only print masked components of swizzle
This matches the IR printer with the disassembler, making the output of the IR
printer much easier to parse at a glance.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16798>
2022-06-01 14:24:10 -04:00
Alyssa Rosenzweig c9093554d0 pan/mdg: Use "<<" instead of "lsl"
Easier to read and consistent with C code.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16798>
2022-06-01 14:24:10 -04:00
Alyssa Rosenzweig 8c11f4809b pan/mdg: Remove uppercase write masks
These do not convey any additional information, and fail to account for
shrinking. In particular, a 64-bit writemask with .keephi would fail to
disassemble and instead trip the assertion, since that would be the ZW
components. Just delete the broken code.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16798>
2022-06-01 14:24:10 -04:00
Alyssa Rosenzweig 9e4b457958 pan/mdg: Scalarize with 64-bit sources
Otherwise, we can get vec3 with u2u32 with 64-bit sources which we need lowered.
Since our current approach is "scalarize all 64-bit ops", we need to check for
conversions too.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16798>
2022-06-01 14:24:05 -04:00
Georg Lehmann 1d815548ab radv, aco: Packed usub_sat/isub_sat.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
2022-06-01 17:09:25 +00:00
Georg Lehmann aa9d2d8893 radv: Enable VK_INTEL_shader_integer_functions2.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
2022-06-01 17:09:25 +00:00
Georg Lehmann 55735ed728 radv: Lower 8bit isub_sat/usub_sat.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
2022-06-01 17:09:25 +00:00
Georg Lehmann 4e6667ea87 radv: Lower hadd/hradd.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
2022-06-01 17:09:25 +00:00
Georg Lehmann cc3f03b757 radv: Lower mul_32x16.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
2022-06-01 17:09:25 +00:00
Georg Lehmann bfc25d6ec9 nir: Add optional lowering for mul_32x16.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
2022-06-01 17:09:25 +00:00
Georg Lehmann 83f51212c1 ac/llvm: Implement uclz.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
2022-06-01 17:09:25 +00:00
Georg Lehmann 8671b866bf ac/llvm: Implement usub_sat and isub_sat.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
2022-06-01 17:09:25 +00:00
Georg Lehmann d404f1964c aco: Implement isub_sat.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
2022-06-01 17:09:25 +00:00
Georg Lehmann faa2a89487 aco: Implement usub_sat.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
2022-06-01 17:09:25 +00:00
Georg Lehmann 529ec3d7dc aco: Implement uclz.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
2022-06-01 17:09:25 +00:00
Danylo Piliaiev 79e266fffc ir3: Force late-z if FS has global store/atomic
No known tests are fixed.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16816>
2022-06-01 16:30:36 +00:00
Alyssa Rosenzweig 5067a26f44 pan/bi: Use flow control lowering on Valhall
Logically at the same part of the compile pipeline as clause scheduling on
Bifrost. Lots of similarities, too. Now that we generate flow control only as a
late pass, various hacks in the compiler are no longer necessary and are
dropped.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>
2022-06-01 16:14:38 +00:00
Alyssa Rosenzweig a394c32cd2 pan/va: Unit test flow control merging
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>
2022-06-01 16:14:38 +00:00
Alyssa Rosenzweig 4b06e7f5b6 pan/va: Unit test flow control insertion
Test that we correctly track the scoreboard, helper invocations, reconvergence,
and ends and insert NOPs to effect this expected flow control.

As the pass inserts NOPs but does not otherwise modify the shader, this is easy
to test with well-defined behaviour of the pass.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>
2022-06-01 16:14:38 +00:00
Alyssa Rosenzweig 0fa9204049 pan/va: Respect assigned slots
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>
2022-06-01 16:14:38 +00:00