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90463 Commits

Author SHA1 Message Date
Marek Olšák 354285afa0 radeonsi/gfx9: fix textureSize/imageSize for 1D textures 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák 566defad13 radeonsi/gfx9: add a workaround for 1D depth textures 
The same workaround is used by Vulkan.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák fc3c503b5d radeonsi/gfx9: enable clamping for Z UNORM formats promoted to Z32F 
so that shaders don't have to do it.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák 5abf60076c radeonsi/gfx9: image descriptor changes in mutable fields 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák c8ffec4f4b radeonsi/gfx9: FMASK image descriptor changes 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák d60f72a9f0 radeonsi/gfx9: image descriptor changes in immutable fields 
The border color swizzle logic was copied from Vulkan. It doesn't make any
sense to me, but it passes all piglits except the stencil ones.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák dfd2b54948 radeonsi/gfx9: DB changes 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák 94819a3e6c radeonsi/gfx9: CB changes 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák 272b50a6f4 radeonsi/gfx9: do DCC clears on non-mipmapped textures only 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák aba8e0ea68 radeonsi/gfx9: update can_sample_z/s flags 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák 054dcbe42c radeonsi/gfx9: pass correct parameters to buffer_get_handle 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák 710aaed52b radeonsi/gfx9: update si_set_optimal_micro_tile_mode 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák 7fcad40ca5 radeonsi/gfx9: don't check array_mode for allowing TC-compatible HTILE 
GFX9 supports this with all modes except linear.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák 6f09b0d076 radeonsi/gfx9: update HTILE/CMASK/FMASK allocators 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák 281542c690 radeonsi/gfx9: stub testdma - array_mode_to_string 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák a0e8b73594 radeonsi/gfx9: update r600_print_texture_info 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák b25d7c2cbf gallium/radeon: move pre-GFX9 radeon_bo_metadata.* to u.legacy.* 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák 9b365d497a winsys/amdgpu: set num_tile_pipes, pipe_interleave_bytes for GFX9 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák 493de7f935 winsys/amdgpu: wire up new addrlib for GFX9 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák e572835fea winsys/amdgpu: update amdgpu_addr_create for GFX9 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák a71139470c winsys/amdgpu: rename GFX6 surface functions 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák 9ca33ab78e gallium/radeon: add GFX9 surface info to radeon_surf 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák ba2e7c68ce gallium/radeon: move pre-GFX9 radeon_surf.* members to radeon_surf.u.legacy.* 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák 641b79774a radeonsi/gfx9: allow Z16_UNORM for TC-compatible HTILE 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák a4f0a1099f radeonsi/gfx9: draw changes 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák b39fade67c radeonsi/gfx9: pad shader binaries by 128 bytes 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák 5271d12a6e radeonsi/gfx9: trivial shader and ring changes 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák 0aae4f4764 radeonsi/gfx9: sampler state changes 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák 71eca0780a radeonsi/gfx9: add a scissor bug workaround 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák b576df4017 radeonsi/gfx9: rasterizer changes 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák be8eba0625 radeonsi/gfx9: disable the 2-bit format fetch fix 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák 31b1042276 radeonsi/gfx9: set NUM_RECORDS correctly 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák 5f4659260e radeonsi/gfx9: ELEMENT_SIZE change 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák d214b95e9a radeonsi/gfx9: enable ETC2 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák 6d21fd51b6 radeonsi/gfx9: disable RB+ on Vega10 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák 2862300d9e radeonsi/gfx9: init_config changes 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák b054718218 radeonsi/gfx9: don't set PA_SC_RASTER_CONFIG* 
The registers don't exist on GFX9.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák de7967a27a radeonsi/gfx9: Gather4 no longer needs the workaround 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák 71ad666414 radeonsi/gfx9: CP DMA changes 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák 7690196135 radeonsi/gfx9: query changes - EVENT_WRITE and SET_PREDICATION 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák ea9cf0a322 radeonsi/gfx9: EVENT_WRITE_EOP -> RELEASE_MEM 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák 3e3d4f5e1d radeonsi/gfx9: INDIRECT_BUFFER change 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák 9680a75489 radeonsi/gfx9: enable SDMA buffer copying & clearing 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák c9b004af58 radeonsi/gfx9: handle GFX9 in a few places 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák 92112ec296 radeonsi/gfx9: don't read back non-existent SRBM registers 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák ef97cc0cae radeonsi/gfx9: add IB parser support 
Both GFX6 and GFX9 fields are printed next to each other in parsed IBs.

The Python script parses both headers like one stream and tries to merge
all definitions.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák 9338ab0afd radeonsi/gfx9: set the LLVM processor, require LLVM 5.0 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák 68d6d097f1 radeonsi/gfx9: add GFX9 and VEGA10 enums 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák 5691e14735 amd: GFX9 packet changes 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák ecbdfbeb05 amd: define event types for GFX9 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00