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radeonsi/gfx9: do DCC clears on non-mipmapped textures only 

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák 2016-10-27 23:48:44 +02:00
parent aba8e0ea68
commit 272b50a6f4
2 changed files with 17 additions and 4 deletions
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16
src/gallium/drivers/radeon/r600_texture.c
View File

@ -2417,7 +2417,7 @@ void vi_dcc_clear_level(struct r600_common_context *rctx,
unsigned level, unsigned clear_value)
{
struct pipe_resource *dcc_buffer;
uint64_t dcc_offset;
uint64_t dcc_offset, clear_size;
assert(rtex->dcc_offset && level < rtex->surface.num_dcc_levels);
@ -2429,10 +2429,18 @@ void vi_dcc_clear_level(struct r600_common_context *rctx,
dcc_offset = rtex->dcc_offset;
}
dcc_offset += rtex->surface.u.legacy.level[level].dcc_offset;
if (rctx->chip_class >= GFX9) {
/* Mipmap level clears aren't implemented. */
assert(rtex->resource.b.b.last_level == 0);
/* MSAA needs a different clear size. */
assert(rtex->resource.b.b.nr_samples <= 1);
clear_size = rtex->surface.dcc_size;
} else {
dcc_offset += rtex->surface.u.legacy.level[level].dcc_offset;
clear_size = rtex->surface.u.legacy.level[level].dcc_fast_clear_size;
}
rctx->clear_buffer(&rctx->b, dcc_buffer, dcc_offset,
rtex->surface.u.legacy.level[level].dcc_fast_clear_size,
rctx->clear_buffer(&rctx->b, dcc_buffer, dcc_offset, clear_size,
clear_value, R600_COHERENCY_CB_META);
}

5
src/gallium/drivers/radeonsi/si_blit.c
View File

@ -1035,6 +1035,11 @@ static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
*/
if (dst->dcc_offset &&
info->dst.level < dst->surface.num_dcc_levels) {
/* TODO: Implement per-level DCC clears for GFX9. */
if (sctx->b.chip_class >= GFX9 &&
info->dst.resource->last_level != 0)
goto resolve_to_temp;
vi_dcc_clear_level(&sctx->b, dst, info->dst.level,
0xFFFFFFFF);
dst->dirty_level_mask &= ~(1 << info->dst.level);