2b440d5461
Merge branch 'master' into autoconf2
2007-12-26 15:41:24 -06:00
ab57cbaccc
autoconf: Helper options for adding GCC 32/64 bit flags
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Two new configure options to add -m32 or -m64 to the CFLAGS and CXXFLAGS
when GCC is in use. By default, the user supplied options are
environment variables are respected, but these options are quick helps
for the common case of x86/x86_64 using GCC.
2007-12-26 15:38:30 -06:00
b422e5ad37
i915: apply commit a0a5e8cfc0 from 965.
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fix #11925
2007-12-25 17:22:19 +08:00
cf46aee14a
mesa: fix a bad cast in put_values_z24.
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The values passed to put_values_z24 are GLuint,
not GLubyte. fix #13543
2007-12-25 14:18:05 +08:00
166a828ddf
__driConfigOptions must be PUBLIC.
2007-12-24 19:16:24 -05:00
0b7e0f8159
R300: RV410 SE chips have half the pipes of regular RV410
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This fixes 3D rendering on x700 SE chips. Reported
by Kano.
2007-12-24 11:59:27 -05:00
4c5a2b3af2
autoconf: Documentation for using the autoconf'd build
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Most of the options available from configure are documented on the
autoconf.html. This page is reached as an alternative provided on the
install.html page. An FAQ about why there is no configure script has
been removed.
2007-12-23 16:38:18 -08:00
26473140b9
fix GL_LINE_LOOP with drivers using own render pipeline stage ( #12410 , #13527 )
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primitive needs to include the begin/end flags (broken since vbo-0.2). Should
fix missing first/last line segment on gamma, i810, i915, mga, r200, radeon,
s3v, savage, unichrome (r300 already correct). Tested on r200, fixes #13527 .
2007-12-22 18:54:18 +01:00
2f3e939ae7
Silence compiler warnings from XML error macros.
2007-12-21 15:31:00 -05:00
9136e1f2c8
[965] Fix and enable separate stencil.
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Note that this does not enable GL_EXT_stencil_two_side, because Mesa's computed
_TestTwoSide ends up respecting only STENCIL_TEST_TWO_SIDE_EXT (defaults to
GL_FALSE), even if the application uses only GL 2.0 / ATI entrypoints.
2007-12-21 11:50:00 -08:00
9e68e191ac
[intel] Move some pixel path support from drivers to shared.
2007-12-21 11:41:46 -08:00
f8830a1bf7
intel: cast a pointer to unsigned long, avoid potential error.
2007-12-21 17:03:55 +08:00
bea6b5fe5a
[965] Enable EXT_framebuffer_object.
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To do so, merge the remainnig necessary code from the buffers, blit, span, and
screen code to shared, and replace it with those.
2007-12-20 11:32:55 -08:00
106f398220
[965] Actually enable SGIS_generate_mipmap.
2007-12-20 11:28:10 -08:00
101abee6c4
[intel] Fix and reenable (software) SGIS_generate_mipmap
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The core problem was that _mesa_generate_mipmap was not respecting RowStride
of the source image. Additionally, the intel private data associated with the
images (level and face) was not being initialized for the
_mesa_generate_mipmap-generated images.
2007-12-20 11:26:34 -08:00
b2f62609d0
[intel] Allow driver hooks to be NULL in intel_buffers.c and just update flags.
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The 965 driver relies on flag checking instead of these hooks, and will be
using this code soon.
2007-12-20 08:24:45 -08:00
fcd1e9dad6
[i915] Move meta_draw_quad into the vtbl with other meta operations.
2007-12-20 08:19:42 -08:00
2761cfce46
return correct size from glGetActiveUniform (bug 13751)
2007-12-20 09:06:05 -07:00
e543292335
i915: avoid dead lock in intel_meta_draw_poly. fix #13696
2007-12-20 16:49:25 +08:00
da693b7c89
Don't try to build nonexistent i915tex driver on linux-x86-64
2007-12-18 22:20:37 -08:00
f71032b7e2
docs: Fix links in contribute section
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The contribute section had a broken hyperlink, masking the mailing list
text.
2007-12-18 22:13:46 -08:00
d2d82f8a29
[915] Set cliprects in the drawbuffer software fallback case as well.
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Otherwise, we may violate cliprect asssertions on clearing the buffers, which
isn't affected by the fallback.
2007-12-18 18:56:20 -08:00
4cca760a9b
i965: allocate GRF registers before building subroutines,
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it ensures there are sufficient registers for all subroutines.
2007-12-19 10:22:28 +08:00
e3a1ae0fcb
i965: restore the flag after building the subroutine of the
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GS thread. fix #13240
2007-12-19 09:59:37 +08:00
88f1419f96
added glSecondaryColor3fv_func
2007-12-18 16:30:42 -07:00
83af4f3623
added two-side test
2007-12-18 16:25:48 -07:00
87002aba3b
Test GL_VERTEX_PROGRAM_TWO_SIDE and frag shader gl_FrontFacing features
2007-12-18 16:24:19 -07:00
caec2a79e6
added twoside demo
2007-12-18 16:24:19 -07:00
256115bd5e
simplify update two-side lighting test (follow-on to previous front/back-face changes)
2007-12-18 16:24:19 -07:00
441bab8f17
fix NEED_SECONDARY_COLOR for vert/frag progs
2007-12-18 16:24:19 -07:00
85f5e6d7b9
Fix a quadstrip front/back-face inconsistancy.
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Only set front material colors to make it noticable if front/back-face
determination is incorrect anywhere.
2007-12-18 16:24:19 -07:00
9efa1029e5
Fix mismatched map/unmap of buffers in swrast read/drawpixels error paths.
2007-12-18 14:51:42 -08:00
4878f12189
[915] Free dri_bufmgr after mesa context data.
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Fixes a crash when buffer objects are left around until context destroy.
2007-12-18 14:17:27 -08:00
a856da6324
[915] Make polygon stipple use pre-unpacked pixel data.
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This fixes a crash when stippling using data from a PBO.
2007-12-18 14:14:44 -08:00
0dc2c68ffc
[915] Fix clear color when clearing with triangles.
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The diffuse color format is always ARGB32, regardless of the destination
surface format.
2007-12-18 10:42:30 -08:00
dd1a868b74
[INTEL] Fix 965 to use new centralized mipmap pitch function
2007-12-18 10:22:16 -08:00
a183efc132
[Intel] Centralize mipmap pitch computations.
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mipmap pitches must account for the device alignment requirements, which
used to be fairly simple; just align to a 4-byte boundary. However, to allow
textures to be drawn to under TTM, they now need to be aligned to a 64-byte
boundary. Placing all of the alignment constraints in a single function
allows this new constraint to be applied uniformly.
There was some pitch constraining code in intel_miptree_create, but that was
modifying the pitch long after the miptree had been layed out, so it only
served to wreck the mipmap and cause rendering errors.
2007-12-18 10:22:04 -08:00
6f1bfdc4bf
[i915] Remove redundant set_draw_region code (like the comment says).
2007-12-17 17:01:07 -08:00
33487c15ba
[intel] Improve INTEL_DEBUG=blit description of clearing.
2007-12-17 16:57:59 -08:00
c24300f937
[intel] Fix copy'n'pasteo in decoding of the blit clear packet.
2007-12-17 16:53:51 -08:00
9a8819e767
[965] Add decode of 3DSTATE_DRAWING_RECTANGLE.
2007-12-17 16:53:47 -08:00
146030aad2
[965] Allow draw or depth regions to be NULL.
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With FBOs, we end up wanting to do 3D metaops against one or the other without
having to find the other one to fill in if we're not going to draw to it.
2007-12-17 16:50:09 -08:00
447facfcd6
[965] Simplify scissor handling by using DrawBuffer values.
2007-12-17 15:30:04 -08:00
8336f3ffb7
[965] fix bad conflict resolution in debug code.
2007-12-17 14:42:31 -08:00
2c9e515d86
[965] Replace our own depth constants in intel context with GL context ones.
2007-12-17 14:28:54 -08:00
98d4355240
[965] Fix software fallbacks with region-backed textures.
2007-12-17 13:47:52 -08:00
c1d6b874b3
[intel] Cleanup of */intel_blit.c to bring the two closer.
2007-12-17 13:19:33 -08:00
b3169a9c35
[965] Output the buffer type in INTEL_DEBUG=bat surface state decode.
2007-12-17 13:02:16 -08:00
1e04132306
i915: Fix issues with glDrawBuffer(GL_NONE).
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Don't dereference NULL renderbuffer pointer, and make sure the software
fallback sticks.
Fixes https://bugs.freedesktop.org/show_bug.cgi?id=13694 .
2007-12-17 12:20:56 +01:00
d859a60dc3
i965: check NULL pointer
2007-12-17 14:42:42 +08:00
Dan Nicholson
Xiang, Haihao
Adam Jackson
Alex Deucher
Roland Scheidegger
Kristian Høgsberg
Eric Anholt
Brian
Keith Packard
Michel Dänzer