Commit Graph

46020 Commits

Author SHA1 Message Date
Chia-I Wu 15576344f7 android: build android sw winsys
This builds the static library libmesa_winsys_sw_android from winsys/sw.
2011-08-21 02:01:49 +08:00
Chia-I Wu b38da5f0a1 android: build targets/egl-static
This builds the static library libmesa_egl_gallium from
targets/egl-static.
2011-08-21 02:01:49 +08:00
Chia-I Wu 98345cf1b5 android: build st/egl with android backend
This builds the static library libmesa_st_egl from st/egl.
2011-08-21 02:01:48 +08:00
Chia-I Wu 688db6e8dc android: build gallium auxiliaries
This builds the static library libmesa_gallium from gallium auxiliaries.
2011-08-21 02:01:48 +08:00
Chia-I Wu c9b21d986e android: build libGLES_mesa
This is the first step to integrate Mesa into Android(-x86) build
system.  You can git clone mesa under the external/ directory of Android
source tree and build Android with

 $ make BOARD_GPU_DRIVERS=swrast

It will build libGLES_mesa that will be loaded by Android runtime.

libGLES_mesa is still a stub in this commit.
2011-08-21 02:01:48 +08:00
Chia-I Wu 4b2b0b9fb8 targets/egl-static: do not rely on libudev on Android
There is no libudev on Android.  Use DRM to get the PCI ID directly.

Reviewed-by: Benjamin Franzke <benjaminfranzke@googlemail.com>
2011-08-21 02:01:48 +08:00
Chia-I Wu 15418a8505 st/egl: add android backend
Both HW and SW rendering are supported for Android.  For SW rendering,
we use the generic gralloc lock/unlock for mapping and unmapping color
buffers (in winsys/android).

For HW rendering, we need to know the real type of color buffers.  This
backend works with drm_gralloc, where a color buffer is backed by a GEM
object.
2011-08-21 02:01:48 +08:00
Chia-I Wu 8e54c47a61 winsys/android: new SW winsys for Android
On Android, color buffers are passed between server and clients as
opaque buffer_handle_t.  This winsys makes use of gralloc, which
provides a generic way to map and unmap buffer_handle_t for CPU access.
2011-08-21 02:01:48 +08:00
Chia-I Wu 00b365bc78 egl: add Android-specific extensions
Add EGL_ANDROID_image_native_buffer and EGL_ANDROID_swap_rectangle.
There is no spec for them though.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Chad Versace <chad@chad-versace.us>
2011-08-21 02:01:48 +08:00
Chia-I Wu b0945c14df egl: add _EGL_PLATFORM_ANDROID
This is Android Gingerbread platform.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Chad Versace <chad@chad-versace.us>
2011-08-21 02:01:48 +08:00
Chia-I Wu 504f92c739 mesa: android has no log2f nor ffs
Define log2f(v) to be logf(v) / M_LN2 and ffs to __builtin_ffs.

Reviewed-by: Chad Versace <chad@chad-versace.us>
2011-08-21 02:01:48 +08:00
Chia-I Wu b34770d834 ralloc: include limits.h for SIZE_MAX on Android
Android does not define SIZE_MAX in stdint.h.  We have to include
limits.h for it.

Reviewed-by: Chad Versace <chad@chad-versace.us>
2011-08-21 02:01:48 +08:00
Chia-I Wu cd893ccba9 gallium: add PIPE_OS_ANDROID support
Android uses Linux kernel and its own C runtime.  It resembles
PIPE_OS_LINUX a lot with some minor exceptions.

Reviewed-by: Brian Paul <brianp@vmware.com>
2011-08-21 02:01:48 +08:00
Chia-I Wu 31753b50f3 glsl: remove an unnecessary header include
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chad Versace <chad@chad-versace.us>
2011-08-21 02:01:47 +08:00
Chia-I Wu a40008ac64 mesa: fix !FEATURE_GL build
Move vbo_exec_FlushVertices_internal out of FEATURE_beginend.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Chad Versace <chad@chad-versace.us>
2011-08-21 02:01:47 +08:00
Kenneth Graunke f7d2dcae3b i965/gen7: Use align1 mode to set URB_WRITE_HWORD channel enables.
Makes the new vertex shader backend work on Ivybridge.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-20 00:17:55 -07:00
Kenneth Graunke e98ee06776 i965/fs: Don't double-convert integer/boolean uniforms.
When ctx->Const.NativeIntegers is set, Core Mesa loads integer/boolean
uniforms directly, rather than loading the floating point equivalent.
So, when that's set, we don't need to perform any conversions.

Unfortunately, we can't properly support native integers with the old
vertex shader backend, so this patch leaves them disabled for now.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-19 23:32:50 -07:00
Kenneth Graunke 01d81dedc7 mesa, glsl_to_tgsi: Add new gl_context::NativeIntegers flag.
Previously, native integer support was based on whether the driver
advertised GLSL 1.30 or not.  However, drivers that natively support
integers may wish to do so for older GLSL versions as well.  Adding this
new opt-in flag allows them to do so.

Currently disabled by default on all drivers, which was the existing
behavior (no drivers currently implement GLSL 1.30).

Fixes piglit tests on i965 with INTEL_GLSL_VERSION=130 set:
- spec/glsl-1.10/fs-uniform-int-110.shader_test
- spec/glsl-1.30/fs-uniform-int-130.shader_test
(it was doubly converting the data)

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-19 23:30:45 -07:00
Kenneth Graunke 07e9b9049f ir_to_mesa: Remove incorrect usage of the 'struct' keyword on classes.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-19 23:29:24 -07:00
Kenneth Graunke eb86bb55f5 i965/fs: Change incorrect use of 'struct fs_reg' to simply 'fs_reg'.
It's actually a class.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-19 23:29:24 -07:00
Kenneth Graunke 64f11db558 glsl: Remove unused variable. 2011-08-19 23:29:23 -07:00
Eric Anholt f4db75547f i965/vs: Implement proper register allocation instead of 1:1 mapping.
Fixes vs-atan-* and several others.  This is not the real solution we
eventually want, which will pack floats, vec2s, and vec3s into vec4
registers, but this code should provide the framework for that.
2011-08-19 17:06:29 -07:00
Eric Anholt 8174945d33 i965/vs: Add simple dead code elimination.
This is copied right from the fragment shader.  It is needed for real
register allocation to work correctly.
2011-08-19 17:06:29 -07:00
Eric Anholt 3dadc1e3cc i965/vs: Copy the live intervals calculation over from the FS.
This is a rather pessimistic calculation, since it doesn't distinguish
individual channels of a vec4, or elements of an array, but should be
a minimum start for register allocation.
2011-08-19 16:55:02 -07:00
Eric Anholt eb5454f20a i965/vs: Remove stale comment about compressed instructions.
This was copy'n'paste from the fragment shader, and didn't make sense
here.
2011-08-19 16:55:02 -07:00
Lauri Kasanen 88bc4eda0f pp/main queue: Add the PP headers
Signed-off-by: Lauri Kasanen <cand@gmx.com>
Signed-off-by: Brian Paul <brianp@vmware.com>
2011-08-19 16:51:16 -06:00
Lauri Kasanen 85d2ee59d9 pp/main queue: Add pp_program.[ch]
Signed-off-by: Lauri Kasanen <cand@gmx.com>
Signed-off-by: Brian Paul <brianp@vmware.com>
2011-08-19 16:51:16 -06:00
Lauri Kasanen 0d383d4790 pp/main queue: Add pp_init.c
Signed-off-by: Lauri Kasanen <cand@gmx.com>
Signed-off-by: Brian Paul <brianp@vmware.com>
2011-08-19 16:51:16 -06:00
Lauri Kasanen de43cd310c pp/main queue: Add pp_run.c
Signed-off-by: Lauri Kasanen <cand@gmx.com>
Signed-off-by: Brian Paul <brianp@vmware.com>
2011-08-19 16:51:06 -06:00
Lauri Kasanen caeb3cdf2f pp: Add Jimenez' MLAA
Signed-off-by: Lauri Kasanen <cand@gmx.com>
Signed-off-by: Brian Paul <brianp@vmware.com>
2011-08-19 16:51:06 -06:00
Lauri Kasanen f951550d3f pp: Add the MLAA areamap
The areamap contains precomputed data on different aliasing types.
It is necessary for good performance.

Signed-off-by: Lauri Kasanen <cand@gmx.com>
Signed-off-by: Brian Paul <brianp@vmware.com>
2011-08-19 16:51:06 -06:00
Lauri Kasanen 6ff00c1afa pp: Cel-shade filter
Signed-off-by: Lauri Kasanen <cand@gmx.com>
Signed-off-by: Brian Paul <brianp@vmware.com>
2011-08-19 16:51:05 -06:00
Lauri Kasanen e453289a77 pp: Color filters
Signed-off-by: Lauri Kasanen <cand@gmx.com>
Signed-off-by: Brian Paul <brianp@vmware.com>
2011-08-19 16:51:05 -06:00
Lauri Kasanen e86e4cf128 pp: Docs
Signed-off-by: Lauri Kasanen <cand@gmx.com>
Signed-off-by: Brian Paul <brianp@vmware.com>
2011-08-19 16:51:05 -06:00
Lauri Kasanen d2fdc58fe7 aux/Makefile,SConscript: Build PP
Signed-off-by: Lauri Kasanen <cand@gmx.com>
Signed-off-by: Brian Paul <brianp@vmware.com>
2011-08-19 16:50:46 -06:00
Lauri Kasanen 421235d42a st/dri: Bind the post-processing queue to dri
Signed-off-by: Lauri Kasanen <cand@gmx.com>
Signed-off-by: Brian Paul <brianp@vmware.com>
2011-08-19 16:49:33 -06:00
Lauri Kasanen 6a6441fc03 driconf: Add the PP descriptions
Signed-off-by: Lauri Kasanen <cand@gmx.com>
Signed-off-by: Brian Paul <brianp@vmware.com>
2011-08-19 16:47:23 -06:00
Marek Olšák db71537f01 r600g: don't allocate separate depth and stencil for transfer textures on EG
The state tracker expects depth and stencil pixels interleaved.
Evergreen can bind an interleaved depth-stencil resource as a colorbuffer,
but not as a zbuffer.

The hardware can do the interleaving for us when decompressing.
2011-08-19 23:12:15 +02:00
Marek Olšák 754ea4ea76 r600g: finally enable float depth buffers on evergreen 2011-08-19 23:12:11 +02:00
Marek Olšák 565f39bdb2 r600g: rename resource -> view in create_sampler_view
The sampler view is not a resource.
Also remove the unused desc variable.
2011-08-19 23:12:11 +02:00
Marek Olšák 751a6ed893 r600g: hack around a problem with texture alignment 2011-08-19 23:12:11 +02:00
Marek Olšák 98a87a594b r600g: simplify the conditionals determining array mode 2011-08-19 23:12:11 +02:00
Marek Olšák 7f29824fd5 r600g: put depth and stencil into one backing buffer
For DRI2 sharing.
2011-08-19 23:12:11 +02:00
Marek Olšák 68c54abb2c r600g: fix depth-stencil on evergreen
Such that it actually works in apps which use both.

A separate buffer is allocated for stencil. The only exception is
the window-system-provided depth-stencil buffer, where depth and stencil
share the same buffer.

This fixes:
- fbo-depthstencil-GL_DEPTH24_STENCIL8-clear
- fbo-depthstencil-GL_DEPTH24_STENCIL8-drawpixels-FLOAT-and-USHORT
- fbo-depthstencil-GL_DEPTH24_STENCIL8-readpixels-24_8
- fbo-depthstencil-GL_DEPTH24_STENCIL8-readpixels-FLOAT-and-USHORT
2011-08-19 23:12:11 +02:00
Brian Paul 3e9dc51f82 mesa: handle array textures in GenerateMipmap(), FramebufferTexture1/2D()
This was an unfinished to-do item before.
With this patch and the two preceeding patches, piglit's
fbo-generatemipmap-array test runs and passes instead of generating
a GL error and dying on an assertion.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2011-08-19 13:31:11 -06:00
Brian Paul 0f8c43c34f meta: use fallback mipmap generation for 1D/2D texture arrays
We could do 1D/2D arrays with textured quad rendering, but it'll take
some work (as with 3D textures).

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2011-08-19 13:31:11 -06:00
Brian Paul 0eb18ee557 mesa: set Q=1 for OPCODE_TEX execution
Q should not be significant for OPCODE_TEX, but it winds up getting
passed to the compute_lambda() function.  Make sure it's 1.0 to
prevent garbage values, which is effectively what we get when the
swizzle is coord.xyzz (which is what GLSL gives us).

Part of the fix for piglit's fbo-generatemipmap-array test.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2011-08-19 13:31:10 -06:00
Brian Paul 352cab498a mesa: restructure error checking in _mesa_FramebufferTexture1D/2DEXT()
In anticipation of adding more texture targets.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2011-08-19 13:31:10 -06:00
Chad Versace f23c3ebecc mesa: Declare _mesa_meta_begin()/end() as public
Declare _mesa_meta_begin()/end() in meta.h so that drivers can write
custom meta-ops (such as HiZ resolves for i965).

This necessitates moving the the META_* macros into meta.h. To prevent
naming collisions, this commit renames each macro to be MESA_META_*.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Chad Versace <chad@chad-versace.us>
2011-08-19 10:49:59 -07:00
Christoph Bumiller 778997f9df nv50: fix potential null deref in insn modifer optimization pass
Bug introduced in 34980cd153.
2011-08-19 16:57:30 +02:00