r600g: fix depth-stencil on evergreen
Such that it actually works in apps which use both. A separate buffer is allocated for stencil. The only exception is the window-system-provided depth-stencil buffer, where depth and stencil share the same buffer. This fixes: - fbo-depthstencil-GL_DEPTH24_STENCIL8-clear - fbo-depthstencil-GL_DEPTH24_STENCIL8-drawpixels-FLOAT-and-USHORT - fbo-depthstencil-GL_DEPTH24_STENCIL8-readpixels-24_8 - fbo-depthstencil-GL_DEPTH24_STENCIL8-readpixels-FLOAT-and-USHORT
This commit is contained in:
Marek Olšák
parent
3e9dc51f82
commit
68c54abb2c
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@ -262,7 +262,6 @@ static uint32_t r600_translate_dbformat(enum pipe_format format)
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case PIPE_FORMAT_Z16_UNORM:
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return V_028040_Z_16;
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case PIPE_FORMAT_Z24X8_UNORM:
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return V_028040_Z_24;
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case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
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return V_028040_Z_24;
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default:
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@ -270,14 +269,6 @@ static uint32_t r600_translate_dbformat(enum pipe_format format)
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}
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}
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static uint32_t r600_translate_stencilformat(enum pipe_format format)
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{
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if (format == PIPE_FORMAT_Z24_UNORM_S8_USCALED)
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return 1;
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else
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return 0;
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}
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static uint32_t r600_translate_colorswap(enum pipe_format format)
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{
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switch (format) {
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@ -1381,55 +1372,51 @@ static void evergreen_cb(struct r600_pipe_context *rctx, struct r600_pipe_state
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}
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static void evergreen_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
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const struct pipe_framebuffer_state *state)
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const struct pipe_framebuffer_state *state)
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{
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struct r600_resource_texture *rtex;
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struct r600_resource *rbuffer;
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struct r600_surface *surf;
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unsigned level;
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unsigned pitch, slice, format, stencil_format;
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unsigned level, first_layer;
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unsigned pitch, slice, format;
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unsigned offset;
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if (state->zsbuf == NULL)
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return;
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level = state->zsbuf->u.tex.level;
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surf = (struct r600_surface *)state->zsbuf;
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rtex = (struct r600_resource_texture*)state->zsbuf->texture;
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rtex = (struct r600_resource_texture*)surf->base.texture;
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rbuffer = &rtex->resource;
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/* XXX quite sure for dx10+ hw don't need any offset hacks */
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offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
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level, state->zsbuf->u.tex.first_layer);
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level = surf->base.u.tex.level;
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first_layer = surf->base.u.tex.first_layer;
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offset = r600_texture_get_offset(rtex, level, first_layer);
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pitch = rtex->pitch_in_blocks[level] / 8 - 1;
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slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
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format = r600_translate_dbformat(state->zsbuf->texture->format);
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stencil_format = r600_translate_stencilformat(state->zsbuf->texture->format);
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format = r600_translate_dbformat(rtex->real_format);
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r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
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offset >> 8, 0xFFFFFFFF, rbuffer->bo, RADEON_USAGE_READWRITE);
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offset >> 8, 0xFFFFFFFF, rtex->resource.bo, RADEON_USAGE_READWRITE);
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r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
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offset >> 8, 0xFFFFFFFF, rbuffer->bo, RADEON_USAGE_READWRITE);
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if (stencil_format) {
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uint32_t stencil_offset;
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stencil_offset = ((surf->aligned_height * rtex->pitch_in_bytes[level]) + 255) & ~255;
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r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
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(offset + stencil_offset) >> 8, 0xFFFFFFFF, rbuffer->bo, RADEON_USAGE_READWRITE);
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r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
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(offset + stencil_offset) >> 8, 0xFFFFFFFF, rbuffer->bo, RADEON_USAGE_READWRITE);
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}
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offset >> 8, 0xFFFFFFFF, rtex->resource.bo, RADEON_USAGE_READWRITE);
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r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL, 0);
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r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
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S_028044_FORMAT(stencil_format), 0xFFFFFFFF, rbuffer->bo, RADEON_USAGE_READWRITE);
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if (rtex->stencil) {
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uint32_t stencil_offset =
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r600_texture_get_offset(rtex->stencil, level, first_layer);
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r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
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stencil_offset >> 8, 0xFFFFFFFF, rtex->stencil->resource.bo, RADEON_USAGE_READWRITE);
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r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
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stencil_offset >> 8, 0xFFFFFFFF, rtex->stencil->resource.bo, RADEON_USAGE_READWRITE);
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r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
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1, 0xFFFFFFFF, rtex->stencil->resource.bo, RADEON_USAGE_READWRITE);
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} else {
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r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
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0, 0xFFFFFFFF, NULL, RADEON_USAGE_READWRITE);
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}
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r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO,
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S_028040_ARRAY_MODE(rtex->array_mode[level]) | S_028040_FORMAT(format),
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0xFFFFFFFF, rbuffer->bo, RADEON_USAGE_READWRITE);
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0xFFFFFFFF, rtex->resource.bo, RADEON_USAGE_READWRITE);
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r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
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S_028058_PITCH_TILE_MAX(pitch),
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0xFFFFFFFF, NULL, 0);
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@ -111,7 +111,7 @@ void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_t
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if (!texture->dirty_db)
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return;
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surf_tmpl.format = texture->resource.b.b.b.format;
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surf_tmpl.format = texture->real_format;
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surf_tmpl.u.tex.level = level;
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surf_tmpl.u.tex.first_layer = 0;
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surf_tmpl.u.tex.last_layer = 0;
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@ -119,7 +119,7 @@ void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_t
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zsurf = ctx->create_surface(ctx, &texture->resource.b.b.b, &surf_tmpl);
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surf_tmpl.format = ((struct pipe_resource*)texture->flushed_depth_texture)->format;
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surf_tmpl.format = texture->flushed_depth_texture->real_format;
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surf_tmpl.usage = PIPE_BIND_RENDER_TARGET;
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cbsurf = ctx->create_surface(ctx,
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(struct pipe_resource*)texture->flushed_depth_texture, &surf_tmpl);
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@ -249,7 +249,7 @@ static void r600_compressed_to_blittable(struct pipe_resource *tex,
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struct texture_orig_info *orig)
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{
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struct r600_resource_texture *rtex = (struct r600_resource_texture*)tex;
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unsigned pixsize = util_format_get_blocksize(tex->format);
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unsigned pixsize = util_format_get_blocksize(rtex->real_format);
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int new_format;
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int new_height, new_width;
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@ -269,7 +269,6 @@ static void r600_compressed_to_blittable(struct pipe_resource *tex,
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tex->width0 = new_width;
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tex->height0 = new_height;
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tex->format = new_format;
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}
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static void r600_reset_blittable_to_compressed(struct pipe_resource *tex,
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@ -52,6 +52,12 @@ struct r600_resource {
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struct r600_resource_texture {
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struct r600_resource resource;
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/* If this resource is a depth-stencil buffer on evergreen, this contains
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* the depth part of the format. There is a separate stencil resource
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* for the stencil buffer below. */
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enum pipe_format real_format;
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unsigned offset[PIPE_MAX_TEXTURE_LEVELS];
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unsigned pitch_in_bytes[PIPE_MAX_TEXTURE_LEVELS]; /* transfer */
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unsigned pitch_in_blocks[PIPE_MAX_TEXTURE_LEVELS]; /* texture resource */
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@ -62,6 +68,7 @@ struct r600_resource_texture {
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unsigned tile_type;
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unsigned depth;
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unsigned dirty_db;
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struct r600_resource_texture *stencil; /* Stencil is in a separate buffer on Evergreen. */
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struct r600_resource_texture *flushed_depth_texture;
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boolean is_flushing_texture;
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@ -173,15 +173,15 @@ static unsigned r600_texture_get_nblocksx(struct pipe_screen *screen,
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{
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struct pipe_resource *ptex = &rtex->resource.b.b.b;
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unsigned nblocksx, block_align, width;
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unsigned blocksize = util_format_get_blocksize(ptex->format);
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unsigned blocksize = util_format_get_blocksize(rtex->real_format);
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if (rtex->pitch_override)
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return rtex->pitch_override / blocksize;
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width = mip_minify(ptex->width0, level);
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nblocksx = util_format_get_nblocksx(ptex->format, width);
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nblocksx = util_format_get_nblocksx(rtex->real_format, width);
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block_align = r600_get_block_alignment(screen, ptex->format,
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block_align = r600_get_block_alignment(screen, rtex->real_format,
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rtex->array_mode[level]);
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nblocksx = align(nblocksx, block_align);
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return nblocksx;
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@ -195,7 +195,7 @@ static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen,
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unsigned height, tile_height;
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height = mip_minify(ptex->height0, level);
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height = util_format_get_nblocksy(ptex->format, height);
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height = util_format_get_nblocksy(rtex->real_format, height);
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tile_height = r600_get_height_alignment(screen,
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rtex->array_mode[level]);
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height = align(height, tile_height);
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@ -220,7 +220,7 @@ static void r600_texture_set_array_mode(struct pipe_screen *screen,
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unsigned w, h, tile_height, tile_width;
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tile_height = r600_get_height_alignment(screen, array_mode);
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tile_width = r600_get_block_alignment(screen, ptex->format, array_mode);
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tile_width = r600_get_block_alignment(screen, rtex->real_format, array_mode);
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w = mip_minify(ptex->width0, level);
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h = mip_minify(ptex->height0, level);
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@ -241,11 +241,11 @@ static void r600_setup_miptree(struct pipe_screen *screen,
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struct radeon *radeon = ((struct r600_screen*)screen)->radeon;
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enum chip_class chipc = r600_get_family_class(radeon);
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unsigned size, layer_size, i, offset;
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unsigned nblocksx, nblocksy, extra_size = 0;
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unsigned nblocksx, nblocksy;
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for (i = 0, offset = 0; i <= ptex->last_level; i++) {
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unsigned blocksize = util_format_get_blocksize(ptex->format);
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unsigned base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
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unsigned blocksize = util_format_get_blocksize(rtex->real_format);
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unsigned base_align = r600_get_base_alignment(screen, rtex->real_format, array_mode);
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r600_texture_set_array_mode(screen, rtex, i, array_mode);
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@ -264,10 +264,6 @@ static void r600_setup_miptree(struct pipe_screen *screen,
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else
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size = layer_size * ptex->array_size;
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/* evergreen stores depth and stencil separately */
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if ((chipc >= EVERGREEN) && util_format_is_depth_or_stencil(ptex->format))
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extra_size = align(extra_size + (nblocksx * nblocksy * 1), base_align);
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/* align base image and start of miptree */
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if ((i == 0) || (i == 1))
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offset = align(offset, base_align);
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@ -278,7 +274,7 @@ static void r600_setup_miptree(struct pipe_screen *screen,
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offset += size;
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}
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rtex->size = offset + extra_size;
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rtex->size = offset;
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}
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/* Figure out whether u_blitter will fallback to a transfer operation.
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@ -384,20 +380,76 @@ r600_texture_create_object(struct pipe_screen *screen,
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resource->b.b.b.screen = screen;
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resource->bo = bo;
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rtex->pitch_override = pitch_in_bytes_override;
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rtex->real_format = base->format;
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/* We must split depth and stencil into two separate buffers on Evergreen. */
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if (r600_get_family_class(((struct r600_screen*)screen)->radeon) >= EVERGREEN &&
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util_format_is_depth_and_stencil(base->format)) {
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struct pipe_resource stencil;
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unsigned stencil_pitch_override = 0;
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switch (base->format) {
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case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
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rtex->real_format = PIPE_FORMAT_Z24X8_UNORM;
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break;
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case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
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rtex->real_format = PIPE_FORMAT_X8Z24_UNORM;
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break;
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case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
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rtex->real_format = PIPE_FORMAT_Z32_FLOAT;
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break;
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default:
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assert(0);
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FREE(rtex);
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return NULL;
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}
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/* Divide the pitch in bytes by 4 for stencil, because it has a smaller pixel size. */
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if (pitch_in_bytes_override) {
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assert(base->format == PIPE_FORMAT_Z24_UNORM_S8_USCALED ||
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base->format == PIPE_FORMAT_S8_USCALED_Z24_UNORM);
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stencil_pitch_override = pitch_in_bytes_override / 4;
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}
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/* Allocate the stencil buffer. */
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stencil = *base;
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stencil.format = PIPE_FORMAT_S8_USCALED;
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rtex->stencil = r600_texture_create_object(screen, &stencil, array_mode,
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stencil_pitch_override, max_buffer_size, bo);
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if (!rtex->stencil) {
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FREE(rtex);
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return NULL;
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}
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/* Proceed in creating the depth buffer. */
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}
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/* only mark depth textures the HW can hit as depth textures */
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if (util_format_is_depth_or_stencil(base->format) && permit_hardware_blit(screen, base))
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if (util_format_is_depth_or_stencil(rtex->real_format) && permit_hardware_blit(screen, base))
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rtex->depth = 1;
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r600_setup_miptree(screen, rtex, array_mode);
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resource->size = rtex->size;
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/* If bo is not NULL, in which case depth and stencil must share the same buffer,
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* and we initialized separate stencil for Evergreen. place it after depth. */
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if (bo && rtex->stencil) {
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unsigned stencil_align, stencil_offset;
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stencil_align = r600_get_base_alignment(screen, rtex->stencil->real_format, array_mode);
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stencil_offset = align(rtex->size, stencil_align);
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for (unsigned i = 0; i <= rtex->stencil->resource.b.b.b.last_level; i++)
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rtex->stencil->offset[i] += stencil_offset;
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}
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if (!resource->bo) {
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struct pipe_resource *ptex = &rtex->resource.b.b.b;
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int base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
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unsigned base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
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resource->bo = r600_bo(radeon, rtex->size, base_align, base->bind, base->usage);
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if (!resource->bo) {
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pipe_resource_reference((struct pipe_resource**)&rtex->stencil, NULL);
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FREE(rtex);
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return NULL;
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}
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@ -436,7 +488,6 @@ struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
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return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
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0, 0, NULL);
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}
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static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
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