Commit Graph

96905 Commits

Author SHA1 Message Date
Jason Ekstrand d7e0d47b9d nir: Add a bunch of b2[if] optimizations
The b2f and b2i conversions always produce zero or one which are both
representable in every type and size.  Since b2i and b2f support all bit
sizes, we can just get rid of the conversion opcode.

total instructions in shared programs: 15089335 -> 15084368 (-0.03%)
instructions in affected programs: 212564 -> 207597 (-2.34%)
helped: 896
HURT: 0

total cycles in shared programs: 369831123 -> 369826267 (<.01%)
cycles in affected programs: 2008647 -> 2003791 (-0.24%)
helped: 693
HURT: 216

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2018-10-11 15:21:19 -05:00
Jason Ekstrand 0e0dc596a2 intel/vec4: Fix nir_op_b2[fi] with 64-bit result
This is valid NIR but you can't actually hit this case today.  GLSL IR
doesn't have a bool to double opcode; it does f2d(b2f(x)).  In SPIR-V we
don't have any to/from bool conversion opcodes at all.  However, the
next commit will make us start generating it so we should be ready.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2018-10-11 15:21:19 -05:00
Jason Ekstrand 497675c21e intel/fs: Fix nir_op_b2[fi] with 64-bit result on Gen8 LP and Gen9 LP
Several of the Atom GPUs have additional restrictions on alignment when
moving < 64-bit source to a 64-bit destination.  All of the nir_op_*2*64
code generation paths respected this, but nir_op_b2[fi] did not.

Previous to commit a68dd47b91 it was not possible to generate such an
instruction from the GLSL path.  It may have been possible from SPIR-V,
but it's not clear.  The aforementioned patch converts a 64-bit
nir_op_fsign into a sequence of operations including a nir_op_b2f with a
64-bit result.  This "just works" everywhere except these Atom parts.

This problem was not detected during normal CI testing because the Atom
parts are not included in developer builds.

v2 (idr): Make the patch compile, and make some cosmetic changes.  Add a
commit message.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108319
Fixes: a68dd47b91 "nir/algebraic: Simplify fsat of fsign"
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2018-10-11 15:21:19 -05:00
Vinson Lee 4ece6aa552 egl: Use correct shared libraries suffix on macOS.
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-10-11 11:30:00 -07:00
Illia Iorin b18f8e63ef mesa: Fix pack_uint_Z_FLOAT32()
Fixed pack_uint_Z_FLOAT32 by casting row data to float instead uint.
Remove code duplicate function pack_uint_Z_FLOAT32_X24S8.
Edited case in "_mesa_get_pack_uint_z_func".
Now it looks like "_mesa_get_pack_float_z_func".
Remove _mesa_problem call, which was added for debuging this issue.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91433
Signed-off-by: Illia Iorin <illia.iorin@globallogic.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2018-10-11 10:15:09 -07:00
Rodrigo Vivi 24db1c7fcc intel: Introducing Whiskey Lake platform
Whiskey Lake uses the same gen graphics as Coffe Lake, including some
ids that were previously marked as reserved on Coffe Lake, but that
now are moved to WHL page.

This follows the ids and approach used on kernel's commit
b9be78531d27 ("drm/i915/whl: Introducing Whiskey Lake platform")
and commit c1c8f6fa731b ("drm/i915: Redefine some Whiskey Lake SKUs")

v2: Lionel noticed that GT{1,2,3} on kernel wasn't following
spec when looking to number of EUs, so kernel has been updated.

Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-10-11 10:02:40 -07:00
Boyuan Zhang d76c277421 st/va: use provided sizes and coords for vlVaGetImage
vlVaGetImage should respect the width, height, and coordinates x and y that
passed in. Therefore, pipe_box should be created with the passed in values
instead of surface width/height.

v2: add input size check, return error when size out of bounds
v3: fix the size check for vaimage
v4: add size adjustment for x and y coordinates

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Cc: "18.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Christian König <christian.koenig@amd.com>
2018-10-11 09:00:18 -04:00
Samuel Pitoiset 229803b66a radv: implement clear operations for R32G32B32
This fixes crashes for some CTS:
dEQP-VK.api.copy_and_blit.core.blit_image.all_formats.color.*.linear_*_*
dEQP-VK.api.copy_and_blit.core.blit_image.all_formats.color.*.*_linear_*

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108113
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-10-11 14:49:16 +02:00
Samuel Pitoiset c3ba3c2611 radv: disallow 3D images and mipmaps/layers for R32G32B32 linear formats
R32G32B32 are weird formats and we are only going to support
some basic operations for now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-10-11 14:49:14 +02:00
Samuel Pitoiset d179312b53 radv: add a workaround for a VGT hang with prim restart and strips
Otherwise, Yakuza and The Evil Within hang the GPU with DXVK.
This apparently only works on Polaris.

Suggested by Marek.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-10-11 10:16:11 +02:00
Timothy Arceri 3bc012a34e glsl: remove redundant es_shader checks
The es check is already covered by the is_version() check.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2018-10-11 14:45:43 +11:00
Dave Airlie cc2fe57922 st/glsl_to_tgsi: initialise need_uarl in contructor
Found by coverity

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-10-11 10:20:37 +10:00
Dave Airlie c5c3da6c90 glspirv: drop pointless assert (size_t is unsigned)
Found by coverity

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2018-10-11 10:19:48 +10:00
Dave Airlie 600d8ecb57 radv: remove unsigned comparison against 0
The value is always >= 0 here.

Found by coverity

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-10-11 10:19:20 +10:00
Dave Airlie 6e1d294804 radv: remove dead code for master_fd close
We have never opened master_Fd at this point, so remove code to
close it.

Found by coverity.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-10-11 10:19:16 +10:00
Dave Airlie 7c04b96f03 radv: don't pass shader key by copy
Coverity pointed out we were copying 168 bytes here unnecessarily.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-10-11 10:18:43 +10:00
Dave Airlie 29a7631986 anv: add missing unlock in error path.
Not going to matter, but be consistent.

Found by coverity

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Fixes: caf41c78c (anv/allocator: Support softpin in the BO cache)
2018-10-11 09:50:27 +10:00
Jason Ekstrand 4ba445e011 intel: Don't propagate conditional modifiers if a UD source is negated
This fixes a bug uncovered by my NIR integer division by constant
optimization series.

Fixes: 19f9cb72c8 "i965/fs: Add pass to propagate conditional..."
Fixes: 627f94b72e "i965/vec4: adding vec4_cmod_propagation..."
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2018-10-10 13:13:12 -05:00
Jason Ekstrand 328d4d080b util: Add tests for fast integer division by constants
While I generally trust rediculousfish to have done his homework, we've
made some adjustments to suit the needs of mesa and it'd be good to
test those.  Also, there's no better place than unit tests to clearly
document the different edge cases of the different methods.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-10-10 13:13:12 -05:00
Marek Olšák a9be8dddfe util: Add power-of-two divisor support to compute_fast_udiv_info
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-10-10 13:13:12 -05:00
Jason Ekstrand 7cde4dbcd7 util: Generalize fast integer division to be variable bit-width
There's nothing inherently fixed-width in the code.  All that's required
to generalize it is to make everything internally 64-bit and pass
UINT_BITS in as a parameter to util_compute_fast_[us]div_info.  With
that, it can now handle 8, 16, 32, and 64-bit integer division by a
constant.

We also add support for division by 1 and by other powers of 2.  This is
useful if you want to divide by a uniform value in a shader where you
have the opportunity to adjust the uniform on the CPU before passing it
in.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-10-10 13:13:12 -05:00
Marek Olšák 64eb0738d4 util: Add fast division helpers
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-10-10 13:13:12 -05:00
Marek Olšák 2940c257a6 util: import public domain code for integer division by a constant
Compilers can use this to generate optimal code for integer division
by a constant.

Additionally, an unsigned division by a uniform that is constant but not
known at compile time can still be optimized by passing 2-4 division
factors to the shader as uniforms and executing one of the fast_udiv*
variants. The signed division algorithm doesn't have this capability.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-10-10 13:13:12 -05:00
Jason Ekstrand 0dca6730b4 util: Add a simple big math library
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2018-10-10 13:13:12 -05:00
Timothy Arceri 0346ad3774 glsl: ignore trailing whitespace when define redefined
The Nvidia/AMD binary drivers allow this, as does GCC.

This fixes shader compilation issues in the latest update of
No Mans Sky.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2018-10-10 15:08:32 +11:00
Ian Romanick b44c9292b7 intel/compiler: Don't handle fsign.sat
No shader-db or CI changes on any Intel platform.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
2018-10-09 13:56:42 -07:00
Ian Romanick a68dd47b91 nir/algebraic: Simplify fsat of fsign
These allows us to not support fsign.sat in the Intel compiler backend,
and that will simplify some later changes.

No shader-db changes on any Intel platform.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
2018-10-09 13:56:42 -07:00
Ian Romanick 1546204cdd nir/algebraic: sign(x)*x*x is abs(x)*x
shader-db results:

All Gen7+ platforms had similar results. (Skylake shown)
total instructions in shared programs: 15106023 -> 15105981 (<.01%)
instructions in affected programs: 300 -> 258 (-14.00%)
helped: 6
HURT: 0
helped stats (abs) min: 7 max: 7 x̄: 7.00 x̃: 7
helped stats (rel) min: 14.00% max: 14.00% x̄: 14.00% x̃: 14.00%
95% mean confidence interval for instructions value: -7.00 -7.00
95% mean confidence interval for instructions %-change: -14.00% -14.00%
Instructions are helped.

total cycles in shared programs: 566050327 -> 566050075 (<.01%)
cycles in affected programs: 2826 -> 2574 (-8.92%)
helped: 6
HURT: 0
helped stats (abs) min: 40 max: 44 x̄: 42.00 x̃: 42
helped stats (rel) min: 8.89% max: 8.94% x̄: 8.92% x̃: 8.92%
95% mean confidence interval for cycles value: -44.30 -39.70
95% mean confidence interval for cycles %-change: -8.95% -8.88%
Cycles are helped.

No changes on Gen6 or earlier.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
2018-10-09 13:56:42 -07:00
Ian Romanick 10f4a8871e nir: Add helper functions to get the instruction that generated a nir_src
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
2018-10-09 13:56:42 -07:00
Brian Paul 797e34f658 svga: change svga_destroy_shader_variant() to return void
svga_destroy_shader_variant() itself flushes and retries the command
if there's a failure.  So no need for the callers to do it.  Other
callers of the function were already ignoring the return value.

This also fixes a corner-case double-free reported by Coverity
(and reported by Dave Airlie).

Tested with various OpenGL apps.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2018-10-09 11:17:14 -06:00
Dylan Baker b781688636 meson: Don't build glsl compiler tests unless OpenGL is enabled
Since there are no other users of the glsl compiler.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-10-09 08:56:00 -07:00
Dylan Baker d84f003b95 meson: Only build gallium state tracker tests with shared_glapi
This has always been a requirement, it's just somehow been missed in the
meson build.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-10-09 08:55:56 -07:00
Dylan Baker 0fa6a8271a meson: only build clapi tests when OpenGL is being built
Otherwise building just vulkan (among other things) will build these
tests, pull in a bunch of stuff they shouldn't, and potentially fail to
compile.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-10-09 08:55:48 -07:00
Ilia Mirkin 92f56fbd89 nvc0: fix blitting red to srgb8_alpha
For some reason the 2d engine can't handle this. Red formats get special
treatment there, so perhaps related.

Fixes dEQP-GLES3 tests of the form:

  dEQP-GLES3.functional.fbo.blit.conversion.r{8,16f,32f}_to_srgb8_alpha8

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Cc: mesa-stable@lists.freedesktop.org
2018-10-09 10:33:11 -04:00
Ilia Mirkin 9bf0614116 nv50,nvc0: guard against zero-size blits
The current state tracker can generate these sometimes. Fixing this is
more involved, and due to some integer math we can generate
divisions-by-zero.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Cc: mesa-stable@lists.freedesktop.org
2018-10-09 10:33:11 -04:00
Ilia Mirkin 78d3640e49 nv50,nvc0: mark RGBX_UINT formats as renderable
This helps st/mesa avoid some (apparently) buggy fallbacks. Specifically
the CopyTexSubImage fallback tries to read texture A as RGBA_FLOAT and
write back that data into the target format, which fails for integer
formats which have no appropriate logic to do the conversion.

Since integer formats don't blend, there's no harm in the fact that the
"A" component gets written anyways.

Fixes, among others:
  https://www.khronos.org/registry/webgl/sdk/tests/conformance2/textures/canvas/tex-2d-rgb8ui-rgb_integer-unsigned_byte.html

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
2018-10-09 10:33:11 -04:00
Eric Engestrom 976188737d radv: add missing meson c++ visibility arguments
Fixes: 6f3aee40f9 "radv: using tls to store llvm related info
                             and speed up compiles (v10)"
Cc: Dave Airlie <airlied@redhat.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2018-10-09 14:22:24 +01:00
Michel Dänzer 9d3fefdc41 gbm: Add GBM_FORMAT_ARGB1555 support
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-10-09 10:32:51 +02:00
Michel Dänzer e7e033ed8a st/dri: Handle BGRA5551 format
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-10-09 10:32:50 +02:00
Rob Clark fa52ff856d freedreno/a5xx+a6xx: fix LRZ pitch alignment
Both RB_2D_DST_SIZE.PITCH (a6xx) and RB_MRT[n].PITCH (a5xx) need
alignment to 64.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-10-08 19:05:14 -04:00
Rob Clark 82c3b6fe49 freedreno/a6xx: add LRZ support
As with a5xx, hidden behind FD_MESA_DEBUG=lrz due to being paranoid
about z-fighting issues with some games (in particular, this was
observed with 0ad on a5xx.. but I think the proper solution to enable
this by default is to figure out how to do driver specific driconf
options).

Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-10-08 19:05:14 -04:00
Rob Clark a877451a41 freedreno: update generated headers
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-10-08 18:03:35 -04:00
Rob Clark bf79a7cc25 freedreno/a6xx: add helper for various CP_EVENT_WRITE
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-10-08 17:50:26 -04:00
Rob Clark 60af89815e freedreno/a6xx: remove unused fxns
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-10-08 17:50:26 -04:00
Rob Clark d5bd3ce89c freedreno/a6xx: remove fd6_shader_stateobj
Earlier gen's already got this cleanup, but a6xx was still off on a
branch then.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-10-08 17:50:26 -04:00
Ilia Mirkin 1bb1c03d61 glsl: fix array assignments of a swizzled vector
This happens in situations where we might do

  vec.wzyx[i] = ...

The swizzle would get effectively ignored because of the interaction
between how ir_assignment->set_lhs works and overwriting the write_mask.
There are two cases, one where i is a constant, and another where i is
variable. We have to be extra-careful in both cases.

Fixes the following WebGL test:

  https://www.khronos.org/registry/webgl/sdk/tests/conformance2/glsl3/vector-dynamic-indexing-swizzled-lvalue.html

And the new piglit tests:

  swizzled-writemask-indexing-nonconst.shader_test
  swizzled-writemask-indexing.shader_test

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: mesa-stable@lists.freedesktop.org
2018-10-08 14:29:14 -04:00
Samuel Pitoiset d3682766f6 radv: tidy up radv_pipeline_init_multisample_state()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-10-08 14:17:43 +02:00
Samuel Pitoiset b38228ccb0 radv: always set PA_SC_MODE_CNTL_1.OUT_OF_ORDER_WATER_MARK
It has probably no effect without out of order rasterization
anyway.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-10-08 14:17:40 +02:00
Samuel Pitoiset 937986ca1d radv: set DB_EQAA.INCOHERENT_EQAA_READS
My attempt was to set this field instead of duplicating one.

Fixes: 6cfa321c39 ("radv: add potential missing fields for DB_EQAA")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-10-08 14:17:33 +02:00
Chystiakov, Dmytro 47e3338b04 i965: fallback RGBX to RGBA in glEGLImageTargetRenderbufferStorageOES
In the same fashion as is done for glEGLImageTextureTarget2D.

v2: share the fallback which sets baseformat and internalformat correctly
    which makes both of the tests pass (Tapani)

Fixes android.hardware.nativehardware.cts.AHardwareBufferNativeTests:

   #SingleLayer_ColorTest_GpuColorOutputCpuRead_R8G8B8X8_UNORM
   #SingleLayer_ColorTest_GpuColorOutputIsRenderable_R8G8B8X8_UNORM

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2018-10-08 08:03:45 +03:00
Tapani Pälli d1fa69ed61 glsl: do not attempt assignment if operand type not parsed correctly
v2: check types of both operands (Ian)

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108012
2018-10-08 08:02:50 +03:00
Marek Olšák d877451b48 util/u_queue: add UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY
Initial version discussed with Rob Clark under a different patch name.
This approach leaves his driver unaffected.
2018-10-06 22:05:58 -04:00
Marek Olšák 066aa44fc5 radeonsi: fix a typo at CS_PARTIAL_FLUSH
harmless
2018-10-06 21:50:52 -04:00
Marek Olšák 77903c8cfb ac: add ac_build_round 2018-10-06 21:50:09 -04:00
Marek Olšák fa023f293e ac: correct PKT3_COPY_DATA definitions 2018-10-06 21:50:09 -04:00
Marek Olšák 82f5f89bf6 ac: simplify LLVM alloca helpers 2018-10-06 21:50:09 -04:00
Marek Olšák a668c8d6ba ac: define all address spaces properly 2018-10-06 21:50:09 -04:00
Gert Wollny 8f77156c26 gallivm: Make it possible to disable some optimization shortcuts in release builds
For testing it is of interest that all tests of dEQP pass, e.g. to test
virglrenderer on a host only providing software rendering like in a CI.
Hence make it possible to disable certain optimizations that make tests fail.

While we are there also add some documentation to the flags to make it clear
that this is opt-out.

Setting the environment variable "GALLIVM_PERF=no_filter_hacks" can be used to make
the following tests pass in release mode:

  dEQP-GLES2.functional.texture.mipmap.2d.affine.*_linear_*
  dEQP-GLES2.functional.texture.mipmap.cube.generate.*
  dEQP-GLES2.functional.texture.vertex.2d.filtering.*_mipmap_linear_*
  dEQP-GLES2.functional.texture.vertex.2d.wrap.*

Related:
  https://bugs.freedesktop.org/show_bug.cgi?id=94957

v2: rename optimization disabling flag to 'safemath' and also move the
    nopt flag to the perf flags.

v3: rename flag "safemath" to "no_filter_hacks" since safemath is usually
    associated with floating point operations (Roland)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2018-10-06 13:12:48 +02:00
Tomeu Vizoso 9d81cd8e7c virgl: Pass resource size and transfer offsets
Pass the size of a resource when creating it so a backing can be kept in
the other side.

Also pass the required offset to transfer commands.

This moves vtest closer to how virtio-gpu works, making it more useful
for testing.

v2: - Use new messages for creation and transfers, as changing the
      behavior of the existing messages would be messy given that we don't
      want to break compatibility with older servers.

v3: - Use correct strides: The resource corresponding to the output display
      might have a differnt line stride then the IOVs, so when reading back
      to this resource take the resource stride and the the IOV stride
      into account.

v4: Fix transfer size calculation (Andrey Simiklit)

v5: Add comment about transfer size value in the PUT commend (Gurchetan).
    Add a comment about the size correction for transfers for reading and
    writing the resource. Fixing this by correctly evaluating the size
    upfront will need some work also  on the virglrenderer side.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> (v2)
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2018-10-06 13:12:44 +02:00
Gert Wollny 5d7858f151 virgl, vtest: Correct the transfer size calculation
The transfer size used in virglrenderer refers to uint32_t, so one
must add 3 and then divide by 4 instead of adding 3/4 which is a no-op
with integers.

Fixes: b3b82fe8ea virgl/vtest: add vtest driver

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2018-10-06 13:12:44 +02:00
Alan Coopersmith 066850edad util: Make xmlconfig.c build on Solaris without d_type in dirent (v2)
v2: check for lstat() failing

Fixes: 04bdbbcab3 "xmlconfig: read more config files from drirc.d/"
Signed-off-by: Alan Coopersmith <alan.coopersmith@oracle.com>
Reviewed-by: Roland Mainz <roland.mainz@nrubsig.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2018-10-05 17:30:45 -07:00
Sonny Jiang 084cf3b966 radeonsi:optimizing SET_CONTEXT_REG for shaders vgt_vertex_reuse
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2018-10-05 19:04:13 -04:00
Sonny Jiang ce1d72609d radeonsi:optimizing SET_CONTEXT_REG for shaders Tessellation
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2018-10-05 19:04:13 -04:00
Sonny Jiang 4de328da07 radeonsi:optimizing SET_CONTEXT_REG for shaders PS
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2018-10-05 19:04:13 -04:00
Sonny Jiang f243980f2c radeonsi:optimizing SET_CONTEXT_REG for shaders VS
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2018-10-05 19:04:13 -04:00
Sonny Jiang 4052624398 radeonsi:optimizing SET_CONTEXT_REG for shaders GS
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2018-10-05 19:04:13 -04:00
Marek Olšák 86f004bdfc radeonsi: optimize and allow reg > 31 in radeon_opt_set_context_reg functions
reg_saved will have 64 bits, and (1 << reg) where reg > 31 has undefined
behavior. (1ull << reg) would be correct for 64 bits.

This commit shifts the other way in order to merge the conditions.
2018-10-05 19:04:13 -04:00
Sonny Jiang eeb9170599 radeonsi: optimizing SET_CONTEXT_REG for shaders ES
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2018-10-05 17:53:52 -04:00
Samuel Pitoiset a1bc152340 spirv: mark variables decorated with XfbBuffer as always active
Otherwise, they are removed during NIR linking or in some
lowering passes.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-10-05 18:13:25 +02:00
Jason Ekstrand dd553bc67f nir/alu_to_scalar: Use ssa_for_alu_src in hand-rolled expansions
The ssa_for_alu_src helper will correctly handle swizzles and other
source modifiers for you.  The expansions for unpack_half_2x16,
pack_uvec2_to_uint, and pack_uvec4_to_uint were all broken with regards
to swizzles.  The brokenness of unpack_half_2x16 was causing rendering
errors in Rise of the Tomb Raider on Intel ever since c11833ab24
which added an extra copy propagation to the optimization pipeline and
caused us to start seeing swizzles where we hadn't seen any before.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107926
Fixes: 9ce901058f "nir: Add lowering of nir_op_unpack_half_2x16."
Fixes: 9b8786eba9 "nir: Add lowering support for packing opcodes."
Tested-by: Alex Smith <asmith@feralinteractive.com>
Tested-by: Józef Kucia <joseph.kucia@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2018-10-04 12:43:59 -05:00
Vadym Shovkoplias 5f0567a4f6 glsl/linker: Check the subroutine associated functions names
>From Section 6.1.2 (Subroutines) of the GLSL 4.00 specification

    "A program will fail to compile or link if any shader
     or stage contains two or more functions with the same
     name if the name is associated with a subroutine type."

v2:
  - error out earlier (Tapani)
  - style fixes (Iago)

Fixes:
    * no-overloads.vert

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108109
Signed-off-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com>

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2018-10-04 17:41:19 +02:00
Tomeu Vizoso ed53a79cf8 virgl: Negotiate version with vtest server
Check if server supports version negotation by sending a PING_PROTOCOL_VERSION
message right before a dummy RESOURCE_BUSY_WAIT. If we don't get a reply
for the first, we know the server doesn't support it.

If it does support it, we can query the max protocol version supported
by the server and fall back if needed.

v2: - Send a new message to negotiate the protocol version, checking if
      the server supports this message by immediately sending a busy wait
      message. (Dave Airlie)

v3: - Send a zero-arg command PING_PROTOCOL_VERSION so we actually keep
      compatibility with older servers. (Code by Dave Airlie)

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2018-10-04 16:18:36 +02:00
Sagar Ghuge 0c70e11206 intel: aubinator: Fix memory leaks
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-10-04 10:01:56 +01:00
Sagar Ghuge 29a2eaf3db intel/decoder: construct correct xml filename
construct correct gen xml filename when we try to load hardware xml
description from a given path

v2: remove temporary variable (Francesco Ansanelli)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-10-04 10:01:56 +01:00
Sagar Ghuge f9c8468c82 intel/decoder: Avoid freeing invalid pointer
v2: Free ctx.spec if error while reading genxml (Lionel Landwerlin)

v3: Handle case where genxml is empty (Lionel Landwerlin)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-10-04 10:01:56 +01:00
Sagar Ghuge ba3304e764 intel/decoder: add gen_spec_init method
Initialize gen_spec instance properly when loading hardware xml
description from specifc directory to avoid segmentation fault.

v2: correct function definition (Lionel Landwerlin)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-10-04 10:01:56 +01:00
Samuel Pitoiset 2b34985d93 radv: fix resetting the pool for timestamp queries
Since the driver no longer uses the availability bit for
timestamp queries it shouldn't reset it. Instead, it should
reset the query values to UINT32_MAX. This fixes VM faults.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108164
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Józef Kucia <joseph.kucia@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-10-04 10:56:25 +02:00
Guido Günther b2a876a42b etnaviv: Use write combine instead of unached mappings for shader bo
The later are sensitive to unaligned accesses on arm64[1] and we don't
need an uncached mapping here.

[1]: https://lists.freedesktop.org/archives/etnaviv/2018-September/001956.html

Signed-off-by: Guido Günther <guido.gunther@puri.sm>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
2018-10-04 10:33:25 +02:00
Marek Olšák 8e0b4cb8a1 drirc: add a workaround for ARMA 3
Cc: 18.2 <mesa-stable@lists.freedesktop.org>
2018-10-04 01:01:54 -04:00
Jason Ekstrand f5bab06428 anv/batch_chain: Don't start a new BO just for BATCH_BUFFER_START
Previously, we just went ahead and emitted MI_BATCH_BUFFER_START as
normal.  If we are near enough to the end, this can cause us to start a
new BO just for the MI_BATCH_BUFFER_START which messes up chaining.  We
always reserve enough space at the end for an MI_BATCH_BUFFER_START so
we can just increment cmd_buffer->batch.end prior to emitting the
command.

Fixes: a0b133286a "anv/batch_chain: Simplify secondary batch return..."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107926
Tested-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-10-03 09:03:12 -05:00
Jason Ekstrand 7a89a0d9ed anv: Use separate MOCS settings for external BOs
On Broadwell and above, we have to use different MOCS settings to allow
the kernel to take over and disable caching when needed for external
buffers.  On Broadwell, this is especially important because the kernel
can't disable eLLC so we have to do it in userspace.  We very badly
don't want to do that on everything so we need separate MOCS for
external and internal BOs.

In order to do this, we add an anv-specific BO flag for "external" and
use that to distinguish between buffers which may be shared with other
processes and/or display and those which are entirely internal.  That,
together with an anv_mocs_for_bo helper lets us choose the right MOCS
settings for each BO use.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99507
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-10-03 09:03:03 -05:00
Emil Velikov fe8be81b4a Revert "mesa: remove unnecessary 'sort by year' for the GL extensions"
This reverts commit 3d81e11b49.

As reported by Federico, some games require the 'sort by year' since
they truncate the extensions which do not fit the fixed size string
array.

Seemingly I did not consider that, as the documentation (both Mesa and
Nvidia) mentions about program crashes ... which are worked around by
setting the env. variable.

This commit reinstates the workaround and enhances the documentation.

Cc: Marek Olšák <maraeo@gmail.com>
Cc: Ian Romanick <idr@freedesktop.org>
Reported-by: Federico Dossena <info@fdossena.com>
Fixes: 3d81e11b49 ("mesa: remove unnecessary 'sort by year' for the GL
extensions")
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Federico Dossena <info@fdossena.com>
2018-10-03 13:38:06 +01:00
Emil Velikov 91ff8b1dd9 mesa: reorder and document the tokens in glheader.h
Split into different sections, document each one as well as strange
cases like GL_ATI_texture_compression_3dc.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-10-03 13:38:06 +01:00
Emil Velikov 5f70964b1d mesa: remove duplicate declarations from glheader.h
Remove all the desktop GL and GLX entries from the list.
Former are pulled by the gl.h and glext.h includes at the top while the
latter are no longer needed.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-10-03 13:38:06 +01:00
Emil Velikov 01b92916af i965: reference __DRI_ATTRIB_SWAP_COPY token over the GLX one
Earlier commit updated the code to use the DRI tokens, yet forgot to
update the comment.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-10-03 13:38:06 +01:00
Emil Velikov e04b2c0376 i915: reference __DRI_ATTRIB_SWAP_COPY token over the GLX one
Earlier commit updated the code to use the DRI tokens, yet forgot to
update the comment.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-10-03 13:38:06 +01:00
Emil Velikov d26b122ee8 dri/common: move the required GLX_* token definitions locally
Will allow us to remove even bigger hack elsewhere. But more
importantly, we should not be using _any_ GLX tokens in DRI.

Document the gory details about the current side-effects.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-10-03 13:38:06 +01:00
Emil Velikov 4ef53669af dri/common: use __DRI_ATTRIB_SWAP* instances when describing db_modes
Somewhat recently Thomas Hellstrom added the respective DRI tokens
and updated the drivers. Update the documentation to match reality.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-10-03 13:38:06 +01:00
Emil Velikov d6a6760139 egl/x11: remove eglSwap* surface check
Already handled further up in eglapi.c.

To make things a tiny bit strange, X11+DRI3 was doing the wrong thing by
returning EGL_FALSE (+ no error), while X11+DRI2 was returning EGL_TRUE.

Cc: samiuddi <sami.uddin.mohammad@intel.com>
Cc: Eric Engestrom <eric.engestrom@intel.com>
Cc: Erik Faye-Lund <kusmabite@gmail.com>
Cc: Tomasz Figa <tfiga@chromium.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2018-10-03 13:38:06 +01:00
Emil Velikov 8030741996 egl/surfaceless: remove eglSwap* stubs
The API validation in eglapi.c already returns if the surface type is
!window.

Cc: samiuddi <sami.uddin.mohammad@intel.com>
Cc: Erik Faye-Lund <kusmabite@gmail.com>
Cc: Tomasz Figa <tfiga@chromium.org>
Cc: Gurchetan Singh <gurchetansingh@chromium.org>
Cc: Chad Versace <chadversary@chromium.org>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-10-03 13:38:06 +01:00
Emil Velikov a370e278d3 egl/drm: remove eglSwap* surface check
Already handled further up in eglapi.c

Cc: samiuddi <sami.uddin.mohammad@intel.com>
Cc: Erik Faye-Lund <kusmabite@gmail.com>
Cc: Tomasz Figa <tfiga@chromium.org>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-10-03 13:38:06 +01:00
Emil Velikov 91ccb59ff4 egl/android: remove eglSwap* surface check
Already handled further up in eglapi.c

Cc: samiuddi <sami.uddin.mohammad@intel.com>
Cc: Erik Faye-Lund <kusmabite@gmail.com>
Cc: Tomasz Figa <tfiga@chromium.org>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-10-03 13:38:06 +01:00
Emil Velikov 8f66743ca2 egl: make eglSwapBuffers* a no-op for !window surfaces
Analogous to the previous commit - the spec says the function is a
no-op when a pbuffer or pixmap surface is used.

Cc: samiuddi <sami.uddin.mohammad@intel.com>
Cc: Erik Faye-Lund <kusmabite@gmail.com>
Cc: Tomasz Figa <tfiga@chromium.org>
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-10-03 13:38:05 +01:00
Emil Velikov 64b4ccde0c egl: make eglSwapInterval a no-op for !window surfaces
As the spec says, the function is a no-op when the surface is not a
window one.

That spec implies that EGL_TRUE should be returned in that case, yet
the ARM driver seems to return EGL_FALSE + EGL_BAD_SURFACE.

The Nvidia driver returns EGL_TRUE. We follow that behaviour until a
decision is made.

https://gitlab.khronos.org/egl/API/merge_requests/17

Cc: samiuddi <sami.uddin.mohammad@intel.com>
Cc: Erik Faye-Lund <kusmabite@gmail.com>
Cc: Tomasz Figa <tfiga@chromium.org>
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-10-03 13:38:05 +01:00
Emil Velikov c231b49c53 freedreno: add the a6xx sources to the Android build
Add the files otherwise things just won't build.
Haven't actually tested it, but it's a small step in the right
direction.

Fixes: de3b34df97 ("freedreno: Add a6xx backend")
Cc: Kristian H. Kristensen <hoegsberg@chromium.org>
Cc: Rob Clark <robdclark@gmail.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2018-10-03 13:38:05 +01:00
Emil Velikov 7419b22413 pipe-loader: add a dup() in pipe_loader_sw_probe_kms
The pipe_loader_release API closes the fd given, even if the pipe-loader
should _not_ take ownership of it.

With earlier commit we fixed pipe_loader_drm_probe_fd, and now with
cover the final piece.

Note that unlike the DRM case, here the caller _did_ forget to dup
before using it ... most likely leading to all sorts of fun.

Don't forget the close in the error path. Seems like the things are a
bit leaky/asymmetrical with the semi-recent config work. But we can shave
that yak another day ;-)

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2018-10-03 13:38:05 +01:00
Emil Velikov 6ccc435e7a pipe-loader: move dup(fd) within pipe_loader_drm_probe_fd
Currently pipe_loader_drm_probe_fd takes ownership of the fd given.
To match that, pipe_loader_release closes it.

Yet we have many instances which do not want the change of ownership,
and thus duplicate the fd before passing it to the pipe-loader.

Move the dup() within pipe-loader, explicitly document that and document
all the cases through the codebase.

A trivial git grep -2 pipe_loader_release makes things as obvious as it
gets ;-)

Cc: Leo Liu <leo.liu@amd.com>
Cc: Thomas Hellstrom <thellstrom@vmware.com>
Cc: Axel Davy <davyaxel0@gmail.com>
Cc: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Axel Davy <davyaxel0@gmail.com> (for nine)
2018-10-03 13:38:05 +01:00
Emil Velikov 7b8d1b313c st/nine: do not double-close the fd on teardown
As the newly introduced comment says:
 The pipe loader takes ownership of the fd

Thus, there's no need to close it again.

Cc: Patrick Rudolph <siro@das-labor.org>
Cc: Axel Davy <davyaxel0@gmail.com>
Cc: mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Axel Davy <davyaxel0@gmail.com>
2018-10-03 13:38:05 +01:00
Emil Velikov fa9df82f67 mesa: fold _glapi_check_multithread() back into _mesa_make_current
With commit c6c0f94714, back in 2006 Brian removed the
_glapi_check_multithread() call from core mesa - _mesa_make_current.

It was done to remove fairly awkward #ifdef guard which caused subtle
differences in core mesa.

Since that guard is long gone, we can drop the duplication and
reintroduce the call in core.

Note that the function is was missing when using EGL + classic dri HW
drivers. Yet on TLS builds it's a no-op, so we're safe.

Any non TLS users - more or less anything !Linux (or even musl on Linux
up-to semi-recently) may have experienced problems.

v2: don't remove the call from swrast - move it to core (Eric)

Cc: Eric Anholt <eric@anholt.net>
Cc: Brian Paul <brianp@vmware.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2018-10-03 13:38:05 +01:00
Emil Velikov d081ad2aa2 vl/dri3: do full teardown on screen_destroy
Earlier commit added support for 'front_buffers', erroneously adding a
return in vl_dri3_screen_destroy. Effectively leaking a lot of state.

Fixes: 8d7ac0a4e4 ("vl/dri3: implement DRI3 BufferFromPixmap")
Cc: Leo Liu <leo.liu@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2018-10-03 13:38:05 +01:00