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radeonsi:optimizing SET_CONTEXT_REG for shaders Tessellation 

Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
This commit is contained in:
Sonny Jiang 2018-10-03 11:53:13 -04:00 committed by Marek Olšák
parent 4de328da07
commit ce1d72609d
4 changed files with 26 additions and 5 deletions
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1
src/gallium/drivers/radeonsi/si_gfx_cs.c
View File

@ -376,6 +376,7 @@ void si_begin_new_gfx_cs(struct si_context *ctx)
ctx->tracked_regs.reg_value[SI_TRACKED_SPI_SHADER_Z_FORMAT] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_SPI_SHADER_COL_FORMAT] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_CB_SHADER_MASK] = 0xffffffff;
ctx->tracked_regs.reg_value[SI_TRACKED_VGT_TF_PARAM] = 0x00000000;
/* Set all saved registers state to saved. */
ctx->tracked_regs.reg_saved = 0xffffffffffffffff;

3
src/gallium/drivers/radeonsi/si_shader.h
View File

@ -686,6 +686,9 @@ struct si_shader {
unsigned cb_shader_mask;
} ps;
} ctx_reg;
/*For save precompute registers value */
unsigned vgt_tf_param; /* VGT_TF_PARAM */
};
struct si_shader_part {

1
src/gallium/drivers/radeonsi/si_state.h
View File

@ -312,6 +312,7 @@ enum si_tracked_reg {
SI_TRACKED_SPI_SHADER_COL_FORMAT,
SI_TRACKED_CB_SHADER_MASK,
SI_TRACKED_VGT_TF_PARAM,
SI_NUM_TRACKED_REGS,
};

26
src/gallium/drivers/radeonsi/si_state_shaders.c
View File

@ -396,11 +396,11 @@ static void si_set_tesseval_regs(struct si_screen *sscreen,
} else
distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
S_028B6C_TYPE(type) |
S_028B6C_PARTITIONING(partitioning) |
S_028B6C_TOPOLOGY(topology) |
S_028B6C_DISTRIBUTION_MODE(distribution_mode));
assert(pm4->shader);
pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) |
S_028B6C_PARTITIONING(partitioning) |
S_028B6C_TOPOLOGY(topology) |
S_028B6C_DISTRIBUTION_MODE(distribution_mode);
}
/* Polaris needs different VTX_REUSE_DEPTH settings depending on
@ -568,6 +568,12 @@ static void si_emit_shader_es(struct si_context *sctx)
radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
shader->selector->esgs_itemsize / 4);
if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
SI_TRACKED_VGT_TF_PARAM,
shader->vgt_tf_param);
}
static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
@ -802,6 +808,11 @@ static void si_emit_shader_gs(struct si_context *sctx)
radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL)
radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
SI_TRACKED_VGT_TF_PARAM,
shader->vgt_tf_param);
}
}
@ -965,6 +976,11 @@ static void si_emit_shader_vs(struct si_context *sctx)
radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
SI_TRACKED_PA_CL_VTE_CNTL,
shader->ctx_reg.vs.pa_cl_vte_cntl);
if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
SI_TRACKED_VGT_TF_PARAM,
shader->vgt_tf_param);
}
/**