Commit Graph

96034 Commits

Author SHA1 Message Date
Marek Olšák 06bfb2d28f r600: fork and import gallium/radeon
This marks the end of code sharing between r600 and radeonsi.
It's getting difficult to work on radeonsi without breaking r600.

A lot of functions had to be renamed to prevent linker conflicts.
There are also minor cleanups.

Acked-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-09-26 04:21:14 +02:00
Kenneth Graunke e1623da818 i965: Rename do_flush_locked to submit_batch().
do_flush_locked isn't a great name - especially given that there's no
locking going on in our code relating to execbuf.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2017-09-25 15:15:13 -07:00
Kenneth Graunke 962cc1bd17 i965: Use atomic ops in get_new_program_id().
We have a nice utility function for this, which eliminates the need for
locking stuff.  This isn't really performance critical, but it's less
code to use the atomic.

p_atomic_inc_return does pre-increment rather than post-increment, so we
change screen->program_id to be initialized to 0 instead of 1.  At which
point, we can just delete the initialization because intel_screen is
rzalloc'd.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2017-09-25 15:15:09 -07:00
Kenneth Graunke 2eb26a9986 i965: Convert brw_bufmgr to use C11 mutexes instead of pthreads.
There's no real advantage or disadvantage here, it's just for stylistic
consistency with the rest of the codebase.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2017-09-25 15:15:01 -07:00
Kenneth Graunke 93bb91452a i965: Delete dead meta stencil blit program fields from brw_context.
These have been unused for a while now.
2017-09-25 15:14:44 -07:00
Tim Rowley 5a2bca5db5 swr/rast: Handle instanceID offset / Instance Stride enable
Supported in JitGatherVertices(); FetchJit::JitLoadVertices() may require
similar changes, will need address this if it is determined that this
path is still in use.

Handle Force Sequential Access in FetchJit::Create.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-09-25 13:38:57 -05:00
Tim Rowley 68d8dd1fb5 swr/rast: Remove code supporting legacy llvm (<3.9)
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-09-25 13:38:57 -05:00
Tim Rowley 9c468c775b swr/rast: Fix allocation of DS output data for USE_SIMD16_FRONTEND
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-09-25 13:38:57 -05:00
Tim Rowley d18c2a1fa4 swr/rast: Slightly more efficient blend jit
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-09-25 13:38:57 -05:00
Tim Rowley 5033d49d5d swr/rast: Properly sized null GS buffer
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-09-25 13:38:57 -05:00
Tim Rowley 9c82cf0f1e swr/rast: Move SWR_GS_CONTEXT from thread local storage to stack
Move structure, as the size is significantly reduced due to dynamic
allocation of the GS buffers.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-09-25 13:38:57 -05:00
Tim Rowley efe7fa4384 swr/rast: Fetch compile state changes
Add ForceSequentialAccessEnable and InstanceIDOffsetEnable bools to
FETCH_COMPILE_STATE.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-09-25 13:38:57 -05:00
Tim Rowley cd6e91d3a2 swr/rast: New GS state/context API
One piglit regression, which was a false pass:
  spec@glsl-1.50@execution@geometry@dynamic_input_array_index

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-09-25 13:38:57 -05:00
Tim Rowley 41565ddf7a swr/rast: Add support for R10G10B10_FLOAT_A2_UNORM pixel format
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-09-25 13:38:57 -05:00
Samuel Pitoiset 1cf508b731 radv: save/restore all viewports/scissors for meta operations
This is needed since we don't update the number of viewports/scissors
when they are set dynamically (according to the spec). In the following
scenario:

* vkCmdSetViewport()
* vkCmdClearColorImage() (or any other meta operations)

The viewports/scissors weren't saved correctly because no pipeline
was bound before, and thus the number of viewports/scissors were 0.

This fixes a regression with:

dEQP-VK.draw.negative_viewport_height.front_ccw_cull_back

Fixes: 60878dd00c ("radv: do not update the number of viewports in vkCmdSetViewport()")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-09-25 20:31:55 +02:00
Juan A. Suarez Romero 0509b27b9d docs: update calendar, add news item and link release notes for 17.1.10
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
2017-09-25 17:08:20 +00:00
Juan A. Suarez Romero 0ac0e32ce1 docs: add sha256 checksums for 17.1.10
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit 60df95c6bd8c8cc0d440f3940bbbe936d490c67d)
2017-09-25 17:01:22 +00:00
Juan A. Suarez Romero 3e9ba8d0f5 docs: add release notes for 17.1.10
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit 834d6c60db266c7d7dfd973729f20379dd3da287)
2017-09-25 17:01:18 +00:00
Eric Engestrom adea68a8a2 git_sha1_gen: fix output on python3
String handling has changed on python3.

Before this patch, on python3:
	#define MESA_GIT_SHA1 "git-b'b99dcbfeb3'"
After:
	#define MESA_GIT_SHA1 "git-b99dcbfeb3"

(No change on python2, it always looked ok)

Cc: Jose Fonseca <jfonseca@vmware.com>
Fixes: b99dcbfeb3 "build: Convert git_sha1_gen script to Python."
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2017-09-25 14:58:26 +01:00
Leo Liu f3ed1d2f6b st/va/postproc: implement the DRM prime grabber
Acked-by: Christian König <christian.koenig@amd.com>
2017-09-25 09:42:14 -04:00
Leo Liu b47bdf55dc vl/compositor: convert RGB buffer to YUV with color conversion
Acked-by: Christian König <christian.koenig@amd.com>
2017-09-25 09:42:14 -04:00
Leo Liu 737d13637d vl/csc: add a RGB to YUV CSC matrix
Acked-by: Christian König <christian.koenig@amd.com>
2017-09-25 09:42:14 -04:00
Leo Liu a2ebe57992 vl/compositor: create RGB to YUV fragment shader
Acked-by: Christian König <christian.koenig@amd.com>
2017-09-25 09:42:14 -04:00
Leo Liu 169c077d1d st/va/postproc: use progressive target buffer for scaling
Scaling between interlaced buffers, esp. for scale-up, because
blit will scale up top filed and bottom field separately. it'll
result in the weaving for these buffer with lack of accuracy.
So use shader deint for the case.

Acked-by: Christian König <christian.koenig@amd.com>
2017-09-25 09:42:14 -04:00
Leo Liu 1d1299f8a4 st/va: make internal func vlVaHandleSurfaceAllocate() call simpler
Acked-by: Christian König <christian.koenig@amd.com>
2017-09-25 09:42:14 -04:00
Leo Liu 96f89f440b st/va/postproc: add a full NV12 deint support from buffer I to P
Before it's impossible to transcode an interlaced video, becasue if
in order for encoder to work, we have to force buffer to progessive,
but the deint with buffer from I to P is missing. Now along With
the new YUV deint full function, it works with weave and bob deint.

Also this will benefit transcoding video with scaling parameters.

Acked-by: Christian König <christian.koenig@amd.com>
2017-09-25 09:42:14 -04:00
Leo Liu 4f9e7b1279 vl/compositor: add Bob top and bottom to YUV deint function
Acked-by: Christian König <christian.koenig@amd.com>
2017-09-25 09:42:14 -04:00
Leo Liu 9484852cdb vl/compositor: remove vl_compositor_yuv_deint() function
No longer used.

Acked-by: Christian König <christian.koenig@amd.com>
2017-09-25 09:42:13 -04:00
Leo Liu 3ad8687295 st/va: use new vl_compositor_yuv_deint_full() to deint
We also set src rectangle explicitly just in case of the mismatch
of size between interlaced buffer and progressive buffer

Acked-by: Christian König <christian.koenig@amd.com>
2017-09-25 09:42:13 -04:00
Leo Liu db28fdc0ad st/omx: use new vl_compositor_yuv_deint_full() to deint
v2: add dst rect to make sure no scale

Acked-by: Christian König <christian.koenig@amd.com>
2017-09-25 09:42:13 -04:00
Leo Liu 001358a97c vl/compositor: add a new function for YUV deint
It will replace previous deint function with abilities of
scaling and field deinterlacing

Acked-by: Christian König <christian.koenig@amd.com>
2017-09-25 09:42:13 -04:00
Leo Liu abd05a6cc4 vl/compositor: extend YUV deint function to do field deint
It will add Bob deint ability to interlaced video for HW encoder

Acked-by: Christian König <christian.koenig@amd.com>
2017-09-25 09:42:13 -04:00
Leo Liu 4ef0828946 vl/compositor: separate YUV part from shader video buffer function
So that it can be re-used

Acked-by: Christian König <christian.koenig@amd.com>
2017-09-25 09:42:13 -04:00
Leo Liu eb51838771 st/va/postproc: use video original size for postprocessing
Otherwise the aligned size will make video scaled

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-09-25 09:42:13 -04:00
Bas Nieuwenhuizen 3e685ec983 radv: Fix VK_KHR_image_format_list.
Spec adding corner cases ...

Fixes: 969537d935 "radv: Add support for more DCC compression with VK_KHR_image_format_list."
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-09-25 15:36:19 +02:00
Bas Nieuwenhuizen bf0397b6f5 Revert "Revert "radv: fallback to an in-memory cache when no pipline cache is provided""
I tested this 10 times with
./deqp-vk --deqp-case=dEQP-VK.texture.filtering.3d.formats.r4g4b4a4*

and one full run of CTS, seems the issue is gone.

Also reduces CTS runtime by 30% or so.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-09-25 15:36:19 +02:00
Eric Engestrom bb66af95a7 scons: use python3-compatible exceptions
These changes were generated using python's `2to3` tool.

Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-09-25 12:05:47 +01:00
Eric Engestrom eb2efbba78 scons: use python3-compatible generator
These changes were generated using python's `2to3` tool.

Suggested-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-09-25 12:05:47 +01:00
Eric Engestrom e361047568 scons: use python3-compatible lists
These changes were generated using python's `2to3` tool.

Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2017-09-25 12:05:44 +01:00
Eric Engestrom 29c8d755ea scons: use python3-compatible list-key check
These changes were generated using python's `2to3` tool.

Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-09-25 11:58:53 +01:00
Eric Engestrom 7d48219b3a scons: use python3-compatible print()
These changes were generated using python's `2to3` tool.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102852
Reported-by: Alex Granni <liviuprodea@yahoo.com>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2017-09-25 11:57:12 +01:00
Samuel Pitoiset 3f6a17a8fc radv: init the trace BO before compiling meta shaders
Otherwise, the disasm string is NULL for meta shaders.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-09-25 10:47:01 +02:00
Samuel Pitoiset 6f8c40734b radv: make radv_pipeline_init() static
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-09-25 10:46:59 +02:00
Samuel Pitoiset 2aea632292 radv: remove unused variable in radv_dump_annotated_shader()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-09-25 10:46:57 +02:00
Samuel Pitoiset 45ea90ef1f radv: make use of ATI_VENDOR_ID everywhere
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-09-25 10:46:55 +02:00
Samuel Iglesias Gonsálvez d2cd9deeb8 anv: fix viewport transformation for z component
In Vulkan, for 'z' (depth) component, the scale and translate values
for the viewport transformation are:

pz = maxDepth - minDepth
oz = minDepth

zf = pz × zd + oz

Being zd, the third component in vertex's normalized device coordinates.

Fixes: dEQP-VK.draw.inverted_depth_ranges.*

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: mesa-stable@lists.freedesktop.org
2017-09-25 06:39:40 +02:00
David Airlie 3e54493265 radv: add gfx9 scissor workaround
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: 17.2 <mesa-stable@lists.freedesktop.org>
2017-09-24 05:50:02 +02:00
Adam Jackson 52ed3bca91 glx: Sort the GLX extension bit enum and table
Not quite asciibetical: ARB, then EXT, then vendor, just like the GL
extension enum just below. No functional change, but it bothered me.

Signed-off-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-09-22 21:13:45 -04:00
Wladimir J. van der Laan 3f7093bed2 etnaviv: Add missing includes after 6ace0b8
Add missing includes after 6ace0b8 (etnaviv: don't enable RT
full-overwrite when logicop is enabled), otherwise the etnaviv driver
won't build because of missing macros.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Andres Gomez <agomez@igalia.com>
2017-09-22 20:49:03 +02:00
Lucas Stach e9d37d68cf etnaviv: fix 16bpp clears
util_pack_color may leave undefined values in the upper half of the packed
integer. As our hardware needs the upper 16 bits to mirror the lower 16bits,
this breaks clears of those formats if the undefined values aren't masked off.

I've only observed the issue with R5G6B5_UNORM surfaces, other 16bpp
formats seem to work fine.

Fixes: d6aa2ba2b2 (etnaviv: replace translate_clear_color with util_pack_color)
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-09-22 20:48:32 +02:00