radeonsi: remove workarounds for radeon DRM < 2.45.0

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17411>

src/amd/common/ac_gpu_info.c

@@ -888,22 +888,15 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
    info->has_timeline_syncobj = has_timeline_syncobj(fd);
    info->has_fence_to_handle = info->has_syncobj && info->drm_minor >= 21;
    info->has_local_buffers = info->drm_minor >= 20;
-   info->kernel_flushes_hdp_before_ib = true;
-   info->htile_cmask_support_1d_tiling = true;
    info->si_TA_CS_BC_BASE_ADDR_allowed = true;
    info->has_bo_metadata = true;
-   info->has_gpu_reset_status_query = true;
    info->has_eqaa_surface_allocator = info->gfx_level < GFX11;
-   info->has_format_bc1_through_bc7 = true;
-   info->has_indirect_compute_dispatch = true;
    /* GFX6 doesn't support unaligned loads. */
    info->has_unaligned_shader_loads = info->gfx_level != GFX6;
    /* Disable sparse mappings on GFX6 due to VM faults in CP DMA. Enable them once
     * these faults are mitigated in software.
     */
    info->has_sparse_vm_mappings = info->gfx_level >= GFX7 && info->drm_minor >= 13;
-   info->has_2d_tiling = true;
-   info->has_read_registers_query = true;
    info->has_scheduled_fence_dependency = info->drm_minor >= 28;
    info->mid_command_buffer_preemption_enabled = amdinfo->ids_flags & AMDGPU_IDS_FLAGS_PREEMPTION;
    info->has_tmz_support = has_tmz_support(dev, info, amdinfo);
@@ -1498,18 +1491,11 @@ void ac_print_gpu_info(struct radeon_info *info, FILE *f)
    fprintf(f, "    has_timeline_syncobj = %u\n", info->has_timeline_syncobj);
    fprintf(f, "    has_fence_to_handle = %u\n", info->has_fence_to_handle);
    fprintf(f, "    has_local_buffers = %u\n", info->has_local_buffers);
-   fprintf(f, "    kernel_flushes_hdp_before_ib = %u\n", info->kernel_flushes_hdp_before_ib);
-   fprintf(f, "    htile_cmask_support_1d_tiling = %u\n", info->htile_cmask_support_1d_tiling);
    fprintf(f, "    si_TA_CS_BC_BASE_ADDR_allowed = %u\n", info->si_TA_CS_BC_BASE_ADDR_allowed);
    fprintf(f, "    has_bo_metadata = %u\n", info->has_bo_metadata);
-   fprintf(f, "    has_gpu_reset_status_query = %u\n", info->has_gpu_reset_status_query);
    fprintf(f, "    has_eqaa_surface_allocator = %u\n", info->has_eqaa_surface_allocator);
-   fprintf(f, "    has_format_bc1_through_bc7 = %u\n", info->has_format_bc1_through_bc7);
-   fprintf(f, "    has_indirect_compute_dispatch = %u\n", info->has_indirect_compute_dispatch);
    fprintf(f, "    has_unaligned_shader_loads = %u\n", info->has_unaligned_shader_loads);
    fprintf(f, "    has_sparse_vm_mappings = %u\n", info->has_sparse_vm_mappings);
-   fprintf(f, "    has_2d_tiling = %u\n", info->has_2d_tiling);
-   fprintf(f, "    has_read_registers_query = %u\n", info->has_read_registers_query);
    fprintf(f, "    has_stable_pstate = %u\n", info->has_stable_pstate);
    fprintf(f, "    has_scheduled_fence_dependency = %u\n", info->has_scheduled_fence_dependency);
    fprintf(f, "    mid_command_buffer_preemption_enabled = %u\n",

src/amd/common/ac_gpu_info.h

@@ -183,18 +183,11 @@ struct radeon_info {
    bool has_timeline_syncobj;
    bool has_fence_to_handle;
    bool has_local_buffers;
-   bool kernel_flushes_hdp_before_ib;
-   bool htile_cmask_support_1d_tiling;
    bool si_TA_CS_BC_BASE_ADDR_allowed;
    bool has_bo_metadata;
-   bool has_gpu_reset_status_query;
    bool has_eqaa_surface_allocator;
-   bool has_format_bc1_through_bc7;
-   bool has_indirect_compute_dispatch;
    bool has_unaligned_shader_loads;
    bool has_sparse_vm_mappings;
-   bool has_2d_tiling;
-   bool has_read_registers_query;
    bool has_scheduled_fence_dependency;
    bool has_stable_pstate;
    /* Whether SR-IOV is enabled or amdgpu.mcbp=1 was set on the kernel command line. */

src/gallium/drivers/radeonsi/si_buffer.c

@@ -67,15 +67,6 @@ void si_init_resource_fields(struct si_screen *sscreen, struct si_resource *res,
       res->domains = RADEON_DOMAIN_GTT;
       break;
    case PIPE_USAGE_DYNAMIC:
-      /* Older kernels didn't always flush the HDP cache before
-       * CS execution
-       */
-      if (!sscreen->info.kernel_flushes_hdp_before_ib) {
-         res->domains = RADEON_DOMAIN_GTT;
-         res->flags |= RADEON_FLAG_GTT_WC;
-         break;
-      }
-      FALLTHROUGH;
    case PIPE_USAGE_DEFAULT:
    case PIPE_USAGE_IMMUTABLE:
    default:
@@ -98,7 +89,7 @@ void si_init_resource_fields(struct si_screen *sscreen, struct si_resource *res,
        * radeon doesn't have good BO move throttling, so put all
        * persistent buffers into GTT to prevent VRAM CPU page faults.
        */
-      if (!sscreen->info.kernel_flushes_hdp_before_ib || !sscreen->info.is_amdgpu)
+      if (!sscreen->info.is_amdgpu)
          res->domains = RADEON_DOMAIN_GTT;
    }
 

src/gallium/drivers/radeonsi/si_clear.c

@@ -713,10 +713,6 @@ static void si_fast_clear(struct si_context *sctx, unsigned *buffers,
          continue;
       }
 
-      if (sctx->gfx_level <= GFX8 && tex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_1D &&
-          !sctx->screen->info.htile_cmask_support_1d_tiling)
-         continue;
-
       /* Use a slow clear for small surfaces where the cost of
        * the eliminate pass can be higher than the benefit of fast
        * clear. The closed driver does this, but the numbers may differ.

src/gallium/drivers/radeonsi/si_debug.c

@@ -302,9 +302,6 @@ static void si_dump_mmapped_reg(struct si_context *sctx, FILE *f, unsigned offse
 
 static void si_dump_debug_registers(struct si_context *sctx, FILE *f)
 {
-   if (!sctx->screen->info.has_read_registers_query)
-      return;
-
    fprintf(f, "Memory-mapped registers:\n");
    si_dump_mmapped_reg(sctx, f, R_008010_GRBM_STATUS);
 

src/gallium/drivers/radeonsi/si_get.c

@@ -166,6 +166,8 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_ALLOW_DRAW_OUT_OF_ORDER:
    case PIPE_CAP_QUERY_SO_OVERFLOW:
    case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
+   case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
+   case PIPE_CAP_TEXTURE_MULTISAMPLE:
       return 1;
 
    case PIPE_CAP_TEXTURE_TRANSFER_MODES:
@@ -195,15 +197,9 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
       return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
 
-   case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
-      return sscreen->info.has_gpu_reset_status_query;
-
    case PIPE_CAP_DEVICE_PROTECTED_CONTENT:
       return sscreen->info.has_tmz_support;
 
-   case PIPE_CAP_TEXTURE_MULTISAMPLE:
-      return sscreen->info.has_2d_tiling;
-
    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
       return SI_MAP_BUFFER_ALIGNMENT;
 
@@ -221,8 +217,6 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 
    case PIPE_CAP_GLSL_FEATURE_LEVEL:
    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
-      if (!sscreen->info.has_indirect_compute_dispatch)
-         return 420;
       return 460;
 
    case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
@@ -475,9 +469,8 @@ static int si_get_shader_param(struct pipe_screen *pscreen, enum pipe_shader_typ
    case PIPE_SHADER_CAP_SUPPORTED_IRS:
       if (shader == PIPE_SHADER_COMPUTE) {
          return (1 << PIPE_SHADER_IR_NATIVE) |
-                (sscreen->info.has_indirect_compute_dispatch ?
+                (1 << PIPE_SHADER_IR_NIR) |
-                    (1 << PIPE_SHADER_IR_NIR) |
+                (1 << PIPE_SHADER_IR_TGSI);
-                    (1 << PIPE_SHADER_IR_TGSI) : 0);
       }
       return (1 << PIPE_SHADER_IR_TGSI) |
              (1 << PIPE_SHADER_IR_NIR);

src/gallium/drivers/radeonsi/si_query.c

@@ -1853,12 +1853,10 @@ static unsigned si_get_num_queries(struct si_screen *sscreen)
    }
 
    /* radeon */
-   if (sscreen->info.has_read_registers_query) {
+   if (sscreen->info.gfx_level == GFX7)
-      if (sscreen->info.gfx_level == GFX7)
+      return ARRAY_SIZE(si_driver_query_list) - 6;
-         return ARRAY_SIZE(si_driver_query_list) - 6;
+   else
-      else
+      return ARRAY_SIZE(si_driver_query_list) - 7;
-         return ARRAY_SIZE(si_driver_query_list) - 7;
-   }
 
    return ARRAY_SIZE(si_driver_query_list) - 21;
 }

src/gallium/drivers/radeonsi/si_state.c

@@ -1868,9 +1868,6 @@ static uint32_t si_translate_texformat(struct pipe_screen *screen, enum pipe_for
    }
 
    if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
-      if (!sscreen->info.has_format_bc1_through_bc7)
-         goto out_unknown;
-
       switch (format) {
       case PIPE_FORMAT_RGTC1_SNORM:
       case PIPE_FORMAT_LATC1_SNORM:
@@ -1913,9 +1910,6 @@ static uint32_t si_translate_texformat(struct pipe_screen *screen, enum pipe_for
    }
 
    if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
-      if (!sscreen->info.has_format_bc1_through_bc7)
-         goto out_unknown;
-
       switch (format) {
       case PIPE_FORMAT_BPTC_RGBA_UNORM:
       case PIPE_FORMAT_BPTC_SRGBA:
@@ -1942,9 +1936,6 @@ static uint32_t si_translate_texformat(struct pipe_screen *screen, enum pipe_for
    }
 
    if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
-      if (!sscreen->info.has_format_bc1_through_bc7)
-         goto out_unknown;
-
       switch (format) {
       case PIPE_FORMAT_DXT1_RGB:
       case PIPE_FORMAT_DXT1_RGBA:

src/gallium/winsys/radeon/drm/radeon_drm_surface.c

@@ -293,10 +293,6 @@ static void si_compute_htile(const struct radeon_info *info,
        surf->flags & RADEON_SURF_NO_HTILE)
       return;
 
-   if (surf->u.legacy.level[0].mode == RADEON_SURF_MODE_1D &&
-       !info->htile_cmask_support_1d_tiling)
-      return;
-
    /* Overalign HTILE on P2 configs to work around GPU hangs in
      * piglit/depthstencil-render-miplevels 585.
      *

src/gallium/winsys/radeon/drm/radeon_drm_winsys.c

@@ -570,21 +570,13 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
                                      ws->accel_working2 < 3);
    ws->info.tcc_cache_line_size = 64; /* TC L2 line size on GCN */
    ws->info.ib_alignment = 4096;
-   ws->info.kernel_flushes_hdp_before_ib = true;
-   /* HTILE is broken with 1D tiling on old kernels and GFX7. */
-   ws->info.htile_cmask_support_1d_tiling = true;
    ws->info.si_TA_CS_BC_BASE_ADDR_allowed = ws->info.drm_minor >= 48;
    ws->info.has_bo_metadata = false;
-   ws->info.has_gpu_reset_status_query = true;
    ws->info.has_eqaa_surface_allocator = false;
-   ws->info.has_format_bc1_through_bc7 = true;
-   ws->info.has_indirect_compute_dispatch = true;
    /* GFX6 doesn't support unaligned loads. */
    ws->info.has_unaligned_shader_loads = ws->info.gfx_level == GFX7 &&
                                          ws->info.drm_minor >= 50;
    ws->info.has_sparse_vm_mappings = false;
-   ws->info.has_2d_tiling = true;
-   ws->info.has_read_registers_query = true;
    ws->info.max_alignment = 1024*1024;
    ws->info.has_graphics = true;
    ws->info.cpdma_prefetch_writes_memory = true;
@@ -669,9 +661,6 @@ uint32_t radeon_drm_get_gpu_reset_counter(struct radeon_drm_winsys *ws)
 {
    uint64_t retval = 0;
 
-   if (!ws->info.has_gpu_reset_status_query)
-      return 0;
-
    radeon_get_drm_value(ws->fd, RADEON_INFO_GPU_RESET_COUNTER,
                         "gpu-reset-counter", (uint32_t*)&retval);
    return retval;