462 lines
16 KiB
C
462 lines
16 KiB
C
/*
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* Copyright © 2014 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
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* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*/
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#include "radeon_drm_winsys.h"
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#include "util/format/u_format.h"
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#include <radeon_surface.h>
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static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
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{
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unsigned index, tileb;
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tileb = 8 * 8 * surf->bpe;
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tileb = MIN2(surf->u.legacy.tile_split, tileb);
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for (index = 0; tileb > 64; index++)
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tileb >>= 1;
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assert(index < 16);
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return index;
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}
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#define G_009910_MICRO_TILE_MODE(x) (((x) >> 0) & 0x03)
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#define G_009910_MICRO_TILE_MODE_NEW(x) (((x) >> 22) & 0x07)
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static void set_micro_tile_mode(struct radeon_surf *surf,
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struct radeon_info *info)
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{
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uint32_t tile_mode;
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if (info->gfx_level < GFX6) {
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surf->micro_tile_mode = 0;
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return;
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}
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tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
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if (info->gfx_level >= GFX7)
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surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
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else
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surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
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}
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static void surf_level_winsys_to_drm(struct radeon_surface_level *level_drm,
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const struct legacy_surf_level *level_ws,
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unsigned bpe)
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{
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level_drm->offset = (uint64_t)level_ws->offset_256B * 256;
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level_drm->slice_size = (uint64_t)level_ws->slice_size_dw * 4;
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level_drm->nblk_x = level_ws->nblk_x;
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level_drm->nblk_y = level_ws->nblk_y;
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level_drm->pitch_bytes = level_ws->nblk_x * bpe;
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level_drm->mode = level_ws->mode;
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}
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static void surf_level_drm_to_winsys(struct legacy_surf_level *level_ws,
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const struct radeon_surface_level *level_drm,
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unsigned bpe)
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{
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level_ws->offset_256B = level_drm->offset / 256;
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level_ws->slice_size_dw = level_drm->slice_size / 4;
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level_ws->nblk_x = level_drm->nblk_x;
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level_ws->nblk_y = level_drm->nblk_y;
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level_ws->mode = level_drm->mode;
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assert(level_drm->nblk_x * bpe == level_drm->pitch_bytes);
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}
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static void surf_winsys_to_drm(struct radeon_surface *surf_drm,
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const struct pipe_resource *tex,
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unsigned flags, unsigned bpe,
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enum radeon_surf_mode mode,
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const struct radeon_surf *surf_ws)
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{
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int i;
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memset(surf_drm, 0, sizeof(*surf_drm));
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surf_drm->npix_x = tex->width0;
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surf_drm->npix_y = tex->height0;
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surf_drm->npix_z = tex->depth0;
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surf_drm->blk_w = util_format_get_blockwidth(tex->format);
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surf_drm->blk_h = util_format_get_blockheight(tex->format);
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surf_drm->blk_d = 1;
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surf_drm->array_size = 1;
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surf_drm->last_level = tex->last_level;
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surf_drm->bpe = bpe;
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surf_drm->nsamples = tex->nr_samples ? tex->nr_samples : 1;
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surf_drm->flags = flags;
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surf_drm->flags = RADEON_SURF_CLR(surf_drm->flags, TYPE);
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surf_drm->flags = RADEON_SURF_CLR(surf_drm->flags, MODE);
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surf_drm->flags |= RADEON_SURF_SET(mode, MODE) |
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RADEON_SURF_HAS_SBUFFER_MIPTREE |
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RADEON_SURF_HAS_TILE_MODE_INDEX;
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switch (tex->target) {
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case PIPE_TEXTURE_1D:
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surf_drm->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
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break;
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case PIPE_TEXTURE_RECT:
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case PIPE_TEXTURE_2D:
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surf_drm->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
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break;
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case PIPE_TEXTURE_3D:
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surf_drm->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
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break;
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case PIPE_TEXTURE_1D_ARRAY:
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surf_drm->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
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surf_drm->array_size = tex->array_size;
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break;
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case PIPE_TEXTURE_CUBE_ARRAY: /* cube array layout like 2d array */
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assert(tex->array_size % 6 == 0);
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FALLTHROUGH;
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case PIPE_TEXTURE_2D_ARRAY:
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surf_drm->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
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surf_drm->array_size = tex->array_size;
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break;
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case PIPE_TEXTURE_CUBE:
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surf_drm->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
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break;
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case PIPE_BUFFER:
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default:
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assert(0);
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}
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surf_drm->bo_size = surf_ws->surf_size;
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surf_drm->bo_alignment = 1 << surf_ws->surf_alignment_log2;
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surf_drm->bankw = surf_ws->u.legacy.bankw;
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surf_drm->bankh = surf_ws->u.legacy.bankh;
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surf_drm->mtilea = surf_ws->u.legacy.mtilea;
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surf_drm->tile_split = surf_ws->u.legacy.tile_split;
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for (i = 0; i <= surf_drm->last_level; i++) {
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surf_level_winsys_to_drm(&surf_drm->level[i], &surf_ws->u.legacy.level[i],
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bpe * surf_drm->nsamples);
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surf_drm->tiling_index[i] = surf_ws->u.legacy.tiling_index[i];
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}
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if (flags & RADEON_SURF_SBUFFER) {
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surf_drm->stencil_tile_split = surf_ws->u.legacy.stencil_tile_split;
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for (i = 0; i <= surf_drm->last_level; i++) {
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surf_level_winsys_to_drm(&surf_drm->stencil_level[i],
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&surf_ws->u.legacy.zs.stencil_level[i],
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surf_drm->nsamples);
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surf_drm->stencil_tiling_index[i] = surf_ws->u.legacy.zs.stencil_tiling_index[i];
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}
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}
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}
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static void surf_drm_to_winsys(struct radeon_drm_winsys *ws,
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struct radeon_surf *surf_ws,
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const struct radeon_surface *surf_drm)
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{
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int i;
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memset(surf_ws, 0, sizeof(*surf_ws));
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surf_ws->blk_w = surf_drm->blk_w;
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surf_ws->blk_h = surf_drm->blk_h;
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surf_ws->bpe = surf_drm->bpe;
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surf_ws->is_linear = surf_drm->level[0].mode <= RADEON_SURF_MODE_LINEAR_ALIGNED;
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surf_ws->has_stencil = !!(surf_drm->flags & RADEON_SURF_SBUFFER);
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surf_ws->flags = surf_drm->flags;
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surf_ws->surf_size = surf_drm->bo_size;
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surf_ws->surf_alignment_log2 = util_logbase2(surf_drm->bo_alignment);
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surf_ws->u.legacy.bankw = surf_drm->bankw;
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surf_ws->u.legacy.bankh = surf_drm->bankh;
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surf_ws->u.legacy.mtilea = surf_drm->mtilea;
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surf_ws->u.legacy.tile_split = surf_drm->tile_split;
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surf_ws->u.legacy.macro_tile_index = cik_get_macro_tile_index(surf_ws);
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for (i = 0; i <= surf_drm->last_level; i++) {
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surf_level_drm_to_winsys(&surf_ws->u.legacy.level[i], &surf_drm->level[i],
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surf_drm->bpe * surf_drm->nsamples);
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surf_ws->u.legacy.tiling_index[i] = surf_drm->tiling_index[i];
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}
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if (surf_ws->flags & RADEON_SURF_SBUFFER) {
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surf_ws->u.legacy.stencil_tile_split = surf_drm->stencil_tile_split;
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for (i = 0; i <= surf_drm->last_level; i++) {
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surf_level_drm_to_winsys(&surf_ws->u.legacy.zs.stencil_level[i],
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&surf_drm->stencil_level[i],
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surf_drm->nsamples);
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surf_ws->u.legacy.zs.stencil_tiling_index[i] = surf_drm->stencil_tiling_index[i];
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}
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}
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set_micro_tile_mode(surf_ws, &ws->info);
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surf_ws->is_displayable = surf_ws->is_linear ||
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surf_ws->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY ||
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surf_ws->micro_tile_mode == RADEON_MICRO_MODE_RENDER;
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}
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static void si_compute_cmask(const struct radeon_info *info,
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const struct ac_surf_config *config,
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struct radeon_surf *surf)
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{
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unsigned pipe_interleave_bytes = info->pipe_interleave_bytes;
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unsigned num_pipes = info->num_tile_pipes;
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unsigned cl_width, cl_height;
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if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
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return;
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assert(info->gfx_level <= GFX8);
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switch (num_pipes) {
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case 2:
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cl_width = 32;
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cl_height = 16;
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break;
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case 4:
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cl_width = 32;
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cl_height = 32;
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break;
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case 8:
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cl_width = 64;
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cl_height = 32;
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break;
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case 16: /* Hawaii */
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cl_width = 64;
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cl_height = 64;
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break;
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default:
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assert(0);
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return;
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}
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unsigned base_align = num_pipes * pipe_interleave_bytes;
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unsigned width = align(surf->u.legacy.level[0].nblk_x, cl_width*8);
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unsigned height = align(surf->u.legacy.level[0].nblk_y, cl_height*8);
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unsigned slice_elements = (width * height) / (8*8);
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/* Each element of CMASK is a nibble. */
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unsigned slice_bytes = slice_elements / 2;
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surf->u.legacy.color.cmask_slice_tile_max = (width * height) / (128*128);
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if (surf->u.legacy.color.cmask_slice_tile_max)
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surf->u.legacy.color.cmask_slice_tile_max -= 1;
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unsigned num_layers;
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if (config->is_3d)
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num_layers = config->info.depth;
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else if (config->is_cube)
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num_layers = 6;
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else
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num_layers = config->info.array_size;
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surf->cmask_alignment_log2 = util_logbase2(MAX2(256, base_align));
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surf->cmask_size = align(slice_bytes, base_align) * num_layers;
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}
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static void si_compute_htile(const struct radeon_info *info,
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struct radeon_surf *surf, unsigned num_layers)
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{
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unsigned cl_width, cl_height, width, height;
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unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
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unsigned num_pipes = info->num_tile_pipes;
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surf->meta_size = 0;
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if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER) ||
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surf->flags & RADEON_SURF_NO_HTILE)
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return;
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/* Overalign HTILE on P2 configs to work around GPU hangs in
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* piglit/depthstencil-render-miplevels 585.
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*
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* This has been confirmed to help Kabini & Stoney, where the hangs
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* are always reproducible. I think I have seen the test hang
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* on Carrizo too, though it was very rare there.
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*/
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if (info->gfx_level >= GFX7 && num_pipes < 4)
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num_pipes = 4;
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switch (num_pipes) {
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case 1:
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cl_width = 32;
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cl_height = 16;
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break;
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case 2:
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cl_width = 32;
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cl_height = 32;
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break;
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case 4:
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cl_width = 64;
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cl_height = 32;
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break;
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case 8:
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cl_width = 64;
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cl_height = 64;
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break;
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case 16:
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cl_width = 128;
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cl_height = 64;
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break;
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default:
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assert(0);
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return;
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}
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width = align(surf->u.legacy.level[0].nblk_x, cl_width * 8);
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height = align(surf->u.legacy.level[0].nblk_y, cl_height * 8);
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slice_elements = (width * height) / (8 * 8);
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slice_bytes = slice_elements * 4;
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pipe_interleave_bytes = info->pipe_interleave_bytes;
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base_align = num_pipes * pipe_interleave_bytes;
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surf->meta_alignment_log2 = util_logbase2(base_align);
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surf->meta_size = num_layers * align(slice_bytes, base_align);
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}
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static int radeon_winsys_surface_init(struct radeon_winsys *rws,
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const struct pipe_resource *tex,
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uint64_t flags, unsigned bpe,
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enum radeon_surf_mode mode,
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struct radeon_surf *surf_ws)
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{
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struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
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struct radeon_surface surf_drm;
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int r;
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surf_winsys_to_drm(&surf_drm, tex, flags, bpe, mode, surf_ws);
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if (!(flags & (RADEON_SURF_IMPORTED | RADEON_SURF_FMASK))) {
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r = radeon_surface_best(ws->surf_man, &surf_drm);
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if (r)
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return r;
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}
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r = radeon_surface_init(ws->surf_man, &surf_drm);
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if (r)
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return r;
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surf_drm_to_winsys(ws, surf_ws, &surf_drm);
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/* Compute FMASK. */
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if (ws->gen == DRV_SI &&
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tex->nr_samples >= 2 &&
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!(flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_FMASK | RADEON_SURF_NO_FMASK))) {
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/* FMASK is allocated like an ordinary texture. */
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struct pipe_resource templ = *tex;
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struct radeon_surf fmask = {};
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unsigned fmask_flags, bpe;
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templ.nr_samples = 1;
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fmask_flags = flags | RADEON_SURF_FMASK;
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switch (tex->nr_samples) {
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case 2:
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case 4:
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bpe = 1;
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break;
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case 8:
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bpe = 4;
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break;
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default:
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fprintf(stderr, "radeon: Invalid sample count for FMASK allocation.\n");
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return -1;
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}
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if (radeon_winsys_surface_init(rws, &templ, fmask_flags, bpe,
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RADEON_SURF_MODE_2D, &fmask)) {
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fprintf(stderr, "Got error in surface_init while allocating FMASK.\n");
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return -1;
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}
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assert(fmask.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
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surf_ws->fmask_size = fmask.surf_size;
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surf_ws->fmask_alignment_log2 = util_logbase2(MAX2(256, 1 << fmask.surf_alignment_log2));
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surf_ws->fmask_tile_swizzle = fmask.tile_swizzle;
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surf_ws->u.legacy.color.fmask.slice_tile_max =
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(fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64;
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if (surf_ws->u.legacy.color.fmask.slice_tile_max)
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surf_ws->u.legacy.color.fmask.slice_tile_max -= 1;
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surf_ws->u.legacy.color.fmask.tiling_index = fmask.u.legacy.tiling_index[0];
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surf_ws->u.legacy.color.fmask.bankh = fmask.u.legacy.bankh;
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surf_ws->u.legacy.color.fmask.pitch_in_pixels = fmask.u.legacy.level[0].nblk_x;
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}
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if (ws->gen == DRV_SI &&
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(tex->nr_samples <= 1 || surf_ws->fmask_size)) {
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struct ac_surf_config config;
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/* Only these fields need to be set for the CMASK computation. */
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config.info.width = tex->width0;
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config.info.height = tex->height0;
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config.info.depth = tex->depth0;
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config.info.array_size = tex->array_size;
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config.is_3d = !!(tex->target == PIPE_TEXTURE_3D);
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config.is_cube = !!(tex->target == PIPE_TEXTURE_CUBE);
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si_compute_cmask(&ws->info, &config, surf_ws);
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}
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if (ws->gen == DRV_SI) {
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si_compute_htile(&ws->info, surf_ws, util_num_layers(tex, 0));
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/* Determine the memory layout of multiple allocations in one buffer. */
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surf_ws->total_size = surf_ws->surf_size;
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if (surf_ws->meta_size) {
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surf_ws->meta_offset = align64(surf_ws->total_size, 1 << surf_ws->meta_alignment_log2);
|
|
surf_ws->total_size = surf_ws->meta_offset + surf_ws->meta_size;
|
|
}
|
|
|
|
if (surf_ws->fmask_size) {
|
|
assert(tex->nr_samples >= 2);
|
|
surf_ws->fmask_offset = align64(surf_ws->total_size, 1 << surf_ws->fmask_alignment_log2);
|
|
surf_ws->total_size = surf_ws->fmask_offset + surf_ws->fmask_size;
|
|
}
|
|
|
|
/* Single-sample CMASK is in a separate buffer. */
|
|
if (surf_ws->cmask_size && tex->nr_samples >= 2) {
|
|
surf_ws->cmask_offset = align64(surf_ws->total_size, 1 << surf_ws->cmask_alignment_log2);
|
|
surf_ws->total_size = surf_ws->cmask_offset + surf_ws->cmask_size;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
void radeon_surface_init_functions(struct radeon_drm_winsys *ws)
|
|
{
|
|
ws->base.surface_init = radeon_winsys_surface_init;
|
|
}
|