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mesa/src/gallium/drivers/r600/r600_asm.c

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r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
/*
* Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* on the rights to use, copy, modify, merge, publish, distribute, sub
* license, and/or sell copies of the Software, and to permit persons to whom
* the Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
r600g: delete old path Lot of clean can now happen. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-29 19:26:29 +01:00
#include <stdio.h>
#include <errno.h>
r600g: build fetch shader from vertex elements Vertex elements change are less frequent than draw call, those to avoid rebuilding fetch shader to often build the fetch shader along vertex elements. This also allow to move vertex buffer setup out of draw path and make update to it less frequent. Shader update can still be improved to only update SPI regs (based on some rasterizer state like flat shading or point sprite ...). Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-12-04 01:47:02 +00:00
#include "util/u_format.h"
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
#include "util/u_memory.h"
r600g: add fetch shader capabilities Use fetch shader instead of having fetch instruction in the vertex shader. Allow to restrict shader update to a smaller part when vertex buffer input layout changes. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-11-18 19:29:16 +00:00
#include "pipe/p_shader_tokens.h"
r600g: delete old path Lot of clean can now happen. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-29 19:26:29 +01:00
#include "r600_pipe.h"
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
#include "r600_sq.h"
r600g: split opcodes out and add wrapper around usage. This splits the r600 opcodes out of the sq file and adds a wrapper so we can convert to evergreen opcodes later without touching these functions too much.
2010-09-07 23:49:00 +01:00
#include "r600_opcodes.h"
r600g: misc cleanup Avoid using r600_screen structure to get ptr to radeon winsys structure. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-15 16:47:32 +01:00
#include "r600_asm.h"
r600g: build fetch shader from vertex elements Vertex elements change are less frequent than draw call, those to avoid rebuilding fetch shader to often build the fetch shader along vertex elements. This also allow to move vertex buffer setup out of draw path and make update to it less frequent. Shader update can still be improved to only update SPI regs (based on some rasterizer state like flat shading or point sprite ...). Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-12-04 01:47:02 +00:00
#include "r600_formats.h"
#include "r600d.h"
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
r600g: rework bank swizzle code
2010-12-18 16:56:36 +00:00
#define NUM_OF_CYCLES 3
#define NUM_OF_COMPONENTS 4
r600g: pass r600_bc to some addition compiler helper functions needed for asic specific opcodes Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:50:29 +00:00
static inline unsigned int r600_bc_get_num_operands(struct r600_bc *bc, struct r600_bc_alu *alu)
r600g: add initial bank swizzle support. this is ported from r600c mostly, bank swizzling is real messy and I don't think I got enough sleep last night to fully understand it.
2010-09-08 05:09:40 +01:00
{
if(alu->is_op3)
return 3;
r600g: compiler helper opcode fixes for evergreen Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:47:29 +00:00
switch (bc->chiprev) {
case CHIPREV_R600:
case CHIPREV_R700:
switch (alu->inst) {
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
return 0;
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
return 2;
r600g: code cleanup (indent, trailing space, empty line ...) Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-11-17 22:20:59 +00:00
r600g: compiler helper opcode fixes for evergreen Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:47:29 +00:00
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
return 1;
default: R600_ERR(
"Need instruction operand number for 0x%x.\n", alu->inst);
}
break;
case CHIPREV_EVERGREEN:
switch (alu->inst) {
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
return 0;
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW:
return 2;
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
return 1;
default: R600_ERR(
"Need instruction operand number for 0x%x.\n", alu->inst);
}
break;
}
r600g: code cleanup (indent, trailing space, empty line ...) Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-11-17 22:20:59 +00:00
r600g: add initial bank swizzle support. this is ported from r600c mostly, bank swizzling is real messy and I don't think I got enough sleep last night to fully understand it.
2010-09-08 05:09:40 +01:00
return 3;
}
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
int r700_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id);
static struct r600_bc_cf *r600_bc_cf(void)
{
struct r600_bc_cf *cf = CALLOC_STRUCT(r600_bc_cf);
if (cf == NULL)
return NULL;
LIST_INITHEAD(&cf->list);
LIST_INITHEAD(&cf->alu);
LIST_INITHEAD(&cf->vtx);
r600g: first pass at texture support This add texture support to the assembler, generated code is wrong (tested against working dump). Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-24 01:55:48 +01:00
LIST_INITHEAD(&cf->tex);
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
return cf;
}
static struct r600_bc_alu *r600_bc_alu(void)
{
struct r600_bc_alu *alu = CALLOC_STRUCT(r600_bc_alu);
if (alu == NULL)
return NULL;
LIST_INITHEAD(&alu->list);
return alu;
}
static struct r600_bc_vtx *r600_bc_vtx(void)
{
struct r600_bc_vtx *vtx = CALLOC_STRUCT(r600_bc_vtx);
if (vtx == NULL)
return NULL;
LIST_INITHEAD(&vtx->list);
return vtx;
}
r600g: first pass at texture support This add texture support to the assembler, generated code is wrong (tested against working dump). Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-24 01:55:48 +01:00
static struct r600_bc_tex *r600_bc_tex(void)
{
struct r600_bc_tex *tex = CALLOC_STRUCT(r600_bc_tex);
if (tex == NULL)
return NULL;
LIST_INITHEAD(&tex->list);
return tex;
}
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
int r600_bc_init(struct r600_bc *bc, enum radeon_family family)
{
LIST_INITHEAD(&bc->cf);
bc->family = family;
r600g: add a chiprev type for r600/r700/evergreen instead of using family
2010-08-19 05:43:11 +01:00
switch (bc->family) {
case CHIP_R600:
case CHIP_RV610:
case CHIP_RV630:
case CHIP_RV670:
case CHIP_RV620:
case CHIP_RV635:
case CHIP_RS780:
case CHIP_RS880:
r600g: use meaningful defines for chiprev Makes the code much clearer.
2010-11-19 20:32:02 +00:00
bc->chiprev = CHIPREV_R600;
r600g: add a chiprev type for r600/r700/evergreen instead of using family
2010-08-19 05:43:11 +01:00
break;
case CHIP_RV770:
case CHIP_RV730:
case CHIP_RV710:
case CHIP_RV740:
r600g: use meaningful defines for chiprev Makes the code much clearer.
2010-11-19 20:32:02 +00:00
bc->chiprev = CHIPREV_R700;
r600g: add a chiprev type for r600/r700/evergreen instead of using family
2010-08-19 05:43:11 +01:00
break;
r600g: add initial evergreen support adds shader opcodes + assembler support (except ARL) uses constant buffers add interp instructions in fragment shader adds all evergreen hw states adds evergreen pm4 support. this runs gears for me on my evergreen
2010-09-03 05:38:41 +01:00
case CHIP_CEDAR:
case CHIP_REDWOOD:
case CHIP_JUNIPER:
case CHIP_CYPRESS:
case CHIP_HEMLOCK:
r600g: add support for ontario APUs Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2010-11-22 22:47:24 +00:00
case CHIP_PALM:
r600g: add support for NI (Northern Islands) GPUs This adds support for Barts, Turks, and Caicos asics.
2011-01-06 23:05:16 +00:00
case CHIP_BARTS:
case CHIP_TURKS:
case CHIP_CAICOS:
r600g: use meaningful defines for chiprev Makes the code much clearer.
2010-11-19 20:32:02 +00:00
bc->chiprev = CHIPREV_EVERGREEN;
r600g: add initial evergreen support adds shader opcodes + assembler support (except ARL) uses constant buffers add interp instructions in fragment shader adds all evergreen hw states adds evergreen pm4 support. this runs gears for me on my evergreen
2010-09-03 05:38:41 +01:00
break;
r600g: add a chiprev type for r600/r700/evergreen instead of using family
2010-08-19 05:43:11 +01:00
default:
R600_ERR("unknown family %d\n", bc->family);
return -EINVAL;
}
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
return 0;
}
static int r600_bc_add_cf(struct r600_bc *bc)
{
struct r600_bc_cf *cf = r600_bc_cf();
if (cf == NULL)
return -ENOMEM;
LIST_ADDTAIL(&cf->list, &bc->cf);
if (bc->cf_last)
cf->id = bc->cf_last->id + 2;
bc->cf_last = cf;
bc->ncf++;
bc->ndw += 2;
r600g: fix LIT + fix multiple constant one ALU + fix ALU block splitting Make sure LIT fills all slot for instruction (can't do W instruction without having the Z slot filled with at least a NOP). ALU instruction can't access more than 4 constant, move constant to temporary reg if we reach the limit. Fix ALU block splitting, only split ALU after ALU with last instruction bit sets. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-08-03 19:14:58 +01:00
bc->force_add_cf = 0;
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
return 0;
}
int r600_bc_add_output(struct r600_bc *bc, const struct r600_bc_output *output)
{
int r;
r = r600_bc_add_cf(bc);
if (r)
return r;
bc->cf_last->inst = output->inst;
memcpy(&bc->cf_last->output, output, sizeof(struct r600_bc_output));
return 0;
}
r600g: fix alu slot assignment
2010-12-18 12:57:18 +00:00
/* alu instructions that can ony exits once per group */
r600g: pass r600_bc to some addition compiler helper functions needed for asic specific opcodes Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:50:29 +00:00
static int is_alu_once_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
r600g: fix alu slot assignment
2010-12-18 12:57:18 +00:00
{
r600g: compiler helper opcode fixes for evergreen Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:47:29 +00:00
switch (bc->chiprev) {
case CHIPREV_R600:
case CHIPREV_R700:
return !alu->is_op3 && (
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
case CHIPREV_EVERGREEN:
default:
return !alu->is_op3 && (
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
}
r600g: fix alu slot assignment
2010-12-18 12:57:18 +00:00
}
r600g: pass r600_bc to some addition compiler helper functions needed for asic specific opcodes Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:50:29 +00:00
static int is_alu_reduction_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
r600g: fix alu slot assignment
2010-12-18 12:57:18 +00:00
{
r600g: compiler helper opcode fixes for evergreen Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:47:29 +00:00
switch (bc->chiprev) {
case CHIPREV_R600:
case CHIPREV_R700:
return !alu->is_op3 && (
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
case CHIPREV_EVERGREEN:
default:
return !alu->is_op3 && (
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
}
r600g: fix alu slot assignment
2010-12-18 12:57:18 +00:00
}
r600g: pass r600_bc to some addition compiler helper functions needed for asic specific opcodes Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:50:29 +00:00
static int is_alu_mova_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
r600g: fix alu slot assignment
2010-12-18 12:57:18 +00:00
{
r600g: compiler helper opcode fixes for evergreen Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:47:29 +00:00
switch (bc->chiprev) {
case CHIPREV_R600:
case CHIPREV_R700:
return !alu->is_op3 && (
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
case CHIPREV_EVERGREEN:
default:
return !alu->is_op3 && (
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
}
r600g: fix alu slot assignment
2010-12-18 12:57:18 +00:00
}
/* alu instructions that can only execute on the vector unit */
r600g: pass r600_bc to some addition compiler helper functions needed for asic specific opcodes Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:50:29 +00:00
static int is_alu_vec_unit_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
r600g: fix alu slot assignment
2010-12-18 12:57:18 +00:00
{
r600g: pass r600_bc to some addition compiler helper functions needed for asic specific opcodes Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:50:29 +00:00
return is_alu_reduction_inst(bc, alu) ||
is_alu_mova_inst(bc, alu);
r600g: fix alu slot assignment
2010-12-18 12:57:18 +00:00
}
/* alu instructions that can only execute on the trans unit */
r600g: pass r600_bc to some addition compiler helper functions needed for asic specific opcodes Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:50:29 +00:00
static int is_alu_trans_unit_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
r600g: fix alu slot assignment
2010-12-18 12:57:18 +00:00
{
r600g: compiler helper opcode fixes for evergreen Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:47:29 +00:00
switch (bc->chiprev) {
case CHIPREV_R600:
case CHIPREV_R700:
if (!alu->is_op3)
return alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_FF ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_FF ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SQRT_IEEE;
else
return alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT ||
alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_D2 ||
alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M2 ||
alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M4;
case CHIPREV_EVERGREEN:
default:
if (!alu->is_op3)
return alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_FF ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_FF ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN ||
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SQRT_IEEE;
else
return alu->inst == EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
}
r600g: fix alu slot assignment
2010-12-18 12:57:18 +00:00
}
/* alu instructions that can execute on any unit */
r600g: pass r600_bc to some addition compiler helper functions needed for asic specific opcodes Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:50:29 +00:00
static int is_alu_any_unit_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
r600g: fix alu slot assignment
2010-12-18 12:57:18 +00:00
{
r600g: pass r600_bc to some addition compiler helper functions needed for asic specific opcodes Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:50:29 +00:00
return !is_alu_vec_unit_inst(bc, alu) &&
!is_alu_trans_unit_inst(bc, alu);
r600g: fix alu slot assignment
2010-12-18 12:57:18 +00:00
}
r600g: pass r600_bc to some addition compiler helper functions needed for asic specific opcodes Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:50:29 +00:00
static int assign_alu_units(struct r600_bc *bc, struct r600_bc_alu *alu_first,
struct r600_bc_alu *assignment[5])
r600g: fix alu slot assignment
2010-12-18 12:57:18 +00:00
{
struct r600_bc_alu *alu;
unsigned i, chan, trans;
for (i = 0; i < 5; i++)
assignment[i] = NULL;
r600g: merge alu groups
2010-12-20 21:09:09 +00:00
for (alu = alu_first; alu; alu = LIST_ENTRY(struct r600_bc_alu, alu->list.next, list)) {
r600g: fix alu slot assignment
2010-12-18 12:57:18 +00:00
chan = alu->dst.chan;
r600g: pass r600_bc to some addition compiler helper functions needed for asic specific opcodes Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:50:29 +00:00
if (is_alu_trans_unit_inst(bc, alu))
r600g: fix alu slot assignment
2010-12-18 12:57:18 +00:00
trans = 1;
r600g: pass r600_bc to some addition compiler helper functions needed for asic specific opcodes Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:50:29 +00:00
else if (is_alu_vec_unit_inst(bc, alu))
r600g: fix alu slot assignment
2010-12-18 12:57:18 +00:00
trans = 0;
else if (assignment[chan])
trans = 1; // assume ALU_INST_PREFER_VECTOR
else
trans = 0;
if (trans) {
if (assignment[4]) {
assert(0); //ALU.Trans has already been allocated
return -1;
}
assignment[4] = alu;
} else {
if (assignment[chan]) {
assert(0); //ALU.chan has already been allocated
return -1;
}
assignment[chan] = alu;
}
if (alu->last)
break;
}
return 0;
}
r600g: rework bank swizzle code
2010-12-18 16:56:36 +00:00
struct alu_bank_swizzle {
int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS];
int hw_cfile_addr[4];
int hw_cfile_elem[4];
};
const unsigned cycle_for_bank_swizzle_vec[][3] = {
[SQ_ALU_VEC_012] = { 0, 1, 2 },
[SQ_ALU_VEC_021] = { 0, 2, 1 },
[SQ_ALU_VEC_120] = { 1, 2, 0 },
[SQ_ALU_VEC_102] = { 1, 0, 2 },
[SQ_ALU_VEC_201] = { 2, 0, 1 },
[SQ_ALU_VEC_210] = { 2, 1, 0 }
};
const unsigned cycle_for_bank_swizzle_scl[][3] = {
[SQ_ALU_SCL_210] = { 2, 1, 0 },
[SQ_ALU_SCL_122] = { 1, 2, 2 },
[SQ_ALU_SCL_212] = { 2, 1, 2 },
[SQ_ALU_SCL_221] = { 2, 2, 1 }
};
static void init_bank_swizzle(struct alu_bank_swizzle *bs)
r600g: add initial bank swizzle support. this is ported from r600c mostly, bank swizzling is real messy and I don't think I got enough sleep last night to fully understand it.
2010-09-08 05:09:40 +01:00
{
r600g: rework bank swizzle code
2010-12-18 16:56:36 +00:00
int i, cycle, component;
r600g: add initial bank swizzle support. this is ported from r600c mostly, bank swizzling is real messy and I don't think I got enough sleep last night to fully understand it.
2010-09-08 05:09:40 +01:00
/* set up gpr use */
for (cycle = 0; cycle < NUM_OF_CYCLES; cycle++)
for (component = 0; component < NUM_OF_COMPONENTS; component++)
r600g: rework bank swizzle code
2010-12-18 16:56:36 +00:00
bs->hw_gpr[cycle][component] = -1;
for (i = 0; i < 4; i++)
bs->hw_cfile_addr[i] = -1;
for (i = 0; i < 4; i++)
bs->hw_cfile_elem[i] = -1;
r600g: add initial bank swizzle support. this is ported from r600c mostly, bank swizzling is real messy and I don't think I got enough sleep last night to fully understand it.
2010-09-08 05:09:40 +01:00
}
r600g: rework bank swizzle code
2010-12-18 16:56:36 +00:00
static int reserve_gpr(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan, unsigned cycle)
r600g: add initial bank swizzle support. this is ported from r600c mostly, bank swizzling is real messy and I don't think I got enough sleep last night to fully understand it.
2010-09-08 05:09:40 +01:00
{
r600g: rework bank swizzle code
2010-12-18 16:56:36 +00:00
if (bs->hw_gpr[cycle][chan] == -1)
bs->hw_gpr[cycle][chan] = sel;
else if (bs->hw_gpr[cycle][chan] != (int)sel) {
// Another scalar operation has already used GPR read port for channel
r600g: add initial bank swizzle support. this is ported from r600c mostly, bank swizzling is real messy and I don't think I got enough sleep last night to fully understand it.
2010-09-08 05:09:40 +01:00
return -1;
}
return 0;
}
r600g: rework bank swizzle code
2010-12-18 16:56:36 +00:00
static int reserve_cfile(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan)
r600g: add initial bank swizzle support. this is ported from r600c mostly, bank swizzling is real messy and I don't think I got enough sleep last night to fully understand it.
2010-09-08 05:09:40 +01:00
{
r600g: rework bank swizzle code
2010-12-18 16:56:36 +00:00
int res, resmatch = -1, resempty = -1;
for (res = 3; res >= 0; --res) {
if (bs->hw_cfile_addr[res] == -1)
resempty = res;
else if (bs->hw_cfile_addr[res] == sel &&
bs->hw_cfile_elem[res] == chan)
resmatch = res;
r600g: add initial bank swizzle support. this is ported from r600c mostly, bank swizzling is real messy and I don't think I got enough sleep last night to fully understand it.
2010-09-08 05:09:40 +01:00
}
r600g: rework bank swizzle code
2010-12-18 16:56:36 +00:00
if (resmatch != -1)
return 0; // Read for this scalar element already reserved, nothing to do here.
else if (resempty != -1) {
bs->hw_cfile_addr[resempty] = sel;
bs->hw_cfile_elem[resempty] = chan;
} else {
// All cfile read ports are used, cannot reference vector element
return -1;
r600g: add initial bank swizzle support. this is ported from r600c mostly, bank swizzling is real messy and I don't think I got enough sleep last night to fully understand it.
2010-09-08 05:09:40 +01:00
}
r600g: rework bank swizzle code
2010-12-18 16:56:36 +00:00
return 0;
r600g: add initial bank swizzle support. this is ported from r600c mostly, bank swizzling is real messy and I don't think I got enough sleep last night to fully understand it.
2010-09-08 05:09:40 +01:00
}
r600g: rework bank swizzle code
2010-12-18 16:56:36 +00:00
static int is_gpr(unsigned sel)
r600g: add initial bank swizzle support. this is ported from r600c mostly, bank swizzling is real messy and I don't think I got enough sleep last night to fully understand it.
2010-09-08 05:09:40 +01:00
{
r600g: rework bank swizzle code
2010-12-18 16:56:36 +00:00
return (sel >= 0 && sel <= 127);
r600g: add initial bank swizzle support. this is ported from r600c mostly, bank swizzling is real messy and I don't think I got enough sleep last night to fully understand it.
2010-09-08 05:09:40 +01:00
}
r600g: Split ALU clauses based on used constant cache lines.
2011-01-07 16:06:11 +00:00
/* CB constants start at 512, and get translated to a kcache index when ALU
* clauses are constructed. Note that we handle kcache constants the same way
* as (the now gone) cfile constants, is that really required? */
r600g: rework bank swizzle code
2010-12-18 16:56:36 +00:00
static int is_cfile(unsigned sel)
{
return (sel > 255 && sel < 512) ||
(sel > 511 && sel < 4607) || // Kcache before translate
(sel > 127 && sel < 192); // Kcache after translate
}
r600g: fix warning in r600 pipe driver
2010-09-10 05:07:49 +01:00
static int is_const(int sel)
{
r600g: rework bank swizzle code
2010-12-18 16:56:36 +00:00
return is_cfile(sel) ||
(sel >= V_SQ_ALU_SRC_0 &&
sel <= V_SQ_ALU_SRC_LITERAL);
r600g: fix warning in r600 pipe driver
2010-09-10 05:07:49 +01:00
}
r600g: rework bank swizzle code
2010-12-18 16:56:36 +00:00
r600g: pass r600_bc to some addition compiler helper functions needed for asic specific opcodes Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:50:29 +00:00
static int check_vector(struct r600_bc *bc, struct r600_bc_alu *alu,
struct alu_bank_swizzle *bs, int bank_swizzle)
r600g: add initial bank swizzle support. this is ported from r600c mostly, bank swizzling is real messy and I don't think I got enough sleep last night to fully understand it.
2010-09-08 05:09:40 +01:00
{
r600g: rework bank swizzle code
2010-12-18 16:56:36 +00:00
int r, src, num_src, sel, elem, cycle;
r600g: pass r600_bc to some addition compiler helper functions needed for asic specific opcodes Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:50:29 +00:00
num_src = r600_bc_get_num_operands(bc, alu);
r600g: rework bank swizzle code
2010-12-18 16:56:36 +00:00
for (src = 0; src < num_src; src++) {
sel = alu->src[src].sel;
elem = alu->src[src].chan;
if (is_gpr(sel)) {
cycle = cycle_for_bank_swizzle_vec[bank_swizzle][src];
if (src == 1 && sel == alu->src[0].sel && elem == alu->src[0].chan)
// Nothing to do; special-case optimization,
// second source uses first source’s reservation
continue;
else {
r = reserve_gpr(bs, sel, elem, cycle);
if (r)
return r;
}
} else if (is_cfile(sel)) {
r = reserve_cfile(bs, sel, elem);
if (r)
return r;
}
// No restrictions on PV, PS, literal or special constants
r600g: add initial evergreen support adds shader opcodes + assembler support (except ARL) uses constant buffers add interp instructions in fragment shader adds all evergreen hw states adds evergreen pm4 support. this runs gears for me on my evergreen
2010-09-03 05:38:41 +01:00
}
r600g: add initial bank swizzle support. this is ported from r600c mostly, bank swizzling is real messy and I don't think I got enough sleep last night to fully understand it.
2010-09-08 05:09:40 +01:00
return 0;
}
r600g: rework bank swizzle code
2010-12-18 16:56:36 +00:00
r600g: pass r600_bc to some addition compiler helper functions needed for asic specific opcodes Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:50:29 +00:00
static int check_scalar(struct r600_bc *bc, struct r600_bc_alu *alu,
struct alu_bank_swizzle *bs, int bank_swizzle)
r600g: add initial bank swizzle support. this is ported from r600c mostly, bank swizzling is real messy and I don't think I got enough sleep last night to fully understand it.
2010-09-08 05:09:40 +01:00
{
r600g: rework bank swizzle code
2010-12-18 16:56:36 +00:00
int r, src, num_src, const_count, sel, elem, cycle;
r600g: pass r600_bc to some addition compiler helper functions needed for asic specific opcodes Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:50:29 +00:00
num_src = r600_bc_get_num_operands(bc, alu);
r600g: rework bank swizzle code
2010-12-18 16:56:36 +00:00
for (const_count = 0, src = 0; src < num_src; ++src) {
sel = alu->src[src].sel;
elem = alu->src[src].chan;
if (is_const(sel)) { // Any constant, including literal and inline constants
if (const_count >= 2)
// More than two references to a constant in
// transcendental operation.
return -1;
else
const_count++;
}
if (is_cfile(sel)) {
r = reserve_cfile(bs, sel, elem);
if (r)
return r;
}
}
for (src = 0; src < num_src; ++src) {
sel = alu->src[src].sel;
elem = alu->src[src].chan;
if (is_gpr(sel)) {
cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
if (cycle < const_count)
// Cycle for GPR load conflicts with
// constant load in transcendental operation.
return -1;
r = reserve_gpr(bs, sel, elem, cycle);
if (r)
return r;
}
// Constants already processed
// No restrictions on PV, PS
r600g: add initial evergreen support adds shader opcodes + assembler support (except ARL) uses constant buffers add interp instructions in fragment shader adds all evergreen hw states adds evergreen pm4 support. this runs gears for me on my evergreen
2010-09-03 05:38:41 +01:00
}
r600g: add initial bank swizzle support. this is ported from r600c mostly, bank swizzling is real messy and I don't think I got enough sleep last night to fully understand it.
2010-09-08 05:09:40 +01:00
return 0;
}
r600g: merge alu groups
2010-12-20 21:09:09 +00:00
r600g: pass r600_bc to some addition compiler helper functions needed for asic specific opcodes Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:50:29 +00:00
static int check_and_set_bank_swizzle(struct r600_bc *bc,
struct r600_bc_alu *slots[5])
r600g: add initial bank swizzle support. this is ported from r600c mostly, bank swizzling is real messy and I don't think I got enough sleep last night to fully understand it.
2010-09-08 05:09:40 +01:00
{
r600g: rework bank swizzle code
2010-12-18 16:56:36 +00:00
struct alu_bank_swizzle bs;
int bank_swizzle[5];
r600g: merge alu groups
2010-12-20 21:09:09 +00:00
int i, r = 0, forced = 0;
r600g: rework bank swizzle code
2010-12-18 16:56:36 +00:00
r600g: merge alu groups
2010-12-20 21:09:09 +00:00
for (i = 0; i < 5; i++)
if (slots[i] && slots[i]->bank_swizzle_force) {
slots[i]->bank_swizzle = slots[i]->bank_swizzle_force;
forced = 1;
}
if (forced)
r600g: rework bank swizzle code
2010-12-18 16:56:36 +00:00
return 0;
r600g: add initial bank swizzle support. this is ported from r600c mostly, bank swizzling is real messy and I don't think I got enough sleep last night to fully understand it.
2010-09-08 05:09:40 +01:00
r600g: rework bank swizzle code
2010-12-18 16:56:36 +00:00
// just check every possible combination of bank swizzle
// not very efficent, but works on the first try in most of the cases
r600g: fix alu slot assignment
2010-12-18 12:57:18 +00:00
for (i = 0; i < 4; i++)
r600g: rework bank swizzle code
2010-12-18 16:56:36 +00:00
bank_swizzle[i] = SQ_ALU_VEC_012;
bank_swizzle[4] = SQ_ALU_SCL_210;
while(bank_swizzle[4] <= SQ_ALU_SCL_221) {
init_bank_swizzle(&bs);
for (i = 0; i < 4; i++) {
r600g: merge alu groups
2010-12-20 21:09:09 +00:00
if (slots[i]) {
r600g: pass r600_bc to some addition compiler helper functions needed for asic specific opcodes Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:50:29 +00:00
r = check_vector(bc, slots[i], &bs, bank_swizzle[i]);
r600g: rework bank swizzle code
2010-12-18 16:56:36 +00:00
if (r)
break;
}
}
r600g: merge alu groups
2010-12-20 21:09:09 +00:00
if (!r && slots[4]) {
r600g: pass r600_bc to some addition compiler helper functions needed for asic specific opcodes Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:50:29 +00:00
r = check_scalar(bc, slots[4], &bs, bank_swizzle[4]);
r600g: rework bank swizzle code
2010-12-18 16:56:36 +00:00
}
if (!r) {
for (i = 0; i < 5; i++) {
r600g: merge alu groups
2010-12-20 21:09:09 +00:00
if (slots[i])
slots[i]->bank_swizzle = bank_swizzle[i];
r600g: rework bank swizzle code
2010-12-18 16:56:36 +00:00
}
return 0;
r600g: add initial bank swizzle support. this is ported from r600c mostly, bank swizzling is real messy and I don't think I got enough sleep last night to fully understand it.
2010-09-08 05:09:40 +01:00
}
r600g: fix alu slot assignment
2010-12-18 12:57:18 +00:00
r600g: rework bank swizzle code
2010-12-18 16:56:36 +00:00
for (i = 0; i < 5; i++) {
bank_swizzle[i]++;
if (bank_swizzle[i] <= SQ_ALU_VEC_210)
break;
else
bank_swizzle[i] = SQ_ALU_VEC_012;
}
r600g: add initial bank swizzle support. this is ported from r600c mostly, bank swizzling is real messy and I don't think I got enough sleep last night to fully understand it.
2010-09-08 05:09:40 +01:00
}
r600g: rework bank swizzle code
2010-12-18 16:56:36 +00:00
// couldn't find a working swizzle
return -1;
r600g: add initial bank swizzle support. this is ported from r600c mostly, bank swizzling is real messy and I don't think I got enough sleep last night to fully understand it.
2010-09-08 05:09:40 +01:00
}
r600g: pass r600_bc to some addition compiler helper functions needed for asic specific opcodes Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:50:29 +00:00
static int replace_gpr_with_pv_ps(struct r600_bc *bc,
struct r600_bc_alu *slots[5], struct r600_bc_alu *alu_prev)
r600g: implement replacing gpr with pv and ps
2010-12-18 20:32:16 +00:00
{
r600g: merge alu groups
2010-12-20 21:09:09 +00:00
struct r600_bc_alu *prev[5];
r600g: implement replacing gpr with pv and ps
2010-12-18 20:32:16 +00:00
int gpr[5], chan[5];
int i, j, r, src, num_src;
r600g: pass r600_bc to some addition compiler helper functions needed for asic specific opcodes Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:50:29 +00:00
r = assign_alu_units(bc, alu_prev, prev);
r600g: implement replacing gpr with pv and ps
2010-12-18 20:32:16 +00:00
if (r)
return r;
for (i = 0; i < 5; ++i) {
r600g: merge alu groups
2010-12-20 21:09:09 +00:00
if(prev[i] && prev[i]->dst.write && !prev[i]->dst.rel) {
gpr[i] = prev[i]->dst.sel;
r600g: pass r600_bc to some addition compiler helper functions needed for asic specific opcodes Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:50:29 +00:00
if (is_alu_reduction_inst(bc, prev[i]))
r600g: implement replacing gpr with pv and ps
2010-12-18 20:32:16 +00:00
chan[i] = 0;
else
r600g: merge alu groups
2010-12-20 21:09:09 +00:00
chan[i] = prev[i]->dst.chan;
r600g: implement replacing gpr with pv and ps
2010-12-18 20:32:16 +00:00
} else
r600g: pass r600_bc to some addition compiler helper functions needed for asic specific opcodes Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:50:29 +00:00
gpr[i] = -1;
r600g: implement replacing gpr with pv and ps
2010-12-18 20:32:16 +00:00
}
for (i = 0; i < 5; ++i) {
struct r600_bc_alu *alu = slots[i];
if(!alu)
continue;
r600g: pass r600_bc to some addition compiler helper functions needed for asic specific opcodes Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:50:29 +00:00
num_src = r600_bc_get_num_operands(bc, alu);
r600g: implement replacing gpr with pv and ps
2010-12-18 20:32:16 +00:00
for (src = 0; src < num_src; ++src) {
if (!is_gpr(alu->src[src].sel) || alu->src[src].rel)
continue;
if (alu->src[src].sel == gpr[4] &&
alu->src[src].chan == chan[4]) {
alu->src[src].sel = V_SQ_ALU_SRC_PS;
alu->src[src].chan = 0;
continue;
}
for (j = 0; j < 4; ++j) {
if (alu->src[src].sel == gpr[j] &&
alu->src[src].chan == j) {
alu->src[src].sel = V_SQ_ALU_SRC_PV;
alu->src[src].chan = chan[j];
break;
}
}
}
}
return 0;
}
r600g: rework literal handling
2010-12-22 16:45:51 +00:00
void r600_bc_special_constants(u32 value, unsigned *sel, unsigned *neg)
{
switch(value) {
case 0:
*sel = V_SQ_ALU_SRC_0;
break;
case 1:
*sel = V_SQ_ALU_SRC_1_INT;
break;
case -1:
*sel = V_SQ_ALU_SRC_M_1_INT;
break;
case 0x3F800000: // 1.0f
*sel = V_SQ_ALU_SRC_1;
break;
case 0x3F000000: // 0.5f
*sel = V_SQ_ALU_SRC_0_5;
break;
case 0xBF800000: // -1.0f
*sel = V_SQ_ALU_SRC_1;
*neg ^= 1;
break;
case 0xBF000000: // -0.5f
*sel = V_SQ_ALU_SRC_0_5;
*neg ^= 1;
break;
default:
*sel = V_SQ_ALU_SRC_LITERAL;
break;
}
}
/* compute how many literal are needed */
r600g: pass r600_bc to some addition compiler helper functions needed for asic specific opcodes Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:50:29 +00:00
static int r600_bc_alu_nliterals(struct r600_bc *bc, struct r600_bc_alu *alu,
uint32_t literal[4], unsigned *nliteral)
r600g: rework literal handling
2010-12-22 16:45:51 +00:00
{
r600g: pass r600_bc to some addition compiler helper functions needed for asic specific opcodes Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:50:29 +00:00
unsigned num_src = r600_bc_get_num_operands(bc, alu);
r600g: rework literal handling
2010-12-22 16:45:51 +00:00
unsigned i, j;
for (i = 0; i < num_src; ++i) {
if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
uint32_t value = alu->src[i].value[alu->src[i].chan];
unsigned found = 0;
for (j = 0; j < *nliteral; ++j) {
if (literal[j] == value) {
found = 1;
break;
}
}
if (!found) {
if (*nliteral >= 4)
return -EINVAL;
literal[(*nliteral)++] = value;
}
}
}
return 0;
}
r600g: pass r600_bc to some addition compiler helper functions needed for asic specific opcodes Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:50:29 +00:00
static void r600_bc_alu_adjust_literals(struct r600_bc *bc,
struct r600_bc_alu *alu,
uint32_t literal[4], unsigned nliteral)
r600g: rework literal handling
2010-12-22 16:45:51 +00:00
{
r600g: pass r600_bc to some addition compiler helper functions needed for asic specific opcodes Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:50:29 +00:00
unsigned num_src = r600_bc_get_num_operands(bc, alu);
r600g: rework literal handling
2010-12-22 16:45:51 +00:00
unsigned i, j;
for (i = 0; i < num_src; ++i) {
if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
uint32_t value = alu->src[i].value[alu->src[i].chan];
for (j = 0; j < nliteral; ++j) {
if (literal[j] == value) {
alu->src[i].chan = j;
break;
}
}
}
}
}
r600g: pass r600_bc to some addition compiler helper functions needed for asic specific opcodes Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:50:29 +00:00
static int merge_inst_groups(struct r600_bc *bc, struct r600_bc_alu *slots[5],
struct r600_bc_alu *alu_prev)
r600g: merge alu groups
2010-12-20 21:09:09 +00:00
{
struct r600_bc_alu *prev[5];
struct r600_bc_alu *result[5] = { NULL };
r600d: fix some bugs added reworking literal handling If a literal slot isn't used it should be set to 0 instead of an uninitialized value. Also the channels for pre R700 trig functions were incorrect. And most important literals were not counted against ndw, resulting in an invalid force_add_cf detection.
2011-01-16 00:45:06 +00:00
uint32_t literal[4], prev_literal[4];
unsigned nliteral = 0, prev_nliteral = 0;
r600g: rework literal handling
2010-12-22 16:45:51 +00:00
r600g: merge alu groups
2010-12-20 21:09:09 +00:00
int i, j, r, src, num_src;
int num_once_inst = 0;
r600g: fix alu inst group merging for relative adressing
2011-01-16 20:21:41 +00:00
int have_mova = 0, have_rel = 0;
r600g: merge alu groups
2010-12-20 21:09:09 +00:00
r600g: pass r600_bc to some addition compiler helper functions needed for asic specific opcodes Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:50:29 +00:00
r = assign_alu_units(bc, alu_prev, prev);
r600g: merge alu groups
2010-12-20 21:09:09 +00:00
if (r)
return r;
for (i = 0; i < 5; ++i) {
r600g: Move declaration before code in r600_asm.c. Fixes SCons build.
2011-01-13 22:17:01 +00:00
struct r600_bc_alu *alu;
r600g: rework literal handling
2010-12-22 16:45:51 +00:00
/* check number of literals */
r600d: fix some bugs added reworking literal handling If a literal slot isn't used it should be set to 0 instead of an uninitialized value. Also the channels for pre R700 trig functions were incorrect. And most important literals were not counted against ndw, resulting in an invalid force_add_cf detection.
2011-01-16 00:45:06 +00:00
if (prev[i]) {
if (r600_bc_alu_nliterals(bc, prev[i], literal, &nliteral))
return 0;
if (r600_bc_alu_nliterals(bc, prev[i], prev_literal, &prev_nliteral))
return 0;
r600g: fix alu inst group merging for relative adressing
2011-01-16 20:21:41 +00:00
if (is_alu_mova_inst(bc, prev[i])) {
if (have_rel)
return 0;
have_mova = 1;
}
num_once_inst += is_alu_once_inst(bc, prev[i]);
r600d: fix some bugs added reworking literal handling If a literal slot isn't used it should be set to 0 instead of an uninitialized value. Also the channels for pre R700 trig functions were incorrect. And most important literals were not counted against ndw, resulting in an invalid force_add_cf detection.
2011-01-16 00:45:06 +00:00
}
r600g: pass r600_bc to some addition compiler helper functions needed for asic specific opcodes Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:50:29 +00:00
if (slots[i] && r600_bc_alu_nliterals(bc, slots[i], literal, &nliteral))
r600g: merge alu groups
2010-12-20 21:09:09 +00:00
return 0;
// let's check used slots
if (prev[i] && !slots[i]) {
result[i] = prev[i];
continue;
} else if (prev[i] && slots[i]) {
if (result[4] == NULL && prev[4] == NULL && slots[4] == NULL) {
// trans unit is still free try to use it
r600g: pass r600_bc to some addition compiler helper functions needed for asic specific opcodes Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:50:29 +00:00
if (is_alu_any_unit_inst(bc, slots[i])) {
r600g: merge alu groups
2010-12-20 21:09:09 +00:00
result[i] = prev[i];
result[4] = slots[i];
r600g: pass r600_bc to some addition compiler helper functions needed for asic specific opcodes Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:50:29 +00:00
} else if (is_alu_any_unit_inst(bc, prev[i])) {
r600g: merge alu groups
2010-12-20 21:09:09 +00:00
result[i] = slots[i];
result[4] = prev[i];
} else
return 0;
} else
return 0;
} else if(!slots[i]) {
continue;
} else
result[i] = slots[i];
// let's check source gprs
r600g: Move declaration before code in r600_asm.c. Fixes SCons build.
2011-01-13 22:17:01 +00:00
alu = slots[i];
r600g: pass r600_bc to some addition compiler helper functions needed for asic specific opcodes Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:50:29 +00:00
num_once_inst += is_alu_once_inst(bc, alu);
r600g: merge alu groups
2010-12-20 21:09:09 +00:00
r600g: pass r600_bc to some addition compiler helper functions needed for asic specific opcodes Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:50:29 +00:00
num_src = r600_bc_get_num_operands(bc, alu);
r600g: merge alu groups
2010-12-20 21:09:09 +00:00
for (src = 0; src < num_src; ++src) {
r600g: fix alu inst group merging for relative adressing
2011-01-16 20:21:41 +00:00
if (alu->src[src].rel) {
if (have_mova)
return 0;
have_rel = 1;
}
r600g: merge alu groups
2010-12-20 21:09:09 +00:00
// constants doesn't matter
if (!is_gpr(alu->src[src].sel))
continue;
for (j = 0; j < 5; ++j) {
if (!prev[j] || !prev[j]->dst.write)
continue;
// if it's relative then we can't determin which gpr is really used
if (prev[j]->dst.chan == alu->src[src].chan &&
(prev[j]->dst.sel == alu->src[src].sel ||
prev[j]->dst.rel || alu->src[src].rel))
return 0;
}
}
}
/* more than one PRED_ or KILL_ ? */
if (num_once_inst > 1)
return 0;
/* check if the result can still be swizzlet */
r600g: pass r600_bc to some addition compiler helper functions needed for asic specific opcodes Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:50:29 +00:00
r = check_and_set_bank_swizzle(bc, result);
r600g: merge alu groups
2010-12-20 21:09:09 +00:00
if (r)
return 0;
/* looks like everything worked out right, apply the changes */
r600d: fix some bugs added reworking literal handling If a literal slot isn't used it should be set to 0 instead of an uninitialized value. Also the channels for pre R700 trig functions were incorrect. And most important literals were not counted against ndw, resulting in an invalid force_add_cf detection.
2011-01-16 00:45:06 +00:00
/* undo adding previus literals */
bc->cf_last->ndw -= align(prev_nliteral, 2);
r600g: merge alu groups
2010-12-20 21:09:09 +00:00
/* sort instructions */
for (i = 0; i < 5; ++i) {
slots[i] = result[i];
if (result[i]) {
LIST_DEL(&result[i]->list);
result[i]->last = 0;
LIST_ADDTAIL(&result[i]->list, &bc->cf_last->alu);
}
}
/* determine new last instruction */
LIST_ENTRY(struct r600_bc_alu, bc->cf_last->alu.prev, list)->last = 1;
/* determine new first instruction */
for (i = 0; i < 5; ++i) {
if (result[i]) {
bc->cf_last->curr_bs_head = result[i];
break;
}
}
bc->cf_last->prev_bs_head = bc->cf_last->prev2_bs_head;
bc->cf_last->prev2_bs_head = NULL;
return 0;
}
r600g: Split ALU clauses based on used constant cache lines.
2011-01-07 16:06:11 +00:00
/* This code handles kcache lines as single blocks of 32 constants. We could
* probably do slightly better by recognizing that we actually have two
* consecutive lines of 16 constants, but the resulting code would also be
* somewhat more complicated. */
static int r600_bc_alloc_kcache_lines(struct r600_bc *bc, struct r600_bc_alu *alu, int type)
{
struct r600_bc_kcache *kcache = bc->cf_last->kcache;
unsigned int required_lines;
unsigned int free_lines = 0;
unsigned int cache_line[3];
unsigned int count = 0;
unsigned int i, j;
int r;
/* Collect required cache lines. */
for (i = 0; i < 3; ++i) {
bool found = false;
unsigned int line;
if (alu->src[i].sel < 512)
continue;
line = ((alu->src[i].sel - 512) / 32) * 2;
for (j = 0; j < count; ++j) {
if (cache_line[j] == line) {
found = true;
break;
}
}
if (!found)
cache_line[count++] = line;
}
/* This should never actually happen. */
if (count >= 3) return -ENOMEM;
for (i = 0; i < 2; ++i) {
if (kcache[i].mode == V_SQ_CF_KCACHE_NOP) {
++free_lines;
}
}
/* Filter lines pulled in by previous intructions. Note that this is
* only for the required_lines count, we can't remove these from the
* cache_line array since we may have to start a new ALU clause. */
for (i = 0, required_lines = count; i < count; ++i) {
for (j = 0; j < 2; ++j) {
if (kcache[j].mode == V_SQ_CF_KCACHE_LOCK_2 &&
kcache[j].addr == cache_line[i]) {
--required_lines;
break;
}
}
}
/* Start a new ALU clause if needed. */
if (required_lines > free_lines) {
if ((r = r600_bc_add_cf(bc))) {
return r;
}
bc->cf_last->inst = (type << 3);
kcache = bc->cf_last->kcache;
}
/* Setup the kcache lines. */
for (i = 0; i < count; ++i) {
bool found = false;
for (j = 0; j < 2; ++j) {
if (kcache[j].mode == V_SQ_CF_KCACHE_LOCK_2 &&
kcache[j].addr == cache_line[i]) {
found = true;
break;
}
}
if (found) continue;
for (j = 0; j < 2; ++j) {
if (kcache[j].mode == V_SQ_CF_KCACHE_NOP) {
kcache[j].bank = 0;
kcache[j].addr = cache_line[i];
kcache[j].mode = V_SQ_CF_KCACHE_LOCK_2;
break;
}
}
}
/* Alter the src operands to refer to the kcache. */
for (i = 0; i < 3; ++i) {
static const unsigned int base[] = {128, 160, 256, 288};
unsigned int line;
if (alu->src[i].sel < 512)
continue;
alu->src[i].sel -= 512;
line = (alu->src[i].sel / 32) * 2;
for (j = 0; j < 2; ++j) {
if (kcache[j].mode == V_SQ_CF_KCACHE_LOCK_2 &&
kcache[j].addr == line) {
alu->src[i].sel &= 0x1f;
alu->src[i].sel += base[j];
break;
}
}
}
return 0;
}
r600g: add initial if/else/endif support this adds handling for some more CF instructions and conditions also adds parameter for stack size emission These seem to pass on VS with the stack size hack but not on FS, TODO: fix FS + stack size calcs
2010-08-25 06:57:41 +01:00
int r600_bc_add_alu_type(struct r600_bc *bc, const struct r600_bc_alu *alu, int type)
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
{
struct r600_bc_alu *nalu = r600_bc_alu();
struct r600_bc_alu *lalu;
int i, r;
if (nalu == NULL)
return -ENOMEM;
memcpy(nalu, alu, sizeof(struct r600_bc_alu));
r600g: optimize away CF ALU instructions even if type doesn't match
2010-12-17 23:45:59 +00:00
if (bc->cf_last != NULL && bc->cf_last->inst != (type << 3)) {
/* check if we could add it anyway */
if (bc->cf_last->inst == (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3) &&
type == V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE) {
LIST_FOR_EACH_ENTRY(lalu, &bc->cf_last->alu, list) {
if (lalu->predicate) {
bc->force_add_cf = 1;
break;
}
}
} else
bc->force_add_cf = 1;
}
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
/* cf can contains only alu or only vtx or only tex */
r600g: optimize away CF ALU instructions even if type doesn't match
2010-12-17 23:45:59 +00:00
if (bc->cf_last == NULL || bc->force_add_cf) {
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
r = r600_bc_add_cf(bc);
if (r) {
free(nalu);
return r;
}
}
r600g: optimize away CF ALU instructions even if type doesn't match
2010-12-17 23:45:59 +00:00
bc->cf_last->inst = (type << 3);
r600g: Split ALU clauses based on used constant cache lines.
2011-01-07 16:06:11 +00:00
/* Setup the kcache for this ALU instruction. This will start a new
* ALU clause if needed. */
if ((r = r600_bc_alloc_kcache_lines(bc, nalu, type))) {
free(nalu);
return r;
}
r600g: add initial bank swizzle support. this is ported from r600c mostly, bank swizzling is real messy and I don't think I got enough sleep last night to fully understand it.
2010-09-08 05:09:40 +01:00
if (!bc->cf_last->curr_bs_head) {
bc->cf_last->curr_bs_head = nalu;
}
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
/* number of gpr == the last gpr used in any alu */
for (i = 0; i < 3; i++) {
r600g: Consistently use the copy of the alu instruction in r600_bc_add_alu_type().
2011-01-07 16:06:11 +00:00
if (nalu->src[i].sel >= bc->ngpr && nalu->src[i].sel < 128) {
bc->ngpr = nalu->src[i].sel + 1;
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
}
r600g: rework literal handling
2010-12-22 16:45:51 +00:00
if (nalu->src[i].sel == V_SQ_ALU_SRC_LITERAL)
r600_bc_special_constants(
nalu->src[i].value[nalu->src[i].chan],
&nalu->src[i].sel, &nalu->src[i].neg);
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
}
r600g: Consistently use the copy of the alu instruction in r600_bc_add_alu_type().
2011-01-07 16:06:11 +00:00
if (nalu->dst.sel >= bc->ngpr) {
bc->ngpr = nalu->dst.sel + 1;
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
}
LIST_ADDTAIL(&nalu->list, &bc->cf_last->alu);
/* each alu use 2 dwords */
bc->cf_last->ndw += 2;
bc->ndw += 2;
r600g: add support for constants in memory buffers. DX9 constants were in the constant file, and evergreen no longer support cfile. r600/700 can also use constants in memory buffers, so add the code (disabled for now) to enable that as precursor for evergreen.
2010-09-07 23:41:57 +01:00
r600g: add initial bank swizzle support. this is ported from r600c mostly, bank swizzling is real messy and I don't think I got enough sleep last night to fully understand it.
2010-09-08 05:09:40 +01:00
/* process cur ALU instructions for bank swizzle */
r600g: Consistently use the copy of the alu instruction in r600_bc_add_alu_type().
2011-01-07 16:06:11 +00:00
if (nalu->last) {
r600d: fix some bugs added reworking literal handling If a literal slot isn't used it should be set to 0 instead of an uninitialized value. Also the channels for pre R700 trig functions were incorrect. And most important literals were not counted against ndw, resulting in an invalid force_add_cf detection.
2011-01-16 00:45:06 +00:00
uint32_t literal[4];
unsigned nliteral;
r600g: merge alu groups
2010-12-20 21:09:09 +00:00
struct r600_bc_alu *slots[5];
r600g: pass r600_bc to some addition compiler helper functions needed for asic specific opcodes Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:50:29 +00:00
r = assign_alu_units(bc, bc->cf_last->curr_bs_head, slots);
r600g: fix alu slot assignment
2010-12-18 12:57:18 +00:00
if (r)
return r;
r600g: merge alu groups
2010-12-20 21:09:09 +00:00
if (bc->cf_last->prev_bs_head) {
r = merge_inst_groups(bc, slots, bc->cf_last->prev_bs_head);
if (r)
return r;
}
if (bc->cf_last->prev_bs_head) {
r600g: pass r600_bc to some addition compiler helper functions needed for asic specific opcodes Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:50:29 +00:00
r = replace_gpr_with_pv_ps(bc, slots, bc->cf_last->prev_bs_head);
r600g: merge alu groups
2010-12-20 21:09:09 +00:00
if (r)
return r;
}
r600g: pass r600_bc to some addition compiler helper functions needed for asic specific opcodes Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:50:29 +00:00
r = check_and_set_bank_swizzle(bc, slots);
r600g: merge alu groups
2010-12-20 21:09:09 +00:00
if (r)
return r;
r600d: fix some bugs added reworking literal handling If a literal slot isn't used it should be set to 0 instead of an uninitialized value. Also the channels for pre R700 trig functions were incorrect. And most important literals were not counted against ndw, resulting in an invalid force_add_cf detection.
2011-01-16 00:45:06 +00:00
for (i = 0, nliteral = 0; i < 5; i++) {
if (slots[i]) {
r = r600_bc_alu_nliterals(bc, slots[i], literal, &nliteral);
if (r)
return r;
}
}
bc->cf_last->ndw += align(nliteral, 2);
/* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots)
* worst case */
if ((bc->cf_last->ndw >> 1) >= 120) {
bc->force_add_cf = 1;
}
r600g: merge alu groups
2010-12-20 21:09:09 +00:00
bc->cf_last->prev2_bs_head = bc->cf_last->prev_bs_head;
r600g: implement replacing gpr with pv and ps
2010-12-18 20:32:16 +00:00
bc->cf_last->prev_bs_head = bc->cf_last->curr_bs_head;
r600g: add initial bank swizzle support. this is ported from r600c mostly, bank swizzling is real messy and I don't think I got enough sleep last night to fully understand it.
2010-09-08 05:09:40 +01:00
bc->cf_last->curr_bs_head = NULL;
}
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
return 0;
}
r600g: add initial if/else/endif support this adds handling for some more CF instructions and conditions also adds parameter for stack size emission These seem to pass on VS with the stack size hack but not on FS, TODO: fix FS + stack size calcs
2010-08-25 06:57:41 +01:00
int r600_bc_add_alu(struct r600_bc *bc, const struct r600_bc_alu *alu)
{
r600g: add initial evergreen support adds shader opcodes + assembler support (except ARL) uses constant buffers add interp instructions in fragment shader adds all evergreen hw states adds evergreen pm4 support. this runs gears for me on my evergreen
2010-09-03 05:38:41 +01:00
return r600_bc_add_alu_type(bc, alu, BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
r600g: add initial if/else/endif support this adds handling for some more CF instructions and conditions also adds parameter for stack size emission These seem to pass on VS with the stack size hack but not on FS, TODO: fix FS + stack size calcs
2010-08-25 06:57:41 +01:00
}
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
int r600_bc_add_vtx(struct r600_bc *bc, const struct r600_bc_vtx *vtx)
{
struct r600_bc_vtx *nvtx = r600_bc_vtx();
int r;
if (nvtx == NULL)
return -ENOMEM;
memcpy(nvtx, vtx, sizeof(struct r600_bc_vtx));
/* cf can contains only alu or only vtx or only tex */
if (bc->cf_last == NULL ||
(bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX &&
r600g: deal with overflow of VTX/TEX CF clauses. running piglit's texrect-many caused the vtx to overflow.
2010-09-21 02:24:49 +01:00
bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC) ||
bc->force_add_cf) {
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
r = r600_bc_add_cf(bc);
if (r) {
free(nvtx);
return r;
}
bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_VTX;
}
LIST_ADDTAIL(&nvtx->list, &bc->cf_last->vtx);
r600g: first pass at texture support This add texture support to the assembler, generated code is wrong (tested against working dump). Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-24 01:55:48 +01:00
/* each fetch use 4 dwords */
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
bc->cf_last->ndw += 4;
bc->ndw += 4;
r600g: fix tex and vtx joining
2010-12-16 21:23:48 +00:00
if ((bc->cf_last->ndw / 4) > 7)
r600g: deal with overflow of VTX/TEX CF clauses. running piglit's texrect-many caused the vtx to overflow.
2010-09-21 02:24:49 +01:00
bc->force_add_cf = 1;
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
return 0;
}
r600g: first pass at texture support This add texture support to the assembler, generated code is wrong (tested against working dump). Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-24 01:55:48 +01:00
int r600_bc_add_tex(struct r600_bc *bc, const struct r600_bc_tex *tex)
{
struct r600_bc_tex *ntex = r600_bc_tex();
int r;
if (ntex == NULL)
return -ENOMEM;
memcpy(ntex, tex, sizeof(struct r600_bc_tex));
/* cf can contains only alu or only vtx or only tex */
if (bc->cf_last == NULL ||
r600g: deal with overflow of VTX/TEX CF clauses. running piglit's texrect-many caused the vtx to overflow.
2010-09-21 02:24:49 +01:00
bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_TEX ||
bc->force_add_cf) {
r600g: first pass at texture support This add texture support to the assembler, generated code is wrong (tested against working dump). Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-24 01:55:48 +01:00
r = r600_bc_add_cf(bc);
if (r) {
free(ntex);
return r;
}
bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_TEX;
}
r600g: also look at tex inst when for maximum gpu count
2011-01-12 19:39:40 +00:00
if (ntex->src_gpr >= bc->ngpr) {
bc->ngpr = ntex->src_gpr + 1;
}
if (ntex->dst_gpr >= bc->ngpr) {
bc->ngpr = ntex->dst_gpr + 1;
}
r600g: first pass at texture support This add texture support to the assembler, generated code is wrong (tested against working dump). Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-24 01:55:48 +01:00
LIST_ADDTAIL(&ntex->list, &bc->cf_last->tex);
/* each texture fetch use 4 dwords */
bc->cf_last->ndw += 4;
bc->ndw += 4;
r600g: fix tex and vtx joining
2010-12-16 21:23:48 +00:00
if ((bc->cf_last->ndw / 4) > 7)
r600g: deal with overflow of VTX/TEX CF clauses. running piglit's texrect-many caused the vtx to overflow.
2010-09-21 02:24:49 +01:00
bc->force_add_cf = 1;
r600g: first pass at texture support This add texture support to the assembler, generated code is wrong (tested against working dump). Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-24 01:55:48 +01:00
return 0;
}
r600g: add initial if/else/endif support this adds handling for some more CF instructions and conditions also adds parameter for stack size emission These seem to pass on VS with the stack size hack but not on FS, TODO: fix FS + stack size calcs
2010-08-25 06:57:41 +01:00
int r600_bc_add_cfinst(struct r600_bc *bc, int inst)
{
int r;
r = r600_bc_add_cf(bc);
if (r)
return r;
bc->cf_last->cond = V_SQ_CF_COND_ACTIVE;
bc->cf_last->inst = inst;
return 0;
}
r600g: add initial evergreen support adds shader opcodes + assembler support (except ARL) uses constant buffers add interp instructions in fragment shader adds all evergreen hw states adds evergreen pm4 support. this runs gears for me on my evergreen
2010-09-03 05:38:41 +01:00
/* common to all 3 families */
r600g: first pass at texture support This add texture support to the assembler, generated code is wrong (tested against working dump). Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-24 01:55:48 +01:00
static int r600_bc_vtx_build(struct r600_bc *bc, struct r600_bc_vtx *vtx, unsigned id)
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
{
r600g: add fetch shader capabilities Use fetch shader instead of having fetch instruction in the vertex shader. Allow to restrict shader update to a smaller part when vertex buffer input layout changes. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-11-18 19:29:16 +00:00
unsigned fetch_resource_start = 0;
/* check if we are fetch shader */
/* fetch shader can also access vertex resource,
* first fetch shader resource is at 160
*/
if (bc->type == -1) {
switch (bc->chiprev) {
/* r600 */
r600g: use meaningful defines for chiprev Makes the code much clearer.
2010-11-19 20:32:02 +00:00
case CHIPREV_R600:
r600g: add fetch shader capabilities Use fetch shader instead of having fetch instruction in the vertex shader. Allow to restrict shader update to a smaller part when vertex buffer input layout changes. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-11-18 19:29:16 +00:00
/* r700 */
r600g: use meaningful defines for chiprev Makes the code much clearer.
2010-11-19 20:32:02 +00:00
case CHIPREV_R700:
r600g: add fetch shader capabilities Use fetch shader instead of having fetch instruction in the vertex shader. Allow to restrict shader update to a smaller part when vertex buffer input layout changes. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-11-18 19:29:16 +00:00
fetch_resource_start = 160;
break;
/* evergreen */
r600g: use meaningful defines for chiprev Makes the code much clearer.
2010-11-19 20:32:02 +00:00
case CHIPREV_EVERGREEN:
r600g: add fetch shader capabilities Use fetch shader instead of having fetch instruction in the vertex shader. Allow to restrict shader update to a smaller part when vertex buffer input layout changes. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-11-18 19:29:16 +00:00
fetch_resource_start = 0;
break;
default:
fprintf(stderr, "%s:%s:%d unknown chiprev %d\n",
__FILE__, __func__, __LINE__, bc->chiprev);
break;
}
}
bc->bytecode[id++] = S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id + fetch_resource_start) |
S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x) |
S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) |
S_SQ_VTX_WORD1_DST_SEL_Y(vtx->dst_sel_y) |
S_SQ_VTX_WORD1_DST_SEL_Z(vtx->dst_sel_z) |
S_SQ_VTX_WORD1_DST_SEL_W(vtx->dst_sel_w) |
r600g: add assembler support for other vtx fetch fields. this shouldn't change behaviour, just push the choice of what to do out to the shader.
2010-10-01 02:38:40 +01:00
S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx->use_const_fields) |
S_SQ_VTX_WORD1_DATA_FORMAT(vtx->data_format) |
S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx->num_format_all) |
S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx->format_comp_all) |
S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx->srf_mode_all) |
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr);
bc->bytecode[id++] = S_SQ_VTX_WORD2_MEGA_FETCH(1);
bc->bytecode[id++] = 0;
return 0;
}
r600g: add initial evergreen support adds shader opcodes + assembler support (except ARL) uses constant buffers add interp instructions in fragment shader adds all evergreen hw states adds evergreen pm4 support. this runs gears for me on my evergreen
2010-09-03 05:38:41 +01:00
/* common to all 3 families */
r600g: first pass at texture support This add texture support to the assembler, generated code is wrong (tested against working dump). Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-24 01:55:48 +01:00
static int r600_bc_tex_build(struct r600_bc *bc, struct r600_bc_tex *tex, unsigned id)
{
bc->bytecode[id++] = S_SQ_TEX_WORD0_TEX_INST(tex->inst) |
S_SQ_TEX_WORD0_RESOURCE_ID(tex->resource_id) |
S_SQ_TEX_WORD0_SRC_GPR(tex->src_gpr) |
S_SQ_TEX_WORD0_SRC_REL(tex->src_rel);
bc->bytecode[id++] = S_SQ_TEX_WORD1_DST_GPR(tex->dst_gpr) |
S_SQ_TEX_WORD1_DST_REL(tex->dst_rel) |
S_SQ_TEX_WORD1_DST_SEL_X(tex->dst_sel_x) |
S_SQ_TEX_WORD1_DST_SEL_Y(tex->dst_sel_y) |
S_SQ_TEX_WORD1_DST_SEL_Z(tex->dst_sel_z) |
S_SQ_TEX_WORD1_DST_SEL_W(tex->dst_sel_w) |
S_SQ_TEX_WORD1_LOD_BIAS(tex->lod_bias) |
S_SQ_TEX_WORD1_COORD_TYPE_X(tex->coord_type_x) |
S_SQ_TEX_WORD1_COORD_TYPE_Y(tex->coord_type_y) |
S_SQ_TEX_WORD1_COORD_TYPE_Z(tex->coord_type_z) |
S_SQ_TEX_WORD1_COORD_TYPE_W(tex->coord_type_w);
bc->bytecode[id++] = S_SQ_TEX_WORD2_OFFSET_X(tex->offset_x) |
S_SQ_TEX_WORD2_OFFSET_Y(tex->offset_y) |
S_SQ_TEX_WORD2_OFFSET_Z(tex->offset_z) |
S_SQ_TEX_WORD2_SAMPLER_ID(tex->sampler_id) |
S_SQ_TEX_WORD2_SRC_SEL_X(tex->src_sel_x) |
S_SQ_TEX_WORD2_SRC_SEL_Y(tex->src_sel_y) |
S_SQ_TEX_WORD2_SRC_SEL_Z(tex->src_sel_z) |
S_SQ_TEX_WORD2_SRC_SEL_W(tex->src_sel_w);
bc->bytecode[id++] = 0;
return 0;
}
r600g: add initial evergreen support adds shader opcodes + assembler support (except ARL) uses constant buffers add interp instructions in fragment shader adds all evergreen hw states adds evergreen pm4 support. this runs gears for me on my evergreen
2010-09-03 05:38:41 +01:00
/* r600 only, r700/eg bits in r700_asm.c */
r600g: fix some warnings
2010-08-09 13:57:56 +01:00
static int r600_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id)
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
{
/* don't replace gpr by pv or ps for destination register */
r600g: fix SSG and op3 neg writing 8 more piglits, mainly the two SSG tests.
2010-08-30 05:13:01 +01:00
bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
r600g: add initial relative support to assembler passes another ~20 piglits. /me starts to run out low hanging fruit around now.
2010-08-30 06:19:20 +01:00
S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
r600g: fix SSG and op3 neg writing 8 more piglits, mainly the two SSG tests.
2010-08-30 05:13:01 +01:00
S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
r600g: add initial relative support to assembler passes another ~20 piglits. /me starts to run out low hanging fruit around now.
2010-08-30 06:19:20 +01:00
S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
r600g: fix SSG and op3 neg writing 8 more piglits, mainly the two SSG tests.
2010-08-30 05:13:01 +01:00
S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
S_SQ_ALU_WORD0_LAST(alu->last);
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
if (alu->is_op3) {
bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
r600g: add initial relative support to assembler passes another ~20 piglits. /me starts to run out low hanging fruit around now.
2010-08-30 06:19:20 +01:00
S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
r600g: mipmap early support + EX2/ABS instruction + culling Add mipmap support (demos/src/redbook/mipmap is working) Add EX2/ABS shader instruction support. Add face culling support. Misc fixes. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-29 19:51:06 +01:00
S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
r600g: add initial relative support to assembler passes another ~20 piglits. /me starts to run out low hanging fruit around now.
2010-08-30 06:19:20 +01:00
S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
S_SQ_ALU_WORD1_OP3_ALU_INST(alu->inst) |
r600g: add initial bank swizzle support. this is ported from r600c mostly, bank swizzling is real messy and I don't think I got enough sleep last night to fully understand it.
2010-09-08 05:09:40 +01:00
S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
} else {
bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
r600g: add initial relative support to assembler passes another ~20 piglits. /me starts to run out low hanging fruit around now.
2010-08-30 06:19:20 +01:00
S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
r600g: mipmap early support + EX2/ABS instruction + culling Add mipmap support (demos/src/redbook/mipmap is working) Add EX2/ABS shader instruction support. Add face culling support. Misc fixes. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-29 19:51:06 +01:00
S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
r600g: implement output modifiers and use them to further optimize LRP
2010-12-16 15:42:14 +00:00
S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
S_SQ_ALU_WORD1_OP2_ALU_INST(alu->inst) |
r600g: add initial bank swizzle support. this is ported from r600c mostly, bank swizzling is real messy and I don't think I got enough sleep last night to fully understand it.
2010-09-08 05:09:40 +01:00
S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
r600g: code cleanup (indent, trailing space, empty line ...) Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-11-17 22:20:59 +00:00
S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->predicate) |
S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->predicate);
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
}
return 0;
}
r600g: add initial evergreen support adds shader opcodes + assembler support (except ARL) uses constant buffers add interp instructions in fragment shader adds all evergreen hw states adds evergreen pm4 support. this runs gears for me on my evergreen
2010-09-03 05:38:41 +01:00
/* common for r600/r700 - eg in eg_asm.c */
r600g: fix some warnings
2010-08-09 13:57:56 +01:00
static int r600_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf)
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
{
unsigned id = cf->id;
switch (cf->inst) {
case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
r600g: add initial if/else/endif support this adds handling for some more CF instructions and conditions also adds parameter for stack size emission These seem to pass on VS with the stack size hack but not on FS, TODO: fix FS + stack size calcs
2010-08-25 06:57:41 +01:00
case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
r600g: optimize away CF_INST_POP If last instruction is an CF_INST_ALU we don't need to emit an additional CF_INST_POP for stack clean up after an IF ELSE ENDIF.
2010-12-13 23:43:53 +00:00
case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
r600g: add support for constants in memory buffers. DX9 constants were in the constant file, and evergreen no longer support cfile. r600/700 can also use constants in memory buffers, so add the code (disabled for now) to enable that as precursor for evergreen.
2010-09-07 23:41:57 +01:00
bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
r600g: Store kcache settings as an array.
2011-01-07 16:06:11 +00:00
S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache[0].mode) |
S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache[0].bank) |
S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache[1].bank);
r600g: add support for constants in memory buffers. DX9 constants were in the constant file, and evergreen no longer support cfile. r600/700 can also use constants in memory buffers, so add the code (disabled for now) to enable that as precursor for evergreen.
2010-09-07 23:41:57 +01:00
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(cf->inst >> 3) |
r600g: Store kcache settings as an array.
2011-01-07 16:06:11 +00:00
S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache[1].mode) |
S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache[0].addr) |
S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache[1].addr) |
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
S_SQ_CF_ALU_WORD1_BARRIER(1) |
r600g: use meaningful defines for chiprev Makes the code much clearer.
2010-11-19 20:32:02 +00:00
S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chiprev == CHIPREV_R600 ? cf->r6xx_uses_waterfall : 0) |
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
break;
r600g: first pass at texture support This add texture support to the assembler, generated code is wrong (tested against working dump). Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-24 01:55:48 +01:00
case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(cf->inst) |
S_SQ_CF_WORD1_BARRIER(1) |
S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1);
break;
case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) |
S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) |
S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst) |
S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program);
break;
r600g: add initial if/else/endif support this adds handling for some more CF instructions and conditions also adds parameter for stack size emission These seem to pass on VS with the stack size hack but not on FS, TODO: fix FS + stack size calcs
2010-08-25 06:57:41 +01:00
case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
case V_SQ_CF_WORD1_SQ_CF_INST_POP:
r600g : add basic loop support. Adds BGNLOOP, BRK, CONT, ENDLOOP support, ported from r600c. 17 piglits more on r300g.tests.
2010-08-27 07:08:55 +01:00
case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
r600g: add fetch shader capabilities Use fetch shader instead of having fetch instruction in the vertex shader. Allow to restrict shader update to a smaller part when vertex buffer input layout changes. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-11-18 19:29:16 +00:00
case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
r600g: add initial if/else/endif support this adds handling for some more CF instructions and conditions also adds parameter for stack size emission These seem to pass on VS with the stack size hack but not on FS, TODO: fix FS + stack size calcs
2010-08-25 06:57:41 +01:00
bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(cf->inst) |
S_SQ_CF_WORD1_BARRIER(1) |
S_SQ_CF_WORD1_COND(cf->cond) |
S_SQ_CF_WORD1_POP_COUNT(cf->pop_count);
break;
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
default:
R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
return -EINVAL;
}
return 0;
}
int r600_bc_build(struct r600_bc *bc)
{
struct r600_bc_cf *cf;
struct r600_bc_alu *alu;
struct r600_bc_vtx *vtx;
r600g: first pass at texture support This add texture support to the assembler, generated code is wrong (tested against working dump). Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-24 01:55:48 +01:00
struct r600_bc_tex *tex;
r600g: rework literal handling
2010-12-22 16:45:51 +00:00
uint32_t literal[4];
unsigned nliteral;
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
unsigned addr;
r600g: rework literal handling
2010-12-22 16:45:51 +00:00
int i, r;
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
r600g : add basic loop support. Adds BGNLOOP, BRK, CONT, ENDLOOP support, ported from r600c. 17 piglits more on r300g.tests.
2010-08-27 07:08:55 +01:00
if (bc->callstack[0].max > 0)
r600g: code cleanup (indent, trailing space, empty line ...) Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-11-17 22:20:59 +00:00
bc->nstack = ((bc->callstack[0].max + 3) >> 2) + 2;
r600g: add fetch shader capabilities Use fetch shader instead of having fetch instruction in the vertex shader. Allow to restrict shader update to a smaller part when vertex buffer input layout changes. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-11-18 19:29:16 +00:00
if (bc->type == TGSI_PROCESSOR_VERTEX && !bc->nstack) {
bc->nstack = 1;
}
r600g : add basic loop support. Adds BGNLOOP, BRK, CONT, ENDLOOP support, ported from r600c. 17 piglits more on r300g.tests.
2010-08-27 07:08:55 +01:00
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
/* first path compute addr of each CF block */
/* addr start after all the CF instructions */
addr = bc->cf_last->id + 2;
LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
switch (cf->inst) {
case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
r600g: optimize away CF_INST_POP If last instruction is an CF_INST_ALU we don't need to emit an additional CF_INST_POP for stack clean up after an IF ELSE ENDIF.
2010-12-13 23:43:53 +00:00
case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
r600g: add initial if/else/endif support this adds handling for some more CF instructions and conditions also adds parameter for stack size emission These seem to pass on VS with the stack size hack but not on FS, TODO: fix FS + stack size calcs
2010-08-25 06:57:41 +01:00
case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
break;
r600g: first pass at texture support This add texture support to the assembler, generated code is wrong (tested against working dump). Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-24 01:55:48 +01:00
case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
/* fetch node need to be 16 bytes aligned*/
addr += 3;
addr &= 0xFFFFFFFCUL;
break;
case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
r600g: add initial evergreen support adds shader opcodes + assembler support (except ARL) uses constant buffers add interp instructions in fragment shader adds all evergreen hw states adds evergreen pm4 support. this runs gears for me on my evergreen
2010-09-03 05:38:41 +01:00
case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
break;
r600g: add initial if/else/endif support this adds handling for some more CF instructions and conditions also adds parameter for stack size emission These seem to pass on VS with the stack size hack but not on FS, TODO: fix FS + stack size calcs
2010-08-25 06:57:41 +01:00
case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
case V_SQ_CF_WORD1_SQ_CF_INST_POP:
r600g : add basic loop support. Adds BGNLOOP, BRK, CONT, ENDLOOP support, ported from r600c. 17 piglits more on r300g.tests.
2010-08-27 07:08:55 +01:00
case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
r600g: add fetch shader capabilities Use fetch shader instead of having fetch instruction in the vertex shader. Allow to restrict shader update to a smaller part when vertex buffer input layout changes. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-11-18 19:29:16 +00:00
case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
r600g: add initial if/else/endif support this adds handling for some more CF instructions and conditions also adds parameter for stack size emission These seem to pass on VS with the stack size hack but not on FS, TODO: fix FS + stack size calcs
2010-08-25 06:57:41 +01:00
break;
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
default:
R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
return -EINVAL;
}
cf->addr = addr;
addr += cf->ndw;
bc->ndw = cf->addr + cf->ndw;
}
free(bc->bytecode);
bc->bytecode = calloc(1, bc->ndw * 4);
if (bc->bytecode == NULL)
return -ENOMEM;
LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
addr = cf->addr;
r600g: use meaningful defines for chiprev Makes the code much clearer.
2010-11-19 20:32:02 +00:00
if (bc->chiprev == CHIPREV_EVERGREEN)
r600g: add initial evergreen support adds shader opcodes + assembler support (except ARL) uses constant buffers add interp instructions in fragment shader adds all evergreen hw states adds evergreen pm4 support. this runs gears for me on my evergreen
2010-09-03 05:38:41 +01:00
r = eg_bc_cf_build(bc, cf);
else
r = r600_bc_cf_build(bc, cf);
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
if (r)
return r;
switch (cf->inst) {
case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
r600g: optimize away CF_INST_POP If last instruction is an CF_INST_ALU we don't need to emit an additional CF_INST_POP for stack clean up after an IF ELSE ENDIF.
2010-12-13 23:43:53 +00:00
case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
r600g: add initial if/else/endif support this adds handling for some more CF instructions and conditions also adds parameter for stack size emission These seem to pass on VS with the stack size hack but not on FS, TODO: fix FS + stack size calcs
2010-08-25 06:57:41 +01:00
case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
r600g: rework literal handling
2010-12-22 16:45:51 +00:00
nliteral = 0;
r600d: fix some bugs added reworking literal handling If a literal slot isn't used it should be set to 0 instead of an uninitialized value. Also the channels for pre R700 trig functions were incorrect. And most important literals were not counted against ndw, resulting in an invalid force_add_cf detection.
2011-01-16 00:45:06 +00:00
memset(literal, 0, sizeof(literal));
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
r600g: pass r600_bc to some addition compiler helper functions needed for asic specific opcodes Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:50:29 +00:00
r = r600_bc_alu_nliterals(bc, alu, literal, &nliteral);
r600g: rework literal handling
2010-12-22 16:45:51 +00:00
if (r)
return r;
r600g: pass r600_bc to some addition compiler helper functions needed for asic specific opcodes Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:50:29 +00:00
r600_bc_alu_adjust_literals(bc, alu, literal, nliteral);
r600g: add a chiprev type for r600/r700/evergreen instead of using family
2010-08-19 05:43:11 +01:00
switch(bc->chiprev) {
r600g: use meaningful defines for chiprev Makes the code much clearer.
2010-11-19 20:32:02 +00:00
case CHIPREV_R600:
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
r = r600_bc_alu_build(bc, alu, addr);
break;
r600g: use meaningful defines for chiprev Makes the code much clearer.
2010-11-19 20:32:02 +00:00
case CHIPREV_R700:
case CHIPREV_EVERGREEN: /* eg alu is same encoding as r700 */
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
r = r700_bc_alu_build(bc, alu, addr);
break;
default:
R600_ERR("unknown family %d\n", bc->family);
return -EINVAL;
}
if (r)
return r;
addr += 2;
if (alu->last) {
r600g: rework literal handling
2010-12-22 16:45:51 +00:00
for (i = 0; i < align(nliteral, 2); ++i) {
bc->bytecode[addr++] = literal[i];
}
nliteral = 0;
r600d: fix some bugs added reworking literal handling If a literal slot isn't used it should be set to 0 instead of an uninitialized value. Also the channels for pre R700 trig functions were incorrect. And most important literals were not counted against ndw, resulting in an invalid force_add_cf detection.
2011-01-16 00:45:06 +00:00
memset(literal, 0, sizeof(literal));
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
}
}
break;
case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
r = r600_bc_vtx_build(bc, vtx, addr);
if (r)
return r;
addr += 4;
}
break;
r600g: first pass at texture support This add texture support to the assembler, generated code is wrong (tested against working dump). Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-24 01:55:48 +01:00
case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
r = r600_bc_tex_build(bc, tex, addr);
if (r)
return r;
addr += 4;
}
break;
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
r600g: add initial evergreen support adds shader opcodes + assembler support (except ARL) uses constant buffers add interp instructions in fragment shader adds all evergreen hw states adds evergreen pm4 support. this runs gears for me on my evergreen
2010-09-03 05:38:41 +01:00
case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
r600g : add basic loop support. Adds BGNLOOP, BRK, CONT, ENDLOOP support, ported from r600c. 17 piglits more on r300g.tests.
2010-08-27 07:08:55 +01:00
case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
r600g: add initial if/else/endif support this adds handling for some more CF instructions and conditions also adds parameter for stack size emission These seem to pass on VS with the stack size hack but not on FS, TODO: fix FS + stack size calcs
2010-08-25 06:57:41 +01:00
case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
case V_SQ_CF_WORD1_SQ_CF_INST_POP:
r600g: add fetch shader capabilities Use fetch shader instead of having fetch instruction in the vertex shader. Allow to restrict shader update to a smaller part when vertex buffer input layout changes. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-11-18 19:29:16 +00:00
case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
r600g: drop compiler stuff and switch over dumb tgsi assembler Writing a compiler is time consuming and error prone in order to allow r600g to further progress in the meantime i wrote a simple tgsi assembler, it does stupid thing but i would rather keep the code simple than having people trying to optimize code it does. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-07-23 22:32:32 +01:00
break;
default:
R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
return -EINVAL;
}
}
return 0;
}
r600g: Also clear bc data when we're destroying a shader. [airlied: remove unused vars] Signed-off-by: Tilman Sauerbeck <tilman@code-monkey.de> Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-10-23 12:33:22 +01:00
void r600_bc_clear(struct r600_bc *bc)
{
r600g: Silence uninitialized variable warnings.
2010-10-27 17:26:27 +01:00
struct r600_bc_cf *cf = NULL, *next_cf;
r600g: Also clear bc data when we're destroying a shader. [airlied: remove unused vars] Signed-off-by: Tilman Sauerbeck <tilman@code-monkey.de> Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-10-23 12:33:22 +01:00
free(bc->bytecode);
bc->bytecode = NULL;
LIST_FOR_EACH_ENTRY_SAFE(cf, next_cf, &bc->cf, list) {
r600g: Silence uninitialized variable warnings.
2010-10-27 17:26:27 +01:00
struct r600_bc_alu *alu = NULL, *next_alu;
struct r600_bc_tex *tex = NULL, *next_tex;
struct r600_bc_tex *vtx = NULL, *next_vtx;
r600g: Also clear bc data when we're destroying a shader. [airlied: remove unused vars] Signed-off-by: Tilman Sauerbeck <tilman@code-monkey.de> Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-10-23 12:33:22 +01:00
LIST_FOR_EACH_ENTRY_SAFE(alu, next_alu, &cf->alu, list) {
free(alu);
}
LIST_INITHEAD(&cf->alu);
LIST_FOR_EACH_ENTRY_SAFE(tex, next_tex, &cf->tex, list) {
free(tex);
}
LIST_INITHEAD(&cf->tex);
LIST_FOR_EACH_ENTRY_SAFE(vtx, next_vtx, &cf->vtx, list) {
free(vtx);
}
LIST_INITHEAD(&cf->vtx);
free(cf);
}
LIST_INITHEAD(&cf->list);
}
r600g: dump raw shader output for debugging Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-12-03 16:34:47 +00:00
void r600_bc_dump(struct r600_bc *bc)
{
r600g: Silence uninitialized variable warnings.
2011-01-13 17:07:19 +00:00
struct r600_bc_cf *cf = NULL;
struct r600_bc_alu *alu = NULL;
struct r600_bc_vtx *vtx = NULL;
struct r600_bc_tex *tex = NULL;
r600g: improve r600_bc_dump
2010-12-16 21:05:33 +00:00
unsigned i, id;
r600g: rework literal handling
2010-12-22 16:45:51 +00:00
uint32_t literal[4];
unsigned nliteral;
r600g: dump raw shader output for debugging Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-12-03 16:34:47 +00:00
char chip = '6';
switch (bc->chiprev) {
case 1:
chip = '7';
break;
case 2:
chip = 'E';
break;
case 0:
default:
chip = '6';
break;
}
r600g: also look at tex inst when for maximum gpu count
2011-01-12 19:39:40 +00:00
fprintf(stderr, "bytecode %d dw -- %d gprs ---------------------\n", bc->ndw, bc->ngpr);
r600g: dump raw shader output for debugging Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-12-03 16:34:47 +00:00
fprintf(stderr, " %c\n", chip);
r600g: improve r600_bc_dump
2010-12-16 21:05:33 +00:00
LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
id = cf->id;
switch (cf->inst) {
case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
fprintf(stderr, "ADDR:%d ", cf->addr);
fprintf(stderr, "KCACHE_MODE0:%X ", cf->kcache[0].mode);
fprintf(stderr, "KCACHE_BANK0:%X ", cf->kcache[0].bank);
fprintf(stderr, "KCACHE_BANK1:%X\n", cf->kcache[1].bank);
id++;
fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
fprintf(stderr, "INST:%d ", cf->inst);
fprintf(stderr, "KCACHE_MODE1:%X ", cf->kcache[1].mode);
fprintf(stderr, "KCACHE_ADDR0:%X ", cf->kcache[0].addr);
fprintf(stderr, "KCACHE_ADDR1:%X ", cf->kcache[1].addr);
fprintf(stderr, "COUNT:%d\n", cf->ndw / 2);
break;
case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
fprintf(stderr, "ADDR:%d\n", cf->addr);
id++;
fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
fprintf(stderr, "INST:%d ", cf->inst);
fprintf(stderr, "COUNT:%d\n", cf->ndw / 4);
break;
case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
fprintf(stderr, "GPR:%X ", cf->output.gpr);
fprintf(stderr, "ELEM_SIZE:%X ", cf->output.elem_size);
fprintf(stderr, "ARRAY_BASE:%X ", cf->output.array_base);
fprintf(stderr, "TYPE:%X\n", cf->output.type);
id++;
fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
fprintf(stderr, "SWIZ_X:%X ", cf->output.swizzle_x);
fprintf(stderr, "SWIZ_Y:%X ", cf->output.swizzle_y);
fprintf(stderr, "SWIZ_Z:%X ", cf->output.swizzle_z);
fprintf(stderr, "SWIZ_W:%X ", cf->output.swizzle_w);
fprintf(stderr, "SWIZ_W:%X ", cf->output.swizzle_w);
fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
fprintf(stderr, "INST:%d ", cf->output.inst);
fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
break;
case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
case V_SQ_CF_WORD1_SQ_CF_INST_POP:
case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
fprintf(stderr, "ADDR:%d\n", cf->cf_addr);
id++;
fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
fprintf(stderr, "INST:%d ", cf->inst);
fprintf(stderr, "COND:%X ", cf->cond);
fprintf(stderr, "POP_COUNT:%X\n", cf->pop_count);
break;
}
r600g: fix alu dumping
2010-12-17 21:57:36 +00:00
id = cf->addr;
r600g: rework literal handling
2010-12-22 16:45:51 +00:00
nliteral = 0;
r600g: improve r600_bc_dump
2010-12-16 21:05:33 +00:00
LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
r600g: pass r600_bc to some addition compiler helper functions needed for asic specific opcodes Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-14 22:50:29 +00:00
r600_bc_alu_nliterals(bc, alu, literal, &nliteral);
r600g: rework literal handling
2010-12-22 16:45:51 +00:00
r600g: fix alu dumping
2010-12-17 21:57:36 +00:00
fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
r600g: improve r600_bc_dump
2010-12-16 21:05:33 +00:00
fprintf(stderr, "SRC0(SEL:%d ", alu->src[0].sel);
fprintf(stderr, "REL:%d ", alu->src[0].rel);
fprintf(stderr, "CHAN:%d ", alu->src[0].chan);
fprintf(stderr, "NEG:%d) ", alu->src[0].neg);
fprintf(stderr, "SRC1(SEL:%d ", alu->src[1].sel);
fprintf(stderr, "REL:%d ", alu->src[1].rel);
fprintf(stderr, "CHAN:%d ", alu->src[1].chan);
fprintf(stderr, "NEG:%d) ", alu->src[1].neg);
fprintf(stderr, "LAST:%d)\n", alu->last);
id++;
r600g: fix alu dumping
2010-12-17 21:57:36 +00:00
fprintf(stderr, "%04d %08X %c ", id, bc->bytecode[id], alu->last ? '*' : ' ');
fprintf(stderr, "INST:%d ", alu->inst);
fprintf(stderr, "DST(SEL:%d ", alu->dst.sel);
fprintf(stderr, "CHAN:%d ", alu->dst.chan);
fprintf(stderr, "REL:%d ", alu->dst.rel);
fprintf(stderr, "CLAMP:%d) ", alu->dst.clamp);
fprintf(stderr, "BANK_SWIZZLE:%d ", alu->bank_swizzle);
r600g: improve r600_bc_dump
2010-12-16 21:05:33 +00:00
if (alu->is_op3) {
fprintf(stderr, "SRC2(SEL:%d ", alu->src[2].sel);
fprintf(stderr, "REL:%d ", alu->src[2].rel);
fprintf(stderr, "CHAN:%d ", alu->src[2].chan);
r600g: fix alu dumping
2010-12-17 21:57:36 +00:00
fprintf(stderr, "NEG:%d)\n", alu->src[2].neg);
r600g: improve r600_bc_dump
2010-12-16 21:05:33 +00:00
} else {
fprintf(stderr, "SRC0_ABS:%d ", alu->src[0].abs);
fprintf(stderr, "SRC1_ABS:%d ", alu->src[1].abs);
fprintf(stderr, "WRITE_MASK:%d ", alu->dst.write);
r600g: implement output modifiers and use them to further optimize LRP
2010-12-16 15:42:14 +00:00
fprintf(stderr, "OMOD:%d ", alu->omod);
r600g: improve r600_bc_dump
2010-12-16 21:05:33 +00:00
fprintf(stderr, "EXECUTE_MASK:%d ", alu->predicate);
fprintf(stderr, "UPDATE_PRED:%d\n", alu->predicate);
}
r600g: fix alu dumping
2010-12-17 21:57:36 +00:00
id++;
r600g: improve r600_bc_dump
2010-12-16 21:05:33 +00:00
if (alu->last) {
r600g: rework literal handling
2010-12-22 16:45:51 +00:00
for (i = 0; i < nliteral; i++, id++) {
r600g: improve r600_bc_dump
2010-12-16 21:05:33 +00:00
float *f = (float*)(bc->bytecode + id);
r600g: fix alu dumping
2010-12-17 21:57:36 +00:00
fprintf(stderr, "%04d %08X\t%f\n", id, bc->bytecode[id], *f);
r600g: improve r600_bc_dump
2010-12-16 21:05:33 +00:00
}
r600g: rework literal handling
2010-12-22 16:45:51 +00:00
id += nliteral & 1;
nliteral = 0;
r600g: improve r600_bc_dump
2010-12-16 21:05:33 +00:00
}
}
LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
//TODO
}
LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
//TODO
}
r600g: dump raw shader output for debugging Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-12-03 16:34:47 +00:00
}
r600g: improve r600_bc_dump
2010-12-16 21:05:33 +00:00
r600g: dump raw shader output for debugging Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-12-03 16:34:47 +00:00
fprintf(stderr, "--------------------------------------\n");
}
r600g: build fetch shader from vertex elements Vertex elements change are less frequent than draw call, those to avoid rebuilding fetch shader to often build the fetch shader along vertex elements. This also allow to move vertex buffer setup out of draw path and make update to it less frequent. Shader update can still be improved to only update SPI regs (based on some rasterizer state like flat shading or point sprite ...). Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-12-04 01:47:02 +00:00
void r600_cf_vtx(struct r600_vertex_element *ve, u32 *bytecode, unsigned count)
{
struct r600_pipe_state *rstate;
unsigned i = 0;
if (count > 8) {
bytecode[i++] = S_SQ_CF_WORD0_ADDR(8 >> 1);
bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX) |
S_SQ_CF_WORD1_BARRIER(1) |
S_SQ_CF_WORD1_COUNT(8 - 1);
bytecode[i++] = S_SQ_CF_WORD0_ADDR(40 >> 1);
bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX) |
S_SQ_CF_WORD1_BARRIER(1) |
S_SQ_CF_WORD1_COUNT(count - 8 - 1);
} else {
bytecode[i++] = S_SQ_CF_WORD0_ADDR(8 >> 1);
bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX) |
S_SQ_CF_WORD1_BARRIER(1) |
S_SQ_CF_WORD1_COUNT(count - 1);
}
bytecode[i++] = S_SQ_CF_WORD0_ADDR(0);
bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_RETURN) |
S_SQ_CF_WORD1_BARRIER(1);
rstate = &ve->rstate;
rstate->id = R600_PIPE_STATE_FETCH_SHADER;
rstate->nregs = 0;
r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_RESOURCES_FS,
0x00000000, 0xFFFFFFFF, NULL);
r600_pipe_state_add_reg(rstate, R_0288DC_SQ_PGM_CF_OFFSET_FS,
0x00000000, 0xFFFFFFFF, NULL);
r600_pipe_state_add_reg(rstate, R_028894_SQ_PGM_START_FS,
r600_bo_offset(ve->fetch_shader) >> 8,
0xFFFFFFFF, ve->fetch_shader);
}
void r600_cf_vtx_tc(struct r600_vertex_element *ve, u32 *bytecode, unsigned count)
{
struct r600_pipe_state *rstate;
unsigned i = 0;
if (count > 8) {
bytecode[i++] = S_SQ_CF_WORD0_ADDR(8 >> 1);
bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC) |
S_SQ_CF_WORD1_BARRIER(1) |
S_SQ_CF_WORD1_COUNT(8 - 1);
bytecode[i++] = S_SQ_CF_WORD0_ADDR(40 >> 1);
bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC) |
S_SQ_CF_WORD1_BARRIER(1) |
S_SQ_CF_WORD1_COUNT((count - 8) - 1);
} else {
bytecode[i++] = S_SQ_CF_WORD0_ADDR(8 >> 1);
bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC) |
S_SQ_CF_WORD1_BARRIER(1) |
S_SQ_CF_WORD1_COUNT(count - 1);
}
bytecode[i++] = S_SQ_CF_WORD0_ADDR(0);
bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_RETURN) |
S_SQ_CF_WORD1_BARRIER(1);
rstate = &ve->rstate;
rstate->id = R600_PIPE_STATE_FETCH_SHADER;
rstate->nregs = 0;
r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_RESOURCES_FS,
0x00000000, 0xFFFFFFFF, NULL);
r600_pipe_state_add_reg(rstate, R_0288DC_SQ_PGM_CF_OFFSET_FS,
0x00000000, 0xFFFFFFFF, NULL);
r600_pipe_state_add_reg(rstate, R_028894_SQ_PGM_START_FS,
r600_bo_offset(ve->fetch_shader) >> 8,
0xFFFFFFFF, ve->fetch_shader);
}
static void r600_vertex_data_type(enum pipe_format pformat, unsigned *format,
unsigned *num_format, unsigned *format_comp)
{
const struct util_format_description *desc;
unsigned i;
*format = 0;
*num_format = 0;
*format_comp = 0;
desc = util_format_description(pformat);
if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) {
goto out_unknown;
}
/* Find the first non-VOID channel. */
for (i = 0; i < 4; i++) {
if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
break;
}
}
switch (desc->channel[i].type) {
/* Half-floats, floats, doubles */
case UTIL_FORMAT_TYPE_FLOAT:
switch (desc->channel[i].size) {
case 16:
switch (desc->nr_channels) {
case 1:
*format = FMT_16_FLOAT;
break;
case 2:
*format = FMT_16_16_FLOAT;
break;
case 3:
*format = FMT_16_16_16_FLOAT;
break;
case 4:
*format = FMT_16_16_16_16_FLOAT;
break;
}
break;
case 32:
switch (desc->nr_channels) {
case 1:
*format = FMT_32_FLOAT;
break;
case 2:
*format = FMT_32_32_FLOAT;
break;
case 3:
*format = FMT_32_32_32_FLOAT;
break;
case 4:
*format = FMT_32_32_32_32_FLOAT;
break;
}
break;
default:
goto out_unknown;
}
break;
/* Unsigned ints */
case UTIL_FORMAT_TYPE_UNSIGNED:
/* Signed ints */
case UTIL_FORMAT_TYPE_SIGNED:
switch (desc->channel[i].size) {
case 8:
switch (desc->nr_channels) {
case 1:
*format = FMT_8;
break;
case 2:
*format = FMT_8_8;
break;
case 3:
// *format = FMT_8_8_8; /* fails piglit draw-vertices test */
// break;
case 4:
*format = FMT_8_8_8_8;
break;
}
break;
case 16:
switch (desc->nr_channels) {
case 1:
*format = FMT_16;
break;
case 2:
*format = FMT_16_16;
break;
case 3:
// *format = FMT_16_16_16; /* fails piglit draw-vertices test */
// break;
case 4:
*format = FMT_16_16_16_16;
break;
}
break;
case 32:
switch (desc->nr_channels) {
case 1:
*format = FMT_32;
break;
case 2:
*format = FMT_32_32;
break;
case 3:
*format = FMT_32_32_32;
break;
case 4:
*format = FMT_32_32_32_32;
break;
}
break;
default:
goto out_unknown;
}
break;
default:
goto out_unknown;
}
if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
*format_comp = 1;
}
if (desc->channel[i].normalized) {
*num_format = 0;
} else {
*num_format = 2;
}
return;
out_unknown:
R600_ERR("unsupported vertex format %s\n", util_format_name(pformat));
}
int r600_vertex_elements_build_fetch_shader(struct r600_pipe_context *rctx, struct r600_vertex_element *ve)
{
unsigned ndw, i;
u32 *bytecode;
unsigned fetch_resource_start = 0, format, num_format, format_comp;
struct pipe_vertex_element *elements = ve->elements;
const struct util_format_description *desc;
/* 2 dwords for cf aligned to 4 + 4 dwords per input */
ndw = 8 + ve->count * 4;
ve->fs_size = ndw * 4;
/* use PIPE_BIND_VERTEX_BUFFER so we use the cache buffer manager */
ve->fetch_shader = r600_bo(rctx->radeon, ndw*4, 256, PIPE_BIND_VERTEX_BUFFER, 0);
if (ve->fetch_shader == NULL) {
return -ENOMEM;
}
bytecode = r600_bo_map(rctx->radeon, ve->fetch_shader, 0, NULL);
if (bytecode == NULL) {
r600_bo_reference(rctx->radeon, &ve->fetch_shader, NULL);
return -ENOMEM;
}
if (rctx->family >= CHIP_CEDAR) {
eg_cf_vtx(ve, &bytecode[0], (ndw - 8) / 4);
} else {
r600_cf_vtx(ve, &bytecode[0], (ndw - 8) / 4);
fetch_resource_start = 160;
}
/* vertex elements offset need special handling, if offset is bigger
* than what we can put in fetch instruction then we need to alterate
* the vertex resource offset. In such case in order to simplify code
* we will bound one resource per elements. It's a worst case scenario.
*/
for (i = 0; i < ve->count; i++) {
ve->vbuffer_offset[i] = C_SQ_VTX_WORD2_OFFSET & elements[i].src_offset;
if (ve->vbuffer_offset[i]) {
ve->vbuffer_need_offset = 1;
}
}
for (i = 0; i < ve->count; i++) {
unsigned vbuffer_index;
r600_vertex_data_type(ve->hw_format[i], &format, &num_format, &format_comp);
desc = util_format_description(ve->hw_format[i]);
if (desc == NULL) {
R600_ERR("unknown format %d\n", ve->hw_format[i]);
r600_bo_reference(rctx->radeon, &ve->fetch_shader, NULL);
return -EINVAL;
}
/* see above for vbuffer_need_offset explanation */
vbuffer_index = elements[i].vertex_buffer_index;
if (ve->vbuffer_need_offset) {
bytecode[8 + i * 4 + 0] = S_SQ_VTX_WORD0_BUFFER_ID(i + fetch_resource_start);
} else {
bytecode[8 + i * 4 + 0] = S_SQ_VTX_WORD0_BUFFER_ID(vbuffer_index + fetch_resource_start);
}
bytecode[8 + i * 4 + 0] |= S_SQ_VTX_WORD0_SRC_GPR(0) |
S_SQ_VTX_WORD0_SRC_SEL_X(0) |
S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(0x1F);
bytecode[8 + i * 4 + 1] = S_SQ_VTX_WORD1_DST_SEL_X(desc->swizzle[0]) |
S_SQ_VTX_WORD1_DST_SEL_Y(desc->swizzle[1]) |
S_SQ_VTX_WORD1_DST_SEL_Z(desc->swizzle[2]) |
S_SQ_VTX_WORD1_DST_SEL_W(desc->swizzle[3]) |
S_SQ_VTX_WORD1_USE_CONST_FIELDS(0) |
S_SQ_VTX_WORD1_DATA_FORMAT(format) |
S_SQ_VTX_WORD1_NUM_FORMAT_ALL(num_format) |
S_SQ_VTX_WORD1_FORMAT_COMP_ALL(format_comp) |
S_SQ_VTX_WORD1_SRF_MODE_ALL(1) |
S_SQ_VTX_WORD1_GPR_DST_GPR(i + 1);
bytecode[8 + i * 4 + 2] = S_SQ_VTX_WORD2_OFFSET(elements[i].src_offset) |
S_SQ_VTX_WORD2_MEGA_FETCH(1);
bytecode[8 + i * 4 + 3] = 0;
}
r600_bo_unmap(rctx->radeon, ve->fetch_shader);
return 0;
}