r600g: add initial bank swizzle support.
this is ported from r600c mostly, bank swizzling is real messy and I don't think I got enough sleep last night to fully understand it.
This commit is contained in:
Dave Airlie
parent
48e789d71e
commit
bf346f065c
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@ -28,6 +28,57 @@
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#include <stdio.h>
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#include <errno.h>
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static inline unsigned int r600_bc_get_num_operands(struct r600_bc_alu *alu)
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{
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if(alu->is_op3)
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return 3;
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switch (alu->inst) {
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case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
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return 0;
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case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
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case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
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case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
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case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
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case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
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case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
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case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
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case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
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case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
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case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
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case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
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case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
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case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
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case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
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case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
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case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
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case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
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case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
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case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
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return 2;
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case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
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case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR:
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case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
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case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
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case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
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case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
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case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
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case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
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case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
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case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
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case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
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case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
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case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
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return 1;
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default: R600_ERR(
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"Need instruction operand number for 0x%x.\n", alu->inst);
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};
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return 3;
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}
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int r700_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id);
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static struct r600_bc_cf *r600_bc_cf(void)
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@ -50,6 +101,7 @@ static struct r600_bc_alu *r600_bc_alu(void)
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if (alu == NULL)
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return NULL;
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LIST_INITHEAD(&alu->list);
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LIST_INITHEAD(&alu->bs_list);
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return alu;
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}
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@ -129,10 +181,219 @@ int r600_bc_add_output(struct r600_bc *bc, const struct r600_bc_output *output)
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return 0;
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}
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const unsigned bank_swizzle_vec[8] = {SQ_ALU_VEC_210, //000
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SQ_ALU_VEC_120, //001
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SQ_ALU_VEC_102, //010
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SQ_ALU_VEC_201, //011
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SQ_ALU_VEC_012, //100
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SQ_ALU_VEC_021, //101
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SQ_ALU_VEC_012, //110
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SQ_ALU_VEC_012}; //111
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const unsigned bank_swizzle_scl[8] = {SQ_ALU_SCL_210, //000
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SQ_ALU_SCL_122, //001
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SQ_ALU_SCL_122, //010
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SQ_ALU_SCL_221, //011
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SQ_ALU_SCL_212, //100
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SQ_ALU_SCL_122, //101
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SQ_ALU_SCL_122, //110
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SQ_ALU_SCL_122}; //111
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static int init_gpr(struct r600_bc_alu *alu)
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{
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int cycle, component;
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/* set up gpr use */
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for (cycle = 0; cycle < NUM_OF_CYCLES; cycle++)
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for (component = 0; component < NUM_OF_COMPONENTS; component++)
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alu->hw_gpr[cycle][component] = -1;
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return 0;
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}
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static int reserve_gpr(struct r600_bc_alu *alu, unsigned sel, unsigned chan, unsigned cycle)
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{
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if (alu->hw_gpr[cycle][chan] < 0)
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alu->hw_gpr[cycle][chan] = sel;
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else if (alu->hw_gpr[cycle][chan] != (int)sel) {
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R600_ERR("Another scalar operation has already used GPR read port for channel\n");
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return -1;
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}
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return 0;
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}
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static int cycle_for_scalar_bank_swizzle(const int swiz, const int sel, unsigned *p_cycle)
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{
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int table[3];
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int ret = 0;
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switch (swiz) {
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case SQ_ALU_SCL_210:
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table[0] = 2; table[1] = 1; table[2] = 0;
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*p_cycle = table[sel];
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break;
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case SQ_ALU_SCL_122:
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table[0] = 1; table[1] = 2; table[2] = 2;
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*p_cycle = table[sel];
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break;
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case SQ_ALU_SCL_212:
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table[0] = 2; table[1] = 1; table[2] = 2;
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*p_cycle = table[sel];
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break;
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case SQ_ALU_SCL_221:
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table[0] = 2; table[1] = 2; table[2] = 1;
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*p_cycle = table[sel];
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break;
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break;
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default:
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R600_ERR("bad scalar bank swizzle value\n");
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ret = -1;
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break;
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}
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return ret;
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}
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static int cycle_for_vector_bank_swizzle(const int swiz, const int sel, unsigned *p_cycle)
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{
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int table[3];
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int ret;
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switch (swiz) {
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case SQ_ALU_VEC_012:
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table[0] = 0; table[1] = 1; table[2] = 2;
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*p_cycle = table[sel];
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break;
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case SQ_ALU_VEC_021:
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table[0] = 0; table[1] = 2; table[2] = 1;
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*p_cycle = table[sel];
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break;
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case SQ_ALU_VEC_120:
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table[0] = 1; table[1] = 2; table[2] = 0;
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*p_cycle = table[sel];
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break;
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case SQ_ALU_VEC_102:
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table[0] = 1; table[1] = 0; table[2] = 2;
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*p_cycle = table[sel];
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break;
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case SQ_ALU_VEC_201:
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table[0] = 2; table[1] = 0; table[2] = 1;
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*p_cycle = table[sel];
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break;
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case SQ_ALU_VEC_210:
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table[0] = 2; table[1] = 1; table[2] = 0;
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*p_cycle = table[sel];
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break;
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default:
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R600_ERR("bad vector bank swizzle value\n");
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ret = -1;
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break;
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}
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return ret;
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}
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static int is_const(int sel)
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{
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if (sel > 255 && sel < 512)
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return 1;
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if (sel >= V_SQ_ALU_SRC_0 && sel <= V_SQ_ALU_SRC_LITERAL)
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return 1;
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return 0;
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}
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static void update_chan_counter(struct r600_bc_alu *alu, int *chan_counter)
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{
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int num_src;
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int i;
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int channel_swizzle;
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num_src = r600_bc_get_num_operands(alu);
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for (i = 0; i < num_src; i++) {
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channel_swizzle = alu->src[i].chan;
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if ((alu->src[i].sel > 0 && alu->src[i].sel < 128) && channel_swizzle <= 3)
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chan_counter[channel_swizzle]++;
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}
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}
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#if 0
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/* we need something like this I think - but this is bogus */
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int check_read_slots(struct r600_bc *bc, struct r600_bc_alu *alu_first)
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{
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struct r600_bc_alu *alu;
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int chan_counter[4] = { 0 };
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update_chan_counter(alu_first, chan_counter);
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LIST_FOR_EACH_ENTRY(alu, &alu_first->bs_list, bs_list) {
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update_chan_counter(alu, chan_counter);
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}
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if (chan_counter[0] > 3 ||
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chan_counter[1] > 3 ||
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chan_counter[2] > 3 ||
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chan_counter[3] > 3) {
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R600_ERR("needed to split instruction for input ran out of banks %x %d %d %d %d\n",
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alu_first->inst, chan_counter[0], chan_counter[1], chan_counter[2], chan_counter[3]);
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return -1;
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}
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return 0;
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}
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#endif
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static int check_scalar(struct r600_bc *bc, struct r600_bc_alu *alu)
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{
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unsigned swizzle_key;
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swizzle_key = (is_const(alu->src[0].sel) ? 4 : 0 ) +
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(is_const(alu->src[1].sel) ? 2 : 0 ) +
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(is_const(alu->src[2].sel) ? 1 : 0 );
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alu->bank_swizzle = bank_swizzle_scl[swizzle_key];
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return 0;
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}
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static int check_vector(struct r600_bc *bc, struct r600_bc_alu *alu)
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{
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unsigned swizzle_key;
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swizzle_key = (is_const(alu->src[0].sel) ? 4 : 0 ) +
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(is_const(alu->src[1].sel) ? 2 : 0 ) +
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(is_const(alu->src[2].sel) ? 1 : 0 );
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alu->bank_swizzle = bank_swizzle_vec[swizzle_key];
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return 0;
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}
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static int check_and_set_bank_swizzle(struct r600_bc *bc, struct r600_bc_alu *alu_first)
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{
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struct r600_bc_alu *alu;
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int num_instr = 1;
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init_gpr(alu_first);
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LIST_FOR_EACH_ENTRY(alu, &alu_first->bs_list, bs_list) {
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num_instr++;
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}
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if (num_instr == 1) {
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check_scalar(bc, alu_first);
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} else {
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/* check_read_slots(bc, bc->cf_last->curr_bs_head);*/
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check_vector(bc, alu_first);
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LIST_FOR_EACH_ENTRY(alu, &alu_first->bs_list, bs_list) {
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check_vector(bc, alu);
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}
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}
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return 0;
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}
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int r600_bc_add_alu_type(struct r600_bc *bc, const struct r600_bc_alu *alu, int type)
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{
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struct r600_bc_alu *nalu = r600_bc_alu();
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struct r600_bc_alu *lalu;
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struct r600_bc_alu *curr_bs_head;
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int i, r;
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if (nalu == NULL)
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@ -151,6 +412,12 @@ int r600_bc_add_alu_type(struct r600_bc *bc, const struct r600_bc_alu *alu, int
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}
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bc->cf_last->inst = (type << 3);
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}
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if (!bc->cf_last->curr_bs_head) {
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bc->cf_last->curr_bs_head = nalu;
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LIST_INITHEAD(&nalu->bs_list);
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} else {
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LIST_ADDTAIL(&nalu->bs_list, &bc->cf_last->curr_bs_head->bs_list);
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}
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if (alu->last && (bc->cf_last->ndw >> 1) >= 124) {
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bc->force_add_cf = 1;
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}
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@ -185,6 +452,11 @@ int r600_bc_add_alu_type(struct r600_bc *bc, const struct r600_bc_alu *alu, int
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if (bc->use_mem_constant)
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bc->cf_last->kcache0_mode = 2;
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/* process cur ALU instructions for bank swizzle */
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if (alu->last) {
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check_and_set_bank_swizzle(bc, bc->cf_last->curr_bs_head);
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bc->cf_last->curr_bs_head = NULL;
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}
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return 0;
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}
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@ -365,7 +637,7 @@ static int r600_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsign
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S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
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S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
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S_SQ_ALU_WORD1_OP3_ALU_INST(alu->inst) |
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S_SQ_ALU_WORD1_BANK_SWIZZLE(0);
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S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
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} else {
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bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
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S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
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@ -375,7 +647,7 @@ static int r600_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsign
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S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
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S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
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S_SQ_ALU_WORD1_OP2_ALU_INST(alu->inst) |
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S_SQ_ALU_WORD1_BANK_SWIZZLE(0) |
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S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
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S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->predicate) |
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S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->predicate);
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}
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@ -26,6 +26,9 @@
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#include "radeon.h"
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#include "util/u_double_list.h"
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#define NUM_OF_CYCLES 3
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#define NUM_OF_COMPONENTS 4
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struct r600_bc_alu_src {
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unsigned sel;
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unsigned chan;
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@ -44,6 +47,7 @@ struct r600_bc_alu_dst {
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struct r600_bc_alu {
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struct list_head list;
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struct list_head bs_list; /* bank swizzle list */
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struct r600_bc_alu_src src[3];
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struct r600_bc_alu_dst dst;
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unsigned inst;
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@ -52,7 +56,9 @@ struct r600_bc_alu {
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unsigned predicate;
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unsigned nliteral;
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unsigned literal_added;
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unsigned bank_swizzle;
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u32 value[4];
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int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS];
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};
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struct r600_bc_tex {
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@ -125,6 +131,7 @@ struct r600_bc_cf {
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struct list_head tex;
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struct list_head vtx;
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struct r600_bc_output output;
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struct r600_bc_alu *curr_bs_head;
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};
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#define FC_NONE 0
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@ -455,4 +455,16 @@
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#define V_SQ_REL_ABSOLUTE 0
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#define V_SQ_REL_RELATIVE 1
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#define SQ_ALU_VEC_012 0x00
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#define SQ_ALU_VEC_021 0x01
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#define SQ_ALU_VEC_120 0x02
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#define SQ_ALU_VEC_102 0x03
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#define SQ_ALU_VEC_201 0x04
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#define SQ_ALU_VEC_210 0x05
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#define SQ_ALU_SCL_210 0x00000000
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#define SQ_ALU_SCL_122 0x00000001
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#define SQ_ALU_SCL_212 0x00000002
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#define SQ_ALU_SCL_221 0x00000003
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#endif
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@ -51,7 +51,7 @@ int r700_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id)
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S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
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S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
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S_SQ_ALU_WORD1_OP3_ALU_INST(alu->inst) |
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S_SQ_ALU_WORD1_BANK_SWIZZLE(0);
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S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
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} else {
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bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
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S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
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@ -61,7 +61,7 @@ int r700_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id)
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S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
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S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
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S_SQ_ALU_WORD1_OP2_ALU_INST(alu->inst) |
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S_SQ_ALU_WORD1_BANK_SWIZZLE(0) |
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S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
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S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->predicate) |
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S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->predicate);
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}
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Reference in New Issue