2016-04-01 13:57:54 +01:00
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/*
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* Copyright © 2013 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "util/ralloc.h"
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2016-08-31 00:32:51 +01:00
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#include "main/macros.h" /* Needed for MAX3 and MAX2 for format_rgb9e5 */
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#include "util/format_rgb9e5.h"
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2017-08-02 23:07:33 +01:00
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#include "util/format_srgb.h"
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2016-08-31 00:32:51 +01:00
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2016-08-08 23:25:17 +01:00
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#include "blorp_priv.h"
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2017-02-28 17:10:43 +00:00
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#include "compiler/brw_eu_defines.h"
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2016-04-01 13:57:54 +01:00
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2017-06-23 18:27:27 +01:00
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#include "blorp_nir_builder.h"
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2016-04-28 01:17:11 +01:00
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2016-04-01 13:57:54 +01:00
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#define FILE_DEBUG_FLAG DEBUG_BLORP
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2019-10-30 14:14:06 +00:00
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#pragma pack(push, 1)
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2016-04-01 13:57:54 +01:00
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struct brw_blorp_const_color_prog_key
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{
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2016-10-21 19:30:05 +01:00
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enum blorp_shader_type shader_type; /* Must be BLORP_SHADER_TYPE_CLEAR */
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2016-04-01 13:57:54 +01:00
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bool use_simd16_replicated_data;
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2018-07-12 22:05:26 +01:00
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bool clear_rgb_as_red;
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2016-04-01 13:57:54 +01:00
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};
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2019-10-30 14:14:06 +00:00
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#pragma pack(pop)
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2016-04-01 13:57:54 +01:00
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2017-03-14 12:12:22 +00:00
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static bool
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2019-01-09 23:15:49 +00:00
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blorp_params_get_clear_kernel(struct blorp_batch *batch,
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2016-08-19 13:43:29 +01:00
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struct blorp_params *params,
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2018-07-12 22:05:26 +01:00
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bool use_replicated_data,
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bool clear_rgb_as_red)
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2016-04-01 13:57:54 +01:00
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{
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2019-01-09 23:15:49 +00:00
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struct blorp_context *blorp = batch->blorp;
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2016-10-21 19:30:05 +01:00
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const struct brw_blorp_const_color_prog_key blorp_key = {
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.shader_type = BLORP_SHADER_TYPE_CLEAR,
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.use_simd16_replicated_data = use_replicated_data,
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2018-07-12 22:05:26 +01:00
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.clear_rgb_as_red = clear_rgb_as_red,
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2016-10-21 19:30:05 +01:00
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};
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2016-04-01 13:57:54 +01:00
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2019-01-09 23:15:49 +00:00
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if (blorp->lookup_shader(batch, &blorp_key, sizeof(blorp_key),
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2016-08-19 08:54:56 +01:00
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¶ms->wm_prog_kernel, ¶ms->wm_prog_data))
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2017-03-14 12:12:22 +00:00
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return true;
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2016-04-01 13:57:54 +01:00
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2016-04-28 01:17:11 +01:00
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void *mem_ctx = ralloc_context(NULL);
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2016-04-01 13:57:54 +01:00
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2016-04-28 01:17:11 +01:00
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nir_builder b;
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2020-09-29 08:54:07 +01:00
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blorp_nir_init_shader(&b, mem_ctx, MESA_SHADER_FRAGMENT,
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blorp_shader_type_to_name(blorp_key.shader_type));
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2016-04-01 13:57:54 +01:00
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2016-10-21 22:15:03 +01:00
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nir_variable *v_color =
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BLORP_CREATE_NIR_INPUT(b.shader, clear_color, glsl_vec4_type());
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2018-07-12 22:05:26 +01:00
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nir_ssa_def *color = nir_load_var(&b, v_color);
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if (clear_rgb_as_red) {
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2019-07-18 15:59:44 +01:00
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nir_ssa_def *pos = nir_f2i32(&b, nir_load_frag_coord(&b));
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2018-07-12 22:05:26 +01:00
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nir_ssa_def *comp = nir_umod(&b, nir_channel(&b, pos, 0),
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nir_imm_int(&b, 3));
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nir_ssa_def *color_component =
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2020-08-15 06:11:27 +01:00
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nir_bcsel(&b, nir_ieq_imm(&b, comp, 0),
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2018-07-12 22:05:26 +01:00
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nir_channel(&b, color, 0),
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2020-08-15 06:11:27 +01:00
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nir_bcsel(&b, nir_ieq_imm(&b, comp, 1),
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2018-07-12 22:05:26 +01:00
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nir_channel(&b, color, 1),
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nir_channel(&b, color, 2)));
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nir_ssa_def *u = nir_ssa_undef(&b, 1, 32);
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color = nir_vec4(&b, color_component, u, u, u);
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}
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2016-04-01 13:57:54 +01:00
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2016-04-28 01:17:11 +01:00
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nir_variable *frag_color = nir_variable_create(b.shader, nir_var_shader_out,
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glsl_vec4_type(),
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"gl_FragColor");
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frag_color->data.location = FRAG_RESULT_COLOR;
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2018-07-12 22:05:26 +01:00
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nir_store_var(&b, frag_color, color, 0xf);
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2016-04-01 13:57:54 +01:00
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2016-04-28 01:17:11 +01:00
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struct brw_wm_prog_key wm_key;
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brw_blorp_init_wm_prog_key(&wm_key);
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2016-04-01 13:57:54 +01:00
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2016-11-01 21:03:43 +00:00
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struct brw_wm_prog_data prog_data;
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2016-04-28 01:17:11 +01:00
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const unsigned *program =
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2016-10-21 20:09:38 +01:00
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blorp_compile_fs(blorp, mem_ctx, b.shader, &wm_key, use_replicated_data,
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2017-10-22 04:55:45 +01:00
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&prog_data);
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2016-04-01 13:57:54 +01:00
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2017-03-14 12:12:22 +00:00
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bool result =
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2020-03-12 21:27:13 +00:00
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blorp->upload_shader(batch, MESA_SHADER_FRAGMENT,
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&blorp_key, sizeof(blorp_key),
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2017-10-22 04:55:45 +01:00
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program, prog_data.base.program_size,
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2017-03-14 12:12:22 +00:00
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&prog_data.base, sizeof(prog_data),
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¶ms->wm_prog_kernel, ¶ms->wm_prog_data);
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2016-04-01 13:57:54 +01:00
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2016-04-28 01:17:11 +01:00
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ralloc_free(mem_ctx);
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2017-03-14 12:12:22 +00:00
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return result;
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2016-04-22 19:38:23 +01:00
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}
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2019-10-30 14:14:06 +00:00
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#pragma pack(push, 1)
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2016-10-21 22:50:20 +01:00
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struct layer_offset_vs_key {
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enum blorp_shader_type shader_type;
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unsigned num_inputs;
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};
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2019-10-30 14:14:06 +00:00
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#pragma pack(pop)
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2016-10-21 22:50:20 +01:00
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/* In the case of doing attachment clears, we are using a surface state that
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* is handed to us so we can't set (and don't even know) the base array layer.
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* In order to do a layered clear in this scenario, we need some way of adding
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* the base array layer to the instance id. Unfortunately, our hardware has
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* no real concept of "base instance", so we have to do it manually in a
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* vertex shader.
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*/
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2017-03-14 12:12:22 +00:00
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static bool
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2019-01-09 23:15:49 +00:00
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blorp_params_get_layer_offset_vs(struct blorp_batch *batch,
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2016-10-21 22:50:20 +01:00
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struct blorp_params *params)
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{
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2019-01-09 23:15:49 +00:00
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struct blorp_context *blorp = batch->blorp;
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2016-10-21 22:50:20 +01:00
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struct layer_offset_vs_key blorp_key = {
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.shader_type = BLORP_SHADER_TYPE_LAYER_OFFSET_VS,
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};
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if (params->wm_prog_data)
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blorp_key.num_inputs = params->wm_prog_data->num_varying_inputs;
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2019-01-09 23:15:49 +00:00
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if (blorp->lookup_shader(batch, &blorp_key, sizeof(blorp_key),
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2016-10-21 22:50:20 +01:00
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¶ms->vs_prog_kernel, ¶ms->vs_prog_data))
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2017-03-14 12:12:22 +00:00
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return true;
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2016-10-21 22:50:20 +01:00
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void *mem_ctx = ralloc_context(NULL);
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nir_builder b;
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2020-09-29 08:54:07 +01:00
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blorp_nir_init_shader(&b, mem_ctx, MESA_SHADER_VERTEX,
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blorp_shader_type_to_name(blorp_key.shader_type));
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2016-10-21 22:50:20 +01:00
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const struct glsl_type *uvec4_type = glsl_vector_type(GLSL_TYPE_UINT, 4);
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/* First we deal with the header which has instance and base instance */
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nir_variable *a_header = nir_variable_create(b.shader, nir_var_shader_in,
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uvec4_type, "header");
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a_header->data.location = VERT_ATTRIB_GENERIC0;
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nir_variable *v_layer = nir_variable_create(b.shader, nir_var_shader_out,
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glsl_int_type(), "layer_id");
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v_layer->data.location = VARYING_SLOT_LAYER;
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/* Compute the layer id */
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nir_ssa_def *header = nir_load_var(&b, a_header);
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nir_ssa_def *base_layer = nir_channel(&b, header, 0);
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nir_ssa_def *instance = nir_channel(&b, header, 1);
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nir_store_var(&b, v_layer, nir_iadd(&b, instance, base_layer), 0x1);
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/* Then we copy the vertex from the next slot to VARYING_SLOT_POS */
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nir_variable *a_vertex = nir_variable_create(b.shader, nir_var_shader_in,
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glsl_vec4_type(), "a_vertex");
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a_vertex->data.location = VERT_ATTRIB_GENERIC1;
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nir_variable *v_pos = nir_variable_create(b.shader, nir_var_shader_out,
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glsl_vec4_type(), "v_pos");
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v_pos->data.location = VARYING_SLOT_POS;
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nir_copy_var(&b, v_pos, a_vertex);
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/* Then we copy everything else */
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for (unsigned i = 0; i < blorp_key.num_inputs; i++) {
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nir_variable *a_in = nir_variable_create(b.shader, nir_var_shader_in,
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uvec4_type, "input");
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a_in->data.location = VERT_ATTRIB_GENERIC2 + i;
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nir_variable *v_out = nir_variable_create(b.shader, nir_var_shader_out,
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uvec4_type, "output");
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v_out->data.location = VARYING_SLOT_VAR0 + i;
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nir_copy_var(&b, v_out, a_in);
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}
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struct brw_vs_prog_data vs_prog_data;
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memset(&vs_prog_data, 0, sizeof(vs_prog_data));
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const unsigned *program =
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2017-10-22 04:55:45 +01:00
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blorp_compile_vs(blorp, mem_ctx, b.shader, &vs_prog_data);
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2016-10-21 22:50:20 +01:00
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2017-03-14 12:12:22 +00:00
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bool result =
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2020-03-12 21:27:13 +00:00
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blorp->upload_shader(batch, MESA_SHADER_VERTEX,
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&blorp_key, sizeof(blorp_key),
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2017-10-22 04:55:45 +01:00
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program, vs_prog_data.base.base.program_size,
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2017-03-14 12:12:22 +00:00
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&vs_prog_data.base.base, sizeof(vs_prog_data),
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¶ms->vs_prog_kernel, ¶ms->vs_prog_data);
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2016-10-21 22:50:20 +01:00
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ralloc_free(mem_ctx);
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2017-03-14 12:12:22 +00:00
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return result;
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2016-10-21 22:50:20 +01:00
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}
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2016-08-19 11:53:33 +01:00
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/* The x0, y0, x1, and y1 parameters must already be populated with the render
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* area of the framebuffer to be cleared.
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*/
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static void
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get_fast_clear_rect(const struct isl_device *dev,
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const struct isl_surf *aux_surf,
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unsigned *x0, unsigned *y0,
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unsigned *x1, unsigned *y1)
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{
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unsigned int x_align, y_align;
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unsigned int x_scaledown, y_scaledown;
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/* Only single sampled surfaces need to (and actually can) be resolved. */
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if (aux_surf->usage == ISL_SURF_USAGE_CCS_BIT) {
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/* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
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* Target(s)", beneath the "Fast Color Clear" bullet (p327):
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*
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* Clear pass must have a clear rectangle that must follow
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* alignment rules in terms of pixels and lines as shown in the
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* table below. Further, the clear-rectangle height and width
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* must be multiple of the following dimensions. If the height
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* and width of the render target being cleared do not meet these
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* requirements, an MCS buffer can be created such that it
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* follows the requirement and covers the RT.
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*
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* The alignment size in the table that follows is related to the
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* alignment size that is baked into the CCS surface format but with X
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* alignment multiplied by 16 and Y alignment multiplied by 32.
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*/
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x_align = isl_format_get_layout(aux_surf->format)->bw;
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y_align = isl_format_get_layout(aux_surf->format)->bh;
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x_align *= 16;
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2019-05-10 00:38:12 +01:00
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|
|
/* The line alignment requirement for Y-tiled is halved at SKL and again
|
|
|
|
|
* at TGL.
|
2016-08-19 11:53:33 +01:00
|
|
|
|
*/
|
2021-03-29 22:41:58 +01:00
|
|
|
|
if (dev->info->ver >= 12)
|
2019-05-10 00:38:12 +01:00
|
|
|
|
y_align *= 8;
|
2021-03-29 22:41:58 +01:00
|
|
|
|
else if (dev->info->ver >= 9)
|
2016-08-19 11:53:33 +01:00
|
|
|
|
y_align *= 16;
|
|
|
|
|
else
|
|
|
|
|
y_align *= 32;
|
|
|
|
|
|
|
|
|
|
/* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
|
|
|
|
|
* Target(s)", beneath the "Fast Color Clear" bullet (p327):
|
|
|
|
|
*
|
|
|
|
|
* In order to optimize the performance MCS buffer (when bound to
|
|
|
|
|
* 1X RT) clear similarly to MCS buffer clear for MSRT case,
|
|
|
|
|
* clear rect is required to be scaled by the following factors
|
|
|
|
|
* in the horizontal and vertical directions:
|
|
|
|
|
*
|
|
|
|
|
* The X and Y scale down factors in the table that follows are each
|
|
|
|
|
* equal to half the alignment value computed above.
|
|
|
|
|
*/
|
|
|
|
|
x_scaledown = x_align / 2;
|
|
|
|
|
y_scaledown = y_align / 2;
|
|
|
|
|
|
2019-06-07 21:13:30 +01:00
|
|
|
|
if (ISL_DEV_IS_HASWELL(dev)) {
|
|
|
|
|
/* From BSpec: 3D-Media-GPGPU Engine > 3D Pipeline > Pixel > Pixel
|
|
|
|
|
* Backend > MCS Buffer for Render Target(s) [DevIVB+] > Table "Color
|
|
|
|
|
* Clear of Non-MultiSampled Render Target Restrictions":
|
|
|
|
|
*
|
|
|
|
|
* Clear rectangle must be aligned to two times the number of
|
|
|
|
|
* pixels in the table shown below due to 16x16 hashing across the
|
|
|
|
|
* slice.
|
|
|
|
|
*
|
|
|
|
|
* This restriction is only documented to exist on HSW GT3 but
|
|
|
|
|
* empirical evidence suggests that it's also needed GT2.
|
|
|
|
|
*/
|
|
|
|
|
x_align *= 2;
|
|
|
|
|
y_align *= 2;
|
|
|
|
|
}
|
2016-08-19 11:53:33 +01:00
|
|
|
|
} else {
|
|
|
|
|
assert(aux_surf->usage == ISL_SURF_USAGE_MCS_BIT);
|
|
|
|
|
|
|
|
|
|
/* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
|
|
|
|
|
* Target(s)", beneath the "MSAA Compression" bullet (p326):
|
|
|
|
|
*
|
|
|
|
|
* Clear pass for this case requires that scaled down primitive
|
|
|
|
|
* is sent down with upper left co-ordinate to coincide with
|
|
|
|
|
* actual rectangle being cleared. For MSAA, clear rectangle’s
|
|
|
|
|
* height and width need to as show in the following table in
|
|
|
|
|
* terms of (width,height) of the RT.
|
|
|
|
|
*
|
|
|
|
|
* MSAA Width of Clear Rect Height of Clear Rect
|
|
|
|
|
* 2X Ceil(1/8*width) Ceil(1/2*height)
|
|
|
|
|
* 4X Ceil(1/8*width) Ceil(1/2*height)
|
|
|
|
|
* 8X Ceil(1/2*width) Ceil(1/2*height)
|
|
|
|
|
* 16X width Ceil(1/2*height)
|
|
|
|
|
*
|
|
|
|
|
* The text "with upper left co-ordinate to coincide with actual
|
|
|
|
|
* rectangle being cleared" is a little confusing--it seems to imply
|
|
|
|
|
* that to clear a rectangle from (x,y) to (x+w,y+h), one needs to
|
|
|
|
|
* feed the pipeline using the rectangle (x,y) to
|
|
|
|
|
* (x+Ceil(w/N),y+Ceil(h/2)), where N is either 2 or 8 depending on
|
|
|
|
|
* the number of samples. Experiments indicate that this is not
|
|
|
|
|
* quite correct; actually, what the hardware appears to do is to
|
|
|
|
|
* align whatever rectangle is sent down the pipeline to the nearest
|
|
|
|
|
* multiple of 2x2 blocks, and then scale it up by a factor of N
|
|
|
|
|
* horizontally and 2 vertically. So the resulting alignment is 4
|
|
|
|
|
* vertically and either 4 or 16 horizontally, and the scaledown
|
|
|
|
|
* factor is 2 vertically and either 2 or 8 horizontally.
|
|
|
|
|
*/
|
|
|
|
|
switch (aux_surf->format) {
|
|
|
|
|
case ISL_FORMAT_MCS_2X:
|
|
|
|
|
case ISL_FORMAT_MCS_4X:
|
|
|
|
|
x_scaledown = 8;
|
|
|
|
|
break;
|
|
|
|
|
case ISL_FORMAT_MCS_8X:
|
|
|
|
|
x_scaledown = 2;
|
|
|
|
|
break;
|
|
|
|
|
case ISL_FORMAT_MCS_16X:
|
|
|
|
|
x_scaledown = 1;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
unreachable("Unexpected MCS format for fast clear");
|
|
|
|
|
}
|
|
|
|
|
y_scaledown = 2;
|
|
|
|
|
x_align = x_scaledown * 2;
|
|
|
|
|
y_align = y_scaledown * 2;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
*x0 = ROUND_DOWN_TO(*x0, x_align) / x_scaledown;
|
|
|
|
|
*y0 = ROUND_DOWN_TO(*y0, y_align) / y_scaledown;
|
|
|
|
|
*x1 = ALIGN(*x1, x_align) / x_scaledown;
|
|
|
|
|
*y1 = ALIGN(*y1, y_align) / y_scaledown;
|
|
|
|
|
}
|
|
|
|
|
|
2016-08-08 23:25:17 +01:00
|
|
|
|
void
|
2016-08-19 08:54:56 +01:00
|
|
|
|
blorp_fast_clear(struct blorp_batch *batch,
|
2020-03-17 18:36:40 +00:00
|
|
|
|
const struct blorp_surf *surf,
|
|
|
|
|
enum isl_format format, struct isl_swizzle swizzle,
|
2016-08-26 16:44:18 +01:00
|
|
|
|
uint32_t level, uint32_t start_layer, uint32_t num_layers,
|
2016-07-25 22:03:49 +01:00
|
|
|
|
uint32_t x0, uint32_t y0, uint32_t x1, uint32_t y1)
|
|
|
|
|
{
|
2016-08-19 13:43:29 +01:00
|
|
|
|
struct blorp_params params;
|
|
|
|
|
blorp_params_init(¶ms);
|
2016-08-26 16:44:18 +01:00
|
|
|
|
params.num_layers = num_layers;
|
2016-04-22 20:55:49 +01:00
|
|
|
|
|
2016-07-25 22:03:49 +01:00
|
|
|
|
params.x0 = x0;
|
|
|
|
|
params.y0 = y0;
|
|
|
|
|
params.x1 = x1;
|
|
|
|
|
params.y1 = y1;
|
2016-04-22 20:55:49 +01:00
|
|
|
|
|
2016-10-21 22:50:20 +01:00
|
|
|
|
memset(¶ms.wm_inputs.clear_color, 0xff, 4*sizeof(float));
|
2018-01-19 23:02:07 +00:00
|
|
|
|
params.fast_clear_op = ISL_AUX_OP_FAST_CLEAR;
|
2016-07-25 22:03:49 +01:00
|
|
|
|
|
2016-08-19 11:53:33 +01:00
|
|
|
|
get_fast_clear_rect(batch->blorp->isl_dev, surf->aux_surf,
|
|
|
|
|
¶ms.x0, ¶ms.y0, ¶ms.x1, ¶ms.y1);
|
2016-07-25 22:03:49 +01:00
|
|
|
|
|
2019-01-09 23:15:49 +00:00
|
|
|
|
if (!blorp_params_get_clear_kernel(batch, ¶ms, true, false))
|
2017-03-14 12:12:22 +00:00
|
|
|
|
return;
|
2016-04-22 20:55:49 +01:00
|
|
|
|
|
2016-08-26 16:44:18 +01:00
|
|
|
|
brw_blorp_surface_info_init(batch->blorp, ¶ms.dst, surf, level,
|
|
|
|
|
start_layer, format, true);
|
2016-10-21 18:40:58 +01:00
|
|
|
|
params.num_samples = params.dst.surf.samples;
|
2016-07-25 22:03:49 +01:00
|
|
|
|
|
2020-06-30 23:00:13 +01:00
|
|
|
|
assert(params.num_samples != 0);
|
|
|
|
|
if (params.num_samples == 1)
|
|
|
|
|
params.snapshot_type = INTEL_SNAPSHOT_CCS_COLOR_CLEAR;
|
|
|
|
|
else
|
|
|
|
|
params.snapshot_type = INTEL_SNAPSHOT_MCS_COLOR_CLEAR;
|
|
|
|
|
|
2020-03-17 18:36:40 +00:00
|
|
|
|
/* If a swizzle was provided, we need to swizzle the clear color so that
|
|
|
|
|
* the hardware color format conversion will work properly.
|
|
|
|
|
*/
|
2020-03-25 19:35:53 +00:00
|
|
|
|
params.dst.clear_color =
|
|
|
|
|
isl_color_value_swizzle_inv(params.dst.clear_color, swizzle);
|
2020-03-17 18:36:40 +00:00
|
|
|
|
|
2016-08-19 08:54:56 +01:00
|
|
|
|
batch->blorp->exec(batch, ¶ms);
|
2016-07-25 22:03:49 +01:00
|
|
|
|
}
|
|
|
|
|
|
2016-08-08 23:25:17 +01:00
|
|
|
|
void
|
2016-08-19 08:54:56 +01:00
|
|
|
|
blorp_clear(struct blorp_batch *batch,
|
2016-08-19 13:43:29 +01:00
|
|
|
|
const struct blorp_surf *surf,
|
2016-08-31 02:01:27 +01:00
|
|
|
|
enum isl_format format, struct isl_swizzle swizzle,
|
2016-08-26 16:44:18 +01:00
|
|
|
|
uint32_t level, uint32_t start_layer, uint32_t num_layers,
|
2016-07-25 22:03:49 +01:00
|
|
|
|
uint32_t x0, uint32_t y0, uint32_t x1, uint32_t y1,
|
2016-08-31 02:01:27 +01:00
|
|
|
|
union isl_color_value clear_color,
|
2016-08-31 00:55:35 +01:00
|
|
|
|
const bool color_write_disable[4])
|
2016-07-25 22:03:49 +01:00
|
|
|
|
{
|
2016-08-19 13:43:29 +01:00
|
|
|
|
struct blorp_params params;
|
|
|
|
|
blorp_params_init(¶ms);
|
2020-06-30 23:00:13 +01:00
|
|
|
|
params.snapshot_type = INTEL_SNAPSHOT_SLOW_COLOR_CLEAR;
|
2016-07-25 22:03:49 +01:00
|
|
|
|
|
2017-02-08 20:47:01 +00:00
|
|
|
|
/* Manually apply the clear destination swizzle. This way swizzled clears
|
|
|
|
|
* will work for swizzles which we can't normally use for rendering and it
|
|
|
|
|
* also ensures that they work on pre-Haswell hardware which can't swizlle
|
|
|
|
|
* at all.
|
|
|
|
|
*/
|
2020-03-25 19:35:53 +00:00
|
|
|
|
clear_color = isl_color_value_swizzle_inv(clear_color, swizzle);
|
2017-02-08 20:47:01 +00:00
|
|
|
|
swizzle = ISL_SWIZZLE_IDENTITY;
|
|
|
|
|
|
2018-07-12 22:05:26 +01:00
|
|
|
|
bool clear_rgb_as_red = false;
|
2016-08-31 00:32:51 +01:00
|
|
|
|
if (format == ISL_FORMAT_R9G9B9E5_SHAREDEXP) {
|
|
|
|
|
clear_color.u32[0] = float3_to_rgb9e5(clear_color.f32);
|
|
|
|
|
format = ISL_FORMAT_R32_UINT;
|
2017-08-02 23:07:33 +01:00
|
|
|
|
} else if (format == ISL_FORMAT_L8_UNORM_SRGB) {
|
|
|
|
|
clear_color.f32[0] = util_format_linear_to_srgb_float(clear_color.f32[0]);
|
|
|
|
|
format = ISL_FORMAT_R8_UNORM;
|
2017-01-27 20:32:05 +00:00
|
|
|
|
} else if (format == ISL_FORMAT_A4B4G4R4_UNORM) {
|
|
|
|
|
/* Broadwell and earlier cannot render to this format so we need to work
|
|
|
|
|
* around it by swapping the colors around and using B4G4R4A4 instead.
|
|
|
|
|
*/
|
2017-02-08 20:47:01 +00:00
|
|
|
|
const struct isl_swizzle ARGB = ISL_SWIZZLE(ALPHA, RED, GREEN, BLUE);
|
2020-03-25 19:35:53 +00:00
|
|
|
|
clear_color = isl_color_value_swizzle_inv(clear_color, ARGB);
|
2017-01-27 20:32:05 +00:00
|
|
|
|
format = ISL_FORMAT_B4G4R4A4_UNORM;
|
2018-07-12 22:05:26 +01:00
|
|
|
|
} else if (isl_format_get_layout(format)->bpb % 3 == 0) {
|
|
|
|
|
clear_rgb_as_red = true;
|
|
|
|
|
if (format == ISL_FORMAT_R8G8B8_UNORM_SRGB) {
|
|
|
|
|
clear_color.f32[0] = util_format_linear_to_srgb_float(clear_color.f32[0]);
|
|
|
|
|
clear_color.f32[1] = util_format_linear_to_srgb_float(clear_color.f32[1]);
|
|
|
|
|
clear_color.f32[2] = util_format_linear_to_srgb_float(clear_color.f32[2]);
|
|
|
|
|
}
|
2016-08-31 00:32:51 +01:00
|
|
|
|
}
|
|
|
|
|
|
2016-10-21 22:50:20 +01:00
|
|
|
|
memcpy(¶ms.wm_inputs.clear_color, clear_color.f32, sizeof(float) * 4);
|
2016-04-22 20:55:49 +01:00
|
|
|
|
|
2016-04-28 01:18:02 +01:00
|
|
|
|
bool use_simd16_replicated_data = true;
|
2016-04-22 20:55:49 +01:00
|
|
|
|
|
|
|
|
|
/* From the SNB PRM (Vol4_Part1):
|
|
|
|
|
*
|
|
|
|
|
* "Replicated data (Message Type = 111) is only supported when
|
|
|
|
|
* accessing tiled memory. Using this Message Type to access linear
|
|
|
|
|
* (untiled) memory is UNDEFINED."
|
|
|
|
|
*/
|
2016-07-25 22:03:49 +01:00
|
|
|
|
if (surf->surf->tiling == ISL_TILING_LINEAR)
|
2016-04-28 01:18:02 +01:00
|
|
|
|
use_simd16_replicated_data = false;
|
2016-04-22 20:55:49 +01:00
|
|
|
|
|
2021-03-29 23:40:04 +01:00
|
|
|
|
/* Replicated clears don't work yet before gfx6 */
|
2021-03-29 22:41:58 +01:00
|
|
|
|
if (batch->blorp->isl_dev->info->ver < 6)
|
2017-05-13 01:14:18 +01:00
|
|
|
|
use_simd16_replicated_data = false;
|
|
|
|
|
|
2016-04-22 20:55:49 +01:00
|
|
|
|
/* Constant color writes ignore everyting in blend and color calculator
|
|
|
|
|
* state. This is not documented.
|
|
|
|
|
*/
|
2016-08-31 00:55:35 +01:00
|
|
|
|
if (color_write_disable) {
|
|
|
|
|
for (unsigned i = 0; i < 4; i++) {
|
|
|
|
|
params.color_write_disable[i] = color_write_disable[i];
|
|
|
|
|
if (color_write_disable[i])
|
|
|
|
|
use_simd16_replicated_data = false;
|
|
|
|
|
}
|
2016-07-25 22:03:49 +01:00
|
|
|
|
}
|
|
|
|
|
|
2019-01-09 23:15:49 +00:00
|
|
|
|
if (!blorp_params_get_clear_kernel(batch, ¶ms,
|
2018-07-12 22:05:26 +01:00
|
|
|
|
use_simd16_replicated_data,
|
|
|
|
|
clear_rgb_as_red))
|
2017-03-14 12:12:22 +00:00
|
|
|
|
return;
|
2016-07-25 22:03:49 +01:00
|
|
|
|
|
2019-01-09 23:15:49 +00:00
|
|
|
|
if (!blorp_ensure_sf_program(batch, ¶ms))
|
2017-05-13 04:24:46 +01:00
|
|
|
|
return;
|
|
|
|
|
|
2016-09-12 19:46:22 +01:00
|
|
|
|
while (num_layers > 0) {
|
|
|
|
|
brw_blorp_surface_info_init(batch->blorp, ¶ms.dst, surf, level,
|
|
|
|
|
start_layer, format, true);
|
2016-08-31 02:01:27 +01:00
|
|
|
|
params.dst.view.swizzle = swizzle;
|
2016-04-22 20:55:49 +01:00
|
|
|
|
|
2016-09-10 00:30:24 +01:00
|
|
|
|
params.x0 = x0;
|
|
|
|
|
params.y0 = y0;
|
|
|
|
|
params.x1 = x1;
|
|
|
|
|
params.y1 = y1;
|
|
|
|
|
|
2018-05-25 20:27:17 +01:00
|
|
|
|
if (params.dst.tile_x_sa || params.dst.tile_y_sa) {
|
|
|
|
|
assert(params.dst.surf.samples == 1);
|
|
|
|
|
assert(num_layers == 1);
|
|
|
|
|
params.x0 += params.dst.tile_x_sa;
|
|
|
|
|
params.y0 += params.dst.tile_y_sa;
|
|
|
|
|
params.x1 += params.dst.tile_x_sa;
|
|
|
|
|
params.y1 += params.dst.tile_y_sa;
|
|
|
|
|
}
|
|
|
|
|
|
2016-09-10 00:30:24 +01:00
|
|
|
|
/* The MinLOD and MinimumArrayElement don't work properly for cube maps.
|
2021-03-29 23:40:04 +01:00
|
|
|
|
* Convert them to a single slice on gfx4.
|
2016-09-10 00:30:24 +01:00
|
|
|
|
*/
|
2021-03-29 22:41:58 +01:00
|
|
|
|
if (batch->blorp->isl_dev->info->ver == 4 &&
|
2016-09-10 00:30:24 +01:00
|
|
|
|
(params.dst.surf.usage & ISL_SURF_USAGE_CUBE_BIT)) {
|
|
|
|
|
blorp_surf_convert_to_single_slice(batch->blorp->isl_dev, ¶ms.dst);
|
2017-08-10 18:44:15 +01:00
|
|
|
|
}
|
|
|
|
|
|
2018-07-12 22:05:26 +01:00
|
|
|
|
if (clear_rgb_as_red) {
|
|
|
|
|
surf_fake_rgb_with_red(batch->blorp->isl_dev, ¶ms.dst);
|
|
|
|
|
params.x0 *= 3;
|
|
|
|
|
params.x1 *= 3;
|
|
|
|
|
}
|
|
|
|
|
|
2017-08-10 18:44:15 +01:00
|
|
|
|
if (isl_format_is_compressed(params.dst.surf.format)) {
|
|
|
|
|
blorp_surf_convert_to_uncompressed(batch->blorp->isl_dev, ¶ms.dst,
|
|
|
|
|
NULL, NULL, NULL, NULL);
|
|
|
|
|
//&dst_x, &dst_y, &dst_w, &dst_h);
|
|
|
|
|
}
|
2016-09-10 00:30:24 +01:00
|
|
|
|
|
2017-08-10 18:44:15 +01:00
|
|
|
|
if (params.dst.tile_x_sa || params.dst.tile_y_sa) {
|
2021-03-29 23:40:04 +01:00
|
|
|
|
/* Either we're on gfx4 where there is no multisampling or the
|
2017-08-10 18:44:15 +01:00
|
|
|
|
* surface is compressed which also implies no multisampling.
|
|
|
|
|
* Therefore, sa == px and we don't need to do a conversion.
|
|
|
|
|
*/
|
|
|
|
|
assert(params.dst.surf.samples == 1);
|
|
|
|
|
params.x0 += params.dst.tile_x_sa;
|
|
|
|
|
params.y0 += params.dst.tile_y_sa;
|
|
|
|
|
params.x1 += params.dst.tile_x_sa;
|
|
|
|
|
params.y1 += params.dst.tile_y_sa;
|
2016-09-10 00:30:24 +01:00
|
|
|
|
}
|
|
|
|
|
|
2016-10-21 18:40:58 +01:00
|
|
|
|
params.num_samples = params.dst.surf.samples;
|
|
|
|
|
|
2016-09-12 19:46:22 +01:00
|
|
|
|
/* We may be restricted on the number of layers we can bind at any one
|
|
|
|
|
* time. In particular, Sandy Bridge has a maximum number of layers of
|
|
|
|
|
* 512 but a maximum 3D texture size is much larger.
|
|
|
|
|
*/
|
|
|
|
|
params.num_layers = MIN2(params.dst.view.array_len, num_layers);
|
2018-07-12 22:05:26 +01:00
|
|
|
|
|
|
|
|
|
const unsigned max_image_width = 16 * 1024;
|
|
|
|
|
if (params.dst.surf.logical_level0_px.width > max_image_width) {
|
|
|
|
|
/* Clearing an RGB image as red multiplies the surface width by 3
|
|
|
|
|
* so it may now be too wide for the hardware surface limits. We
|
|
|
|
|
* have to break the clear up into pieces in order to clear wide
|
|
|
|
|
* images.
|
|
|
|
|
*/
|
|
|
|
|
assert(clear_rgb_as_red);
|
|
|
|
|
assert(params.dst.surf.dim == ISL_SURF_DIM_2D);
|
|
|
|
|
assert(params.dst.surf.tiling == ISL_TILING_LINEAR);
|
|
|
|
|
assert(params.dst.surf.logical_level0_px.depth == 1);
|
|
|
|
|
assert(params.dst.surf.logical_level0_px.array_len == 1);
|
|
|
|
|
assert(params.dst.surf.levels == 1);
|
|
|
|
|
assert(params.dst.surf.samples == 1);
|
|
|
|
|
assert(params.dst.tile_x_sa == 0 || params.dst.tile_y_sa == 0);
|
|
|
|
|
assert(params.dst.aux_usage == ISL_AUX_USAGE_NONE);
|
|
|
|
|
|
|
|
|
|
/* max_image_width rounded down to a multiple of 3 */
|
|
|
|
|
const unsigned max_fake_rgb_width = (max_image_width / 3) * 3;
|
|
|
|
|
const unsigned cpp =
|
|
|
|
|
isl_format_get_layout(params.dst.surf.format)->bpb / 8;
|
|
|
|
|
|
|
|
|
|
params.dst.surf.logical_level0_px.width = max_fake_rgb_width;
|
|
|
|
|
params.dst.surf.phys_level0_sa.width = max_fake_rgb_width;
|
|
|
|
|
|
|
|
|
|
uint32_t orig_x0 = params.x0, orig_x1 = params.x1;
|
|
|
|
|
uint64_t orig_offset = params.dst.addr.offset;
|
|
|
|
|
for (uint32_t x = orig_x0; x < orig_x1; x += max_fake_rgb_width) {
|
|
|
|
|
/* Offset to the surface. It's easy because we're linear */
|
|
|
|
|
params.dst.addr.offset = orig_offset + x * cpp;
|
|
|
|
|
|
|
|
|
|
params.x0 = 0;
|
|
|
|
|
params.x1 = MIN2(orig_x1 - x, max_image_width);
|
|
|
|
|
|
|
|
|
|
batch->blorp->exec(batch, ¶ms);
|
|
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
batch->blorp->exec(batch, ¶ms);
|
|
|
|
|
}
|
2016-09-12 19:46:22 +01:00
|
|
|
|
|
|
|
|
|
start_layer += params.num_layers;
|
|
|
|
|
num_layers -= params.num_layers;
|
|
|
|
|
}
|
2016-07-25 22:03:49 +01:00
|
|
|
|
}
|
|
|
|
|
|
2018-02-03 17:12:15 +00:00
|
|
|
|
static bool
|
|
|
|
|
blorp_clear_stencil_as_rgba(struct blorp_batch *batch,
|
|
|
|
|
const struct blorp_surf *surf,
|
|
|
|
|
uint32_t level, uint32_t start_layer,
|
|
|
|
|
uint32_t num_layers,
|
|
|
|
|
uint32_t x0, uint32_t y0, uint32_t x1, uint32_t y1,
|
|
|
|
|
uint8_t stencil_mask, uint8_t stencil_value)
|
|
|
|
|
{
|
|
|
|
|
/* We only support separate W-tiled stencil for now */
|
|
|
|
|
if (surf->surf->format != ISL_FORMAT_R8_UINT ||
|
|
|
|
|
surf->surf->tiling != ISL_TILING_W)
|
|
|
|
|
return false;
|
|
|
|
|
|
|
|
|
|
/* Stencil mask support would require piles of shader magic */
|
|
|
|
|
if (stencil_mask != 0xff)
|
|
|
|
|
return false;
|
|
|
|
|
|
|
|
|
|
if (surf->surf->samples > 1) {
|
|
|
|
|
/* Adjust x0, y0, x1, and y1 to be in units of samples */
|
|
|
|
|
assert(surf->surf->msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED);
|
|
|
|
|
struct isl_extent2d msaa_px_size_sa =
|
|
|
|
|
isl_get_interleaved_msaa_px_size_sa(surf->surf->samples);
|
|
|
|
|
|
|
|
|
|
x0 *= msaa_px_size_sa.w;
|
|
|
|
|
y0 *= msaa_px_size_sa.h;
|
|
|
|
|
x1 *= msaa_px_size_sa.w;
|
|
|
|
|
y1 *= msaa_px_size_sa.h;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* W-tiles and Y-tiles have the same layout as far as cache lines are
|
|
|
|
|
* concerned: both are 8x8 cache lines laid out Y-major. The difference is
|
|
|
|
|
* entirely in how the data is arranged withing the cache line. W-tiling
|
|
|
|
|
* is 8x8 pixels in a swizzled pattern while Y-tiling is 16B by 4 rows
|
|
|
|
|
* regardless of image format size. As long as everything is aligned to 8,
|
|
|
|
|
* we can just treat the W-tiled image as Y-tiled, ignore the layout
|
|
|
|
|
* difference within a cache line, and blast out data.
|
|
|
|
|
*/
|
|
|
|
|
if (x0 % 8 != 0 || y0 % 8 != 0 || x1 % 8 != 0 || y1 % 8 != 0)
|
|
|
|
|
return false;
|
|
|
|
|
|
|
|
|
|
struct blorp_params params;
|
|
|
|
|
blorp_params_init(¶ms);
|
2020-06-30 23:00:13 +01:00
|
|
|
|
params.snapshot_type = INTEL_SNAPSHOT_SLOW_DEPTH_CLEAR;
|
2018-02-03 17:12:15 +00:00
|
|
|
|
|
|
|
|
|
if (!blorp_params_get_clear_kernel(batch, ¶ms, true, false))
|
|
|
|
|
return false;
|
|
|
|
|
|
|
|
|
|
memset(¶ms.wm_inputs.clear_color, stencil_value,
|
|
|
|
|
sizeof(params.wm_inputs.clear_color));
|
|
|
|
|
|
|
|
|
|
/* The Sandy Bridge PRM Vol. 4 Pt. 2, section 2.11.2.1.1 has the
|
|
|
|
|
* following footnote to the format table:
|
|
|
|
|
*
|
|
|
|
|
* 128 BPE Formats cannot be Tiled Y when used as render targets
|
|
|
|
|
*
|
|
|
|
|
* We have to use RGBA16_UINT on SNB.
|
|
|
|
|
*/
|
|
|
|
|
enum isl_format wide_format;
|
2021-03-29 21:17:58 +01:00
|
|
|
|
if (ISL_GFX_VER(batch->blorp->isl_dev) <= 6) {
|
2018-02-03 17:12:15 +00:00
|
|
|
|
wide_format = ISL_FORMAT_R16G16B16A16_UINT;
|
|
|
|
|
|
|
|
|
|
/* For RGBA16_UINT, we need to mask the stencil value otherwise, we risk
|
|
|
|
|
* clamping giving us the wrong values
|
|
|
|
|
*/
|
|
|
|
|
for (unsigned i = 0; i < 4; i++)
|
|
|
|
|
params.wm_inputs.clear_color[i] &= 0xffff;
|
|
|
|
|
} else {
|
|
|
|
|
wide_format = ISL_FORMAT_R32G32B32A32_UINT;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
for (uint32_t a = 0; a < num_layers; a++) {
|
|
|
|
|
uint32_t layer = start_layer + a;
|
|
|
|
|
|
|
|
|
|
brw_blorp_surface_info_init(batch->blorp, ¶ms.dst, surf, level,
|
|
|
|
|
layer, ISL_FORMAT_UNSUPPORTED, true);
|
|
|
|
|
|
|
|
|
|
if (surf->surf->samples > 1)
|
|
|
|
|
blorp_surf_fake_interleaved_msaa(batch->blorp->isl_dev, ¶ms.dst);
|
|
|
|
|
|
|
|
|
|
/* Make it Y-tiled */
|
|
|
|
|
blorp_surf_retile_w_to_y(batch->blorp->isl_dev, ¶ms.dst);
|
|
|
|
|
|
|
|
|
|
unsigned wide_Bpp =
|
|
|
|
|
isl_format_get_layout(wide_format)->bpb / 8;
|
|
|
|
|
|
|
|
|
|
params.dst.view.format = params.dst.surf.format = wide_format;
|
|
|
|
|
assert(params.dst.surf.logical_level0_px.width % wide_Bpp == 0);
|
|
|
|
|
params.dst.surf.logical_level0_px.width /= wide_Bpp;
|
|
|
|
|
assert(params.dst.tile_x_sa % wide_Bpp == 0);
|
|
|
|
|
params.dst.tile_x_sa /= wide_Bpp;
|
|
|
|
|
|
|
|
|
|
params.x0 = params.dst.tile_x_sa + x0 / (wide_Bpp / 2);
|
|
|
|
|
params.y0 = params.dst.tile_y_sa + y0 / 2;
|
|
|
|
|
params.x1 = params.dst.tile_x_sa + x1 / (wide_Bpp / 2);
|
|
|
|
|
params.y1 = params.dst.tile_y_sa + y1 / 2;
|
|
|
|
|
|
|
|
|
|
batch->blorp->exec(batch, ¶ms);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
|
2016-10-07 07:20:12 +01:00
|
|
|
|
void
|
|
|
|
|
blorp_clear_depth_stencil(struct blorp_batch *batch,
|
|
|
|
|
const struct blorp_surf *depth,
|
|
|
|
|
const struct blorp_surf *stencil,
|
|
|
|
|
uint32_t level, uint32_t start_layer,
|
|
|
|
|
uint32_t num_layers,
|
|
|
|
|
uint32_t x0, uint32_t y0, uint32_t x1, uint32_t y1,
|
|
|
|
|
bool clear_depth, float depth_value,
|
|
|
|
|
uint8_t stencil_mask, uint8_t stencil_value)
|
|
|
|
|
{
|
2018-02-03 17:12:15 +00:00
|
|
|
|
if (!clear_depth && blorp_clear_stencil_as_rgba(batch, stencil, level,
|
|
|
|
|
start_layer, num_layers,
|
|
|
|
|
x0, y0, x1, y1,
|
|
|
|
|
stencil_mask,
|
|
|
|
|
stencil_value))
|
|
|
|
|
return;
|
|
|
|
|
|
2016-10-07 07:20:12 +01:00
|
|
|
|
struct blorp_params params;
|
|
|
|
|
blorp_params_init(¶ms);
|
2020-06-30 23:00:13 +01:00
|
|
|
|
params.snapshot_type = INTEL_SNAPSHOT_SLOW_DEPTH_CLEAR;
|
2016-10-07 07:20:12 +01:00
|
|
|
|
|
|
|
|
|
params.x0 = x0;
|
|
|
|
|
params.y0 = y0;
|
|
|
|
|
params.x1 = x1;
|
|
|
|
|
params.y1 = y1;
|
|
|
|
|
|
2021-03-29 21:17:58 +01:00
|
|
|
|
if (ISL_GFX_VER(batch->blorp->isl_dev) == 6) {
|
2017-06-08 17:36:15 +01:00
|
|
|
|
/* For some reason, Sandy Bridge gets occlusion queries wrong if we
|
|
|
|
|
* don't have a shader. In particular, it records samples even though
|
|
|
|
|
* we disable statistics in 3DSTATE_WM. Give it the usual clear shader
|
|
|
|
|
* to work around the issue.
|
|
|
|
|
*/
|
2019-01-09 23:15:49 +00:00
|
|
|
|
if (!blorp_params_get_clear_kernel(batch, ¶ms, false, false))
|
2017-06-08 17:36:15 +01:00
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2016-10-07 07:20:12 +01:00
|
|
|
|
while (num_layers > 0) {
|
|
|
|
|
params.num_layers = num_layers;
|
|
|
|
|
|
|
|
|
|
if (stencil_mask) {
|
|
|
|
|
brw_blorp_surface_info_init(batch->blorp, ¶ms.stencil, stencil,
|
|
|
|
|
level, start_layer,
|
|
|
|
|
ISL_FORMAT_UNSUPPORTED, true);
|
|
|
|
|
params.stencil_mask = stencil_mask;
|
|
|
|
|
params.stencil_ref = stencil_value;
|
|
|
|
|
|
|
|
|
|
params.dst.surf.samples = params.stencil.surf.samples;
|
|
|
|
|
params.dst.surf.logical_level0_px =
|
|
|
|
|
params.stencil.surf.logical_level0_px;
|
2019-08-14 21:58:33 +01:00
|
|
|
|
params.dst.view = params.stencil.view;
|
2016-10-07 07:20:12 +01:00
|
|
|
|
|
2016-10-21 18:40:58 +01:00
|
|
|
|
params.num_samples = params.stencil.surf.samples;
|
|
|
|
|
|
2016-10-07 07:20:12 +01:00
|
|
|
|
/* We may be restricted on the number of layers we can bind at any
|
|
|
|
|
* one time. In particular, Sandy Bridge has a maximum number of
|
|
|
|
|
* layers of 512 but a maximum 3D texture size is much larger.
|
|
|
|
|
*/
|
|
|
|
|
if (params.stencil.view.array_len < params.num_layers)
|
|
|
|
|
params.num_layers = params.stencil.view.array_len;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (clear_depth) {
|
|
|
|
|
brw_blorp_surface_info_init(batch->blorp, ¶ms.depth, depth,
|
|
|
|
|
level, start_layer,
|
|
|
|
|
ISL_FORMAT_UNSUPPORTED, true);
|
|
|
|
|
params.z = depth_value;
|
|
|
|
|
params.depth_format =
|
|
|
|
|
isl_format_get_depth_format(depth->surf->format, false);
|
|
|
|
|
|
|
|
|
|
params.dst.surf.samples = params.depth.surf.samples;
|
|
|
|
|
params.dst.surf.logical_level0_px =
|
|
|
|
|
params.depth.surf.logical_level0_px;
|
|
|
|
|
params.dst.view = params.depth.view;
|
|
|
|
|
|
2016-10-21 18:40:58 +01:00
|
|
|
|
params.num_samples = params.depth.surf.samples;
|
|
|
|
|
|
2016-10-07 07:20:12 +01:00
|
|
|
|
/* We may be restricted on the number of layers we can bind at any
|
|
|
|
|
* one time. In particular, Sandy Bridge has a maximum number of
|
|
|
|
|
* layers of 512 but a maximum 3D texture size is much larger.
|
|
|
|
|
*/
|
|
|
|
|
if (params.depth.view.array_len < params.num_layers)
|
|
|
|
|
params.num_layers = params.depth.view.array_len;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
batch->blorp->exec(batch, ¶ms);
|
|
|
|
|
|
|
|
|
|
start_layer += params.num_layers;
|
|
|
|
|
num_layers -= params.num_layers;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2017-01-11 00:17:26 +00:00
|
|
|
|
bool
|
2021-04-05 21:19:39 +01:00
|
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blorp_can_hiz_clear_depth(const struct intel_device_info *devinfo,
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2019-10-07 23:48:33 +01:00
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const struct isl_surf *surf,
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enum isl_aux_usage aux_usage,
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uint32_t level, uint32_t layer,
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2017-01-11 00:17:26 +00:00
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uint32_t x0, uint32_t y0, uint32_t x1, uint32_t y1)
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{
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2021-03-29 23:40:04 +01:00
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/* This function currently doesn't support any gen prior to gfx8 */
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2021-03-29 22:41:58 +01:00
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assert(devinfo->ver >= 8);
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2017-01-11 00:17:26 +00:00
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2021-03-29 22:41:58 +01:00
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if (devinfo->ver == 8 && surf->format == ISL_FORMAT_R16_UNORM) {
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2017-01-11 00:17:26 +00:00
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/* Apply the D16 alignment restrictions. On BDW, HiZ has an 8x4 sample
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* block with the following property: as the number of samples increases,
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* the number of pixels representable by this block decreases by a factor
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* of the sample dimensions. Sample dimensions scale following the MSAA
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* interleaved pattern.
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*
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* Sample|Sample|Pixel
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* Count |Dim |Dim
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* ===================
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* 1 | 1x1 | 8x4
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* 2 | 2x1 | 4x4
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* 4 | 2x2 | 4x2
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* 8 | 4x2 | 2x2
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* 16 | 4x4 | 2x1
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*
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* Table: Pixel Dimensions in a HiZ Sample Block Pre-SKL
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*/
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const struct isl_extent2d sa_block_dim =
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2019-10-07 23:48:33 +01:00
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isl_get_interleaved_msaa_px_size_sa(surf->samples);
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2017-01-11 00:17:26 +00:00
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const uint8_t align_px_w = 8 / sa_block_dim.w;
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const uint8_t align_px_h = 4 / sa_block_dim.h;
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/* Fast depth clears clear an entire sample block at a time. As a result,
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* the rectangle must be aligned to the dimensions of the encompassing
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* pixel block for a successful operation.
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*
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* Fast clears can still work if the upper-left corner is aligned and the
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* bottom-rigtht corner touches the edge of a depth buffer whose extent
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* is unaligned. This is because each miplevel in the depth buffer is
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* padded by the Pixel Dim (similar to a standard compressed texture).
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* In this case, the clear rectangle could be padded by to match the full
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* depth buffer extent but to support multiple clearing techniques, we
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* chose to be unaware of the depth buffer's extent and thus don't handle
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* this case.
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*/
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if (x0 % align_px_w || y0 % align_px_h ||
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x1 % align_px_w || y1 % align_px_h)
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return false;
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2020-03-04 04:20:26 +00:00
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} else if (aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT) {
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2019-10-07 23:53:44 +01:00
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/* We have to set the WM_HZ_OP::FullSurfaceDepthandStencilClear bit
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* whenever we clear an uninitialized HIZ buffer (as some drivers
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* currently do). However, this bit seems liable to clear 16x8 pixels in
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2021-03-29 23:46:12 +01:00
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* the ZCS on Gfx12 - greater than the slice alignments for depth
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2019-10-07 23:53:44 +01:00
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* buffers.
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*/
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assert(surf->image_alignment_el.w % 16 != 0 ||
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surf->image_alignment_el.h % 8 != 0);
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/* This is the hypothesis behind some corruption that was seen with the
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* amd_vertex_shader_layer-layered-depth-texture-render piglit test.
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*
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* From the Compressed Depth Buffers section of the Bspec, under the
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2021-03-29 23:46:12 +01:00
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* Gfx12 texture performant and ZCS columns:
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2019-10-07 23:53:44 +01:00
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*
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* Update with clear at either 16x8 or 8x4 granularity, based on
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* fs_clr or otherwise.
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*
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* There are a number of ways to avoid full surface CCS clears that
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* overlap other slices, but for now we choose to disable fast-clears
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* when an initializing clear could hit another miplevel.
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*
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* NOTE: Because the CCS compresses the depth buffer and not a version
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2021-03-29 23:46:12 +01:00
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* of it that has been rearranged with different alignments (like Gfx8+
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2019-10-07 23:53:44 +01:00
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* HIZ), we have to make sure that the x0 and y0 are at least 16x8
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* aligned in the context of the entire surface.
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*/
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uint32_t slice_x0, slice_y0;
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isl_surf_get_image_offset_el(surf, level,
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surf->dim == ISL_SURF_DIM_3D ? 0 : layer,
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surf->dim == ISL_SURF_DIM_3D ? layer: 0,
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&slice_x0, &slice_y0);
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const bool max_x1_y1 =
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2020-09-08 15:34:50 +01:00
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x1 == minify(surf->logical_level0_px.width, level) &&
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2019-10-07 23:53:44 +01:00
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y1 == minify(surf->logical_level0_px.height, level);
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const uint32_t haligned_x1 = ALIGN(x1, surf->image_alignment_el.w);
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const uint32_t valigned_y1 = ALIGN(y1, surf->image_alignment_el.h);
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const bool unaligned = (slice_x0 + x0) % 16 || (slice_y0 + y0) % 8 ||
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2020-09-08 15:33:59 +01:00
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(max_x1_y1 ? haligned_x1 % 16 || valigned_y1 % 8 :
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x1 % 16 || y1 % 8);
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2020-09-24 18:01:11 +01:00
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const bool partial_clear = x0 > 0 || y0 > 0 || !max_x1_y1;
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const bool multislice_surf = surf->levels > 1 ||
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surf->logical_level0_px.depth > 1 ||
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surf->logical_level0_px.array_len > 1;
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2019-10-07 23:53:44 +01:00
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2020-09-24 18:01:11 +01:00
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if (unaligned && (partial_clear || multislice_surf))
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2019-10-07 23:53:44 +01:00
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return false;
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2017-01-11 00:17:26 +00:00
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}
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2019-10-07 23:48:33 +01:00
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return isl_aux_usage_has_hiz(aux_usage);
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2017-01-11 00:17:26 +00:00
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}
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2020-09-25 02:09:38 +01:00
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static bool
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blorp_can_clear_full_surface(const struct blorp_surf *depth,
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const struct blorp_surf *stencil,
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uint32_t level,
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uint32_t x0, uint32_t y0,
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uint32_t x1, uint32_t y1,
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bool clear_depth,
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bool clear_stencil)
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{
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uint32_t width = 0, height = 0;
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if (clear_stencil) {
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width = minify(stencil->surf->logical_level0_px.width, level);
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height = minify(stencil->surf->logical_level0_px.height, level);
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}
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if (clear_depth && !(width || height)) {
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width = minify(depth->surf->logical_level0_px.width, level);
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height = minify(depth->surf->logical_level0_px.height, level);
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}
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return x0 == 0 && y0 == 0 && width == x1 && height == y1;
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}
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2017-11-21 22:00:44 +00:00
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void
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blorp_hiz_clear_depth_stencil(struct blorp_batch *batch,
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const struct blorp_surf *depth,
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const struct blorp_surf *stencil,
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uint32_t level,
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uint32_t start_layer, uint32_t num_layers,
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uint32_t x0, uint32_t y0,
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uint32_t x1, uint32_t y1,
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bool clear_depth, float depth_value,
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bool clear_stencil, uint8_t stencil_value)
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{
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struct blorp_params params;
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blorp_params_init(¶ms);
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2020-06-30 23:00:13 +01:00
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params.snapshot_type = INTEL_SNAPSHOT_HIZ_CLEAR;
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2017-11-21 22:00:44 +00:00
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2021-03-29 23:40:04 +01:00
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/* This requires WM_HZ_OP which only exists on gfx8+ */
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2021-03-29 21:17:58 +01:00
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assert(ISL_GFX_VER(batch->blorp->isl_dev) >= 8);
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2017-11-21 22:00:44 +00:00
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params.hiz_op = ISL_AUX_OP_FAST_CLEAR;
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2020-09-25 02:09:38 +01:00
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/* From BSpec: 3DSTATE_WM_HZ_OP_BODY >> Full Surface Depth and Stencil Clear
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*
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* "Software must set this only when the APP requires the entire Depth
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* surface to be cleared."
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*/
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params.full_surface_hiz_op =
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blorp_can_clear_full_surface(depth, stencil, level, x0, y0, x1, y1,
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clear_depth, clear_stencil);
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2017-11-21 22:00:44 +00:00
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params.num_layers = 1;
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params.x0 = x0;
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params.y0 = y0;
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params.x1 = x1;
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params.y1 = y1;
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for (uint32_t l = 0; l < num_layers; l++) {
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const uint32_t layer = start_layer + l;
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if (clear_stencil) {
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brw_blorp_surface_info_init(batch->blorp, ¶ms.stencil, stencil,
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level, layer,
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ISL_FORMAT_UNSUPPORTED, true);
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params.stencil_mask = 0xff;
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params.stencil_ref = stencil_value;
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params.num_samples = params.stencil.surf.samples;
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}
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if (clear_depth) {
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/* If we're clearing depth, we must have HiZ */
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2020-03-07 02:15:08 +00:00
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assert(depth && isl_aux_usage_has_hiz(depth->aux_usage));
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2017-11-21 22:00:44 +00:00
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brw_blorp_surface_info_init(batch->blorp, ¶ms.depth, depth,
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level, layer,
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ISL_FORMAT_UNSUPPORTED, true);
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params.depth.clear_color.f32[0] = depth_value;
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params.depth_format =
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isl_format_get_depth_format(depth->surf->format, false);
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params.num_samples = params.depth.surf.samples;
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}
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batch->blorp->exec(batch, ¶ms);
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}
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}
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2017-01-11 00:17:26 +00:00
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/* Given a depth stencil attachment, this function performs a fast depth clear
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* on a depth portion and a regular clear on the stencil portion. When
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* performing a fast depth clear on the depth portion, the HiZ buffer is simply
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* tagged as cleared so the depth clear value is not actually needed.
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*/
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void
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2021-03-29 23:40:04 +01:00
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blorp_gfx8_hiz_clear_attachments(struct blorp_batch *batch,
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2017-01-11 00:17:26 +00:00
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uint32_t num_samples,
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uint32_t x0, uint32_t y0,
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uint32_t x1, uint32_t y1,
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bool clear_depth, bool clear_stencil,
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uint8_t stencil_value)
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{
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assert(batch->flags & BLORP_BATCH_NO_EMIT_DEPTH_STENCIL);
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struct blorp_params params;
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blorp_params_init(¶ms);
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2020-06-30 23:00:13 +01:00
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params.snapshot_type = INTEL_SNAPSHOT_HIZ_CLEAR;
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2017-01-11 00:17:26 +00:00
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params.num_layers = 1;
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2018-01-19 23:14:37 +00:00
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params.hiz_op = ISL_AUX_OP_FAST_CLEAR;
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2017-01-11 00:17:26 +00:00
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params.x0 = x0;
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params.y0 = y0;
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params.x1 = x1;
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params.y1 = y1;
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params.num_samples = num_samples;
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params.depth.enabled = clear_depth;
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params.stencil.enabled = clear_stencil;
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params.stencil_ref = stencil_value;
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batch->blorp->exec(batch, ¶ms);
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}
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2016-10-21 22:50:20 +01:00
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/** Clear active color/depth/stencili attachments
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*
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* This function performs a clear operation on the currently bound
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* color/depth/stencil attachments. It is assumed that any information passed
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* in here is valid, consistent, and in-bounds relative to the currently
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* attached depth/stencil. The binding_table_offset parameter is the 32-bit
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* offset relative to surface state base address where pre-baked binding table
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* that we are to use lives. If clear_color is false, binding_table_offset
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* must point to a binding table with one entry which is a valid null surface
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* that matches the currently bound depth and stencil.
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*/
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void
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blorp_clear_attachments(struct blorp_batch *batch,
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uint32_t binding_table_offset,
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enum isl_format depth_format,
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uint32_t num_samples,
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uint32_t start_layer, uint32_t num_layers,
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uint32_t x0, uint32_t y0, uint32_t x1, uint32_t y1,
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bool clear_color, union isl_color_value color_value,
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bool clear_depth, float depth_value,
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uint8_t stencil_mask, uint8_t stencil_value)
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{
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struct blorp_params params;
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blorp_params_init(¶ms);
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assert(batch->flags & BLORP_BATCH_NO_EMIT_DEPTH_STENCIL);
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params.x0 = x0;
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params.y0 = y0;
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params.x1 = x1;
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params.y1 = y1;
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params.use_pre_baked_binding_table = true;
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params.pre_baked_binding_table_offset = binding_table_offset;
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params.num_layers = num_layers;
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params.num_samples = num_samples;
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if (clear_color) {
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params.dst.enabled = true;
|
2020-06-30 23:00:13 +01:00
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params.snapshot_type = INTEL_SNAPSHOT_SLOW_COLOR_CLEAR;
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2016-10-21 22:50:20 +01:00
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memcpy(¶ms.wm_inputs.clear_color, color_value.f32, sizeof(float) * 4);
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/* Unfortunately, without knowing whether or not our destination surface
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* is tiled or not, we have to assume it may be linear. This means no
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* SIMD16_REPDATA for us. :-(
|
|
|
|
|
*/
|
2019-01-09 23:15:49 +00:00
|
|
|
|
if (!blorp_params_get_clear_kernel(batch, ¶ms, false, false))
|
2017-03-14 12:12:22 +00:00
|
|
|
|
return;
|
2016-10-21 22:50:20 +01:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (clear_depth) {
|
|
|
|
|
params.depth.enabled = true;
|
2020-06-30 23:00:13 +01:00
|
|
|
|
params.snapshot_type = INTEL_SNAPSHOT_SLOW_DEPTH_CLEAR;
|
2016-10-21 22:50:20 +01:00
|
|
|
|
|
|
|
|
|
params.z = depth_value;
|
|
|
|
|
params.depth_format = isl_format_get_depth_format(depth_format, false);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (stencil_mask) {
|
|
|
|
|
params.stencil.enabled = true;
|
2020-06-30 23:00:13 +01:00
|
|
|
|
params.snapshot_type = INTEL_SNAPSHOT_SLOW_DEPTH_CLEAR;
|
2016-10-21 22:50:20 +01:00
|
|
|
|
|
|
|
|
|
params.stencil_mask = stencil_mask;
|
|
|
|
|
params.stencil_ref = stencil_value;
|
|
|
|
|
}
|
|
|
|
|
|
2019-01-09 23:15:49 +00:00
|
|
|
|
if (!blorp_params_get_layer_offset_vs(batch, ¶ms))
|
2017-03-14 12:12:22 +00:00
|
|
|
|
return;
|
|
|
|
|
|
2016-10-21 22:50:20 +01:00
|
|
|
|
params.vs_inputs.base_layer = start_layer;
|
|
|
|
|
|
|
|
|
|
batch->blorp->exec(batch, ¶ms);
|
|
|
|
|
}
|
|
|
|
|
|
2017-11-11 20:31:54 +00:00
|
|
|
|
void
|
|
|
|
|
blorp_ccs_resolve(struct blorp_batch *batch,
|
|
|
|
|
struct blorp_surf *surf, uint32_t level,
|
|
|
|
|
uint32_t start_layer, uint32_t num_layers,
|
|
|
|
|
enum isl_format format,
|
2018-01-19 23:02:07 +00:00
|
|
|
|
enum isl_aux_op resolve_op)
|
2016-04-01 13:57:54 +01:00
|
|
|
|
{
|
2017-11-11 20:31:54 +00:00
|
|
|
|
struct blorp_params params;
|
|
|
|
|
|
|
|
|
|
blorp_params_init(¶ms);
|
2020-06-30 23:00:13 +01:00
|
|
|
|
switch(resolve_op) {
|
|
|
|
|
case ISL_AUX_OP_AMBIGUATE:
|
|
|
|
|
params.snapshot_type = INTEL_SNAPSHOT_CCS_AMBIGUATE;
|
|
|
|
|
break;
|
|
|
|
|
case ISL_AUX_OP_FULL_RESOLVE:
|
|
|
|
|
params.snapshot_type = INTEL_SNAPSHOT_CCS_RESOLVE;
|
|
|
|
|
break;
|
|
|
|
|
case ISL_AUX_OP_PARTIAL_RESOLVE:
|
|
|
|
|
params.snapshot_type = INTEL_SNAPSHOT_CCS_PARTIAL_RESOLVE;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
assert(false);
|
|
|
|
|
}
|
2017-11-11 20:31:54 +00:00
|
|
|
|
brw_blorp_surface_info_init(batch->blorp, ¶ms.dst, surf,
|
|
|
|
|
level, start_layer, format, true);
|
2016-04-22 20:55:49 +01:00
|
|
|
|
|
2016-08-19 11:49:45 +01:00
|
|
|
|
/* From the Ivy Bridge PRM, Vol2 Part1 11.9 "Render Target Resolve":
|
|
|
|
|
*
|
|
|
|
|
* A rectangle primitive must be scaled down by the following factors
|
|
|
|
|
* with respect to render target being resolved.
|
|
|
|
|
*
|
|
|
|
|
* The scaledown factors in the table that follows are related to the block
|
|
|
|
|
* size of the CCS format. For IVB and HSW, we divide by two, for BDW we
|
|
|
|
|
* multiply by 8 and 16. On Sky Lake, we multiply by 8.
|
|
|
|
|
*/
|
|
|
|
|
const struct isl_format_layout *aux_fmtl =
|
2017-11-11 20:31:54 +00:00
|
|
|
|
isl_format_get_layout(params.dst.aux_surf.format);
|
2016-08-19 11:49:45 +01:00
|
|
|
|
assert(aux_fmtl->txc == ISL_TXC_CCS);
|
|
|
|
|
|
|
|
|
|
unsigned x_scaledown, y_scaledown;
|
2021-03-29 21:17:58 +01:00
|
|
|
|
if (ISL_GFX_VER(batch->blorp->isl_dev) >= 12) {
|
2019-05-10 00:38:12 +01:00
|
|
|
|
x_scaledown = aux_fmtl->bw * 8;
|
|
|
|
|
y_scaledown = aux_fmtl->bh * 4;
|
2021-03-29 21:17:58 +01:00
|
|
|
|
} else if (ISL_GFX_VER(batch->blorp->isl_dev) >= 9) {
|
2016-08-19 11:49:45 +01:00
|
|
|
|
x_scaledown = aux_fmtl->bw * 8;
|
|
|
|
|
y_scaledown = aux_fmtl->bh * 8;
|
2021-03-29 21:17:58 +01:00
|
|
|
|
} else if (ISL_GFX_VER(batch->blorp->isl_dev) >= 8) {
|
2016-08-19 11:49:45 +01:00
|
|
|
|
x_scaledown = aux_fmtl->bw * 8;
|
|
|
|
|
y_scaledown = aux_fmtl->bh * 16;
|
|
|
|
|
} else {
|
|
|
|
|
x_scaledown = aux_fmtl->bw / 2;
|
|
|
|
|
y_scaledown = aux_fmtl->bh / 2;
|
|
|
|
|
}
|
2017-11-11 20:31:54 +00:00
|
|
|
|
params.x0 = params.y0 = 0;
|
2018-05-15 23:57:39 +01:00
|
|
|
|
params.x1 = minify(params.dst.surf.logical_level0_px.width, level);
|
|
|
|
|
params.y1 = minify(params.dst.surf.logical_level0_px.height, level);
|
2017-11-11 20:31:54 +00:00
|
|
|
|
params.x1 = ALIGN(params.x1, x_scaledown) / x_scaledown;
|
|
|
|
|
params.y1 = ALIGN(params.y1, y_scaledown) / y_scaledown;
|
2016-04-22 20:55:49 +01:00
|
|
|
|
|
2021-03-29 22:41:58 +01:00
|
|
|
|
if (batch->blorp->isl_dev->info->ver >= 10) {
|
2018-05-15 23:28:05 +01:00
|
|
|
|
assert(resolve_op == ISL_AUX_OP_FULL_RESOLVE ||
|
|
|
|
|
resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE ||
|
|
|
|
|
resolve_op == ISL_AUX_OP_AMBIGUATE);
|
2021-03-29 22:41:58 +01:00
|
|
|
|
} else if (batch->blorp->isl_dev->info->ver >= 9) {
|
2018-01-19 23:02:07 +00:00
|
|
|
|
assert(resolve_op == ISL_AUX_OP_FULL_RESOLVE ||
|
|
|
|
|
resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE);
|
2016-08-19 10:23:04 +01:00
|
|
|
|
} else {
|
|
|
|
|
/* Broadwell and earlier do not have a partial resolve */
|
2018-01-19 23:02:07 +00:00
|
|
|
|
assert(resolve_op == ISL_AUX_OP_FULL_RESOLVE);
|
2016-08-19 10:23:04 +01:00
|
|
|
|
}
|
2017-11-11 20:31:54 +00:00
|
|
|
|
params.fast_clear_op = resolve_op;
|
|
|
|
|
params.num_layers = num_layers;
|
2016-04-22 20:55:49 +01:00
|
|
|
|
|
|
|
|
|
/* Note: there is no need to initialize push constants because it doesn't
|
|
|
|
|
* matter what data gets dispatched to the render target. However, we must
|
|
|
|
|
* ensure that the fragment shader delivers the data using the "replicated
|
|
|
|
|
* color" message.
|
|
|
|
|
*/
|
|
|
|
|
|
2019-01-09 23:15:49 +00:00
|
|
|
|
if (!blorp_params_get_clear_kernel(batch, ¶ms, true, false))
|
2017-03-14 12:12:22 +00:00
|
|
|
|
return;
|
2016-04-22 20:55:49 +01:00
|
|
|
|
|
2016-08-19 08:54:56 +01:00
|
|
|
|
batch->blorp->exec(batch, ¶ms);
|
2016-07-23 20:46:10 +01:00
|
|
|
|
}
|
2017-06-23 18:27:27 +01:00
|
|
|
|
|
2017-11-11 22:28:17 +00:00
|
|
|
|
static nir_ssa_def *
|
|
|
|
|
blorp_nir_bit(nir_builder *b, nir_ssa_def *src, unsigned bit)
|
|
|
|
|
{
|
|
|
|
|
return nir_iand(b, nir_ushr(b, src, nir_imm_int(b, bit)),
|
|
|
|
|
nir_imm_int(b, 1));
|
|
|
|
|
}
|
|
|
|
|
|
2019-10-30 14:14:06 +00:00
|
|
|
|
#pragma pack(push, 1)
|
2017-06-23 18:27:27 +01:00
|
|
|
|
struct blorp_mcs_partial_resolve_key
|
|
|
|
|
{
|
|
|
|
|
enum blorp_shader_type shader_type;
|
2017-11-11 22:28:17 +00:00
|
|
|
|
bool indirect_clear_color;
|
|
|
|
|
bool int_format;
|
2017-06-23 18:27:27 +01:00
|
|
|
|
uint32_t num_samples;
|
|
|
|
|
};
|
2019-10-30 14:14:06 +00:00
|
|
|
|
#pragma pack(pop)
|
2017-06-23 18:27:27 +01:00
|
|
|
|
|
|
|
|
|
static bool
|
2019-01-09 23:15:49 +00:00
|
|
|
|
blorp_params_get_mcs_partial_resolve_kernel(struct blorp_batch *batch,
|
2017-06-23 18:27:27 +01:00
|
|
|
|
struct blorp_params *params)
|
|
|
|
|
{
|
2019-01-09 23:15:49 +00:00
|
|
|
|
struct blorp_context *blorp = batch->blorp;
|
2017-06-23 18:27:27 +01:00
|
|
|
|
const struct blorp_mcs_partial_resolve_key blorp_key = {
|
|
|
|
|
.shader_type = BLORP_SHADER_TYPE_MCS_PARTIAL_RESOLVE,
|
2017-11-11 22:28:17 +00:00
|
|
|
|
.indirect_clear_color = params->dst.clear_color_addr.buffer != NULL,
|
|
|
|
|
.int_format = isl_format_has_int_channel(params->dst.view.format),
|
2017-06-23 18:27:27 +01:00
|
|
|
|
.num_samples = params->num_samples,
|
|
|
|
|
};
|
|
|
|
|
|
2019-01-09 23:15:49 +00:00
|
|
|
|
if (blorp->lookup_shader(batch, &blorp_key, sizeof(blorp_key),
|
2017-06-23 18:27:27 +01:00
|
|
|
|
¶ms->wm_prog_kernel, ¶ms->wm_prog_data))
|
|
|
|
|
return true;
|
|
|
|
|
|
|
|
|
|
void *mem_ctx = ralloc_context(NULL);
|
|
|
|
|
|
|
|
|
|
nir_builder b;
|
2019-02-13 11:11:47 +00:00
|
|
|
|
blorp_nir_init_shader(&b, mem_ctx, MESA_SHADER_FRAGMENT,
|
2020-09-29 08:54:07 +01:00
|
|
|
|
blorp_shader_type_to_name(blorp_key.shader_type));
|
2017-06-23 18:27:27 +01:00
|
|
|
|
|
|
|
|
|
nir_variable *v_color =
|
|
|
|
|
BLORP_CREATE_NIR_INPUT(b.shader, clear_color, glsl_vec4_type());
|
|
|
|
|
|
|
|
|
|
nir_variable *frag_color =
|
|
|
|
|
nir_variable_create(b.shader, nir_var_shader_out,
|
|
|
|
|
glsl_vec4_type(), "gl_FragColor");
|
|
|
|
|
frag_color->data.location = FRAG_RESULT_COLOR;
|
|
|
|
|
|
|
|
|
|
/* Do an MCS fetch and check if it is equal to the magic clear value */
|
|
|
|
|
nir_ssa_def *mcs =
|
2019-07-18 15:59:44 +01:00
|
|
|
|
blorp_nir_txf_ms_mcs(&b, nir_f2i32(&b, nir_load_frag_coord(&b)),
|
2017-06-23 18:27:27 +01:00
|
|
|
|
nir_load_layer_id(&b));
|
|
|
|
|
nir_ssa_def *is_clear =
|
|
|
|
|
blorp_nir_mcs_is_clear_color(&b, mcs, blorp_key.num_samples);
|
|
|
|
|
|
|
|
|
|
/* If we aren't the clear value, discard. */
|
2021-01-02 08:13:30 +00:00
|
|
|
|
nir_discard_if(&b, nir_inot(&b, is_clear));
|
2017-06-23 18:27:27 +01:00
|
|
|
|
|
2017-11-11 22:28:17 +00:00
|
|
|
|
nir_ssa_def *clear_color = nir_load_var(&b, v_color);
|
2021-03-29 22:41:58 +01:00
|
|
|
|
if (blorp_key.indirect_clear_color && blorp->isl_dev->info->ver <= 8) {
|
2021-03-29 23:46:12 +01:00
|
|
|
|
/* Gfx7-8 clear colors are stored as single 0/1 bits */
|
2017-11-11 22:28:17 +00:00
|
|
|
|
clear_color = nir_vec4(&b, blorp_nir_bit(&b, clear_color, 31),
|
|
|
|
|
blorp_nir_bit(&b, clear_color, 30),
|
|
|
|
|
blorp_nir_bit(&b, clear_color, 29),
|
|
|
|
|
blorp_nir_bit(&b, clear_color, 28));
|
|
|
|
|
|
|
|
|
|
if (!blorp_key.int_format)
|
|
|
|
|
clear_color = nir_i2f32(&b, clear_color);
|
|
|
|
|
}
|
|
|
|
|
nir_store_var(&b, frag_color, clear_color, 0xf);
|
2017-06-23 18:27:27 +01:00
|
|
|
|
|
|
|
|
|
struct brw_wm_prog_key wm_key;
|
|
|
|
|
brw_blorp_init_wm_prog_key(&wm_key);
|
2019-02-21 23:20:39 +00:00
|
|
|
|
wm_key.base.tex.compressed_multisample_layout_mask = 1;
|
|
|
|
|
wm_key.base.tex.msaa_16 = blorp_key.num_samples == 16;
|
2017-06-23 18:27:27 +01:00
|
|
|
|
wm_key.multisample_fbo = true;
|
|
|
|
|
|
|
|
|
|
struct brw_wm_prog_data prog_data;
|
|
|
|
|
const unsigned *program =
|
|
|
|
|
blorp_compile_fs(blorp, mem_ctx, b.shader, &wm_key, false,
|
2017-10-22 04:55:45 +01:00
|
|
|
|
&prog_data);
|
2017-06-23 18:27:27 +01:00
|
|
|
|
|
|
|
|
|
bool result =
|
2020-03-12 21:27:13 +00:00
|
|
|
|
blorp->upload_shader(batch, MESA_SHADER_FRAGMENT,
|
|
|
|
|
&blorp_key, sizeof(blorp_key),
|
2017-10-22 04:55:45 +01:00
|
|
|
|
program, prog_data.base.program_size,
|
2017-06-23 18:27:27 +01:00
|
|
|
|
&prog_data.base, sizeof(prog_data),
|
|
|
|
|
¶ms->wm_prog_kernel, ¶ms->wm_prog_data);
|
|
|
|
|
|
|
|
|
|
ralloc_free(mem_ctx);
|
|
|
|
|
return result;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
blorp_mcs_partial_resolve(struct blorp_batch *batch,
|
|
|
|
|
struct blorp_surf *surf,
|
|
|
|
|
enum isl_format format,
|
|
|
|
|
uint32_t start_layer, uint32_t num_layers)
|
|
|
|
|
{
|
|
|
|
|
struct blorp_params params;
|
|
|
|
|
blorp_params_init(¶ms);
|
2020-06-30 23:00:13 +01:00
|
|
|
|
params.snapshot_type = INTEL_SNAPSHOT_MCS_PARTIAL_RESOLVE;
|
2017-06-23 18:27:27 +01:00
|
|
|
|
|
2021-03-29 22:41:58 +01:00
|
|
|
|
assert(batch->blorp->isl_dev->info->ver >= 7);
|
2017-06-23 18:27:27 +01:00
|
|
|
|
|
|
|
|
|
params.x0 = 0;
|
|
|
|
|
params.y0 = 0;
|
|
|
|
|
params.x1 = surf->surf->logical_level0_px.width;
|
|
|
|
|
params.y1 = surf->surf->logical_level0_px.height;
|
|
|
|
|
|
|
|
|
|
brw_blorp_surface_info_init(batch->blorp, ¶ms.src, surf, 0,
|
|
|
|
|
start_layer, format, false);
|
|
|
|
|
brw_blorp_surface_info_init(batch->blorp, ¶ms.dst, surf, 0,
|
|
|
|
|
start_layer, format, true);
|
|
|
|
|
|
|
|
|
|
params.num_samples = params.dst.surf.samples;
|
|
|
|
|
params.num_layers = num_layers;
|
2017-11-11 22:28:17 +00:00
|
|
|
|
params.dst_clear_color_as_input = surf->clear_color_addr.buffer != NULL;
|
2017-06-23 18:27:27 +01:00
|
|
|
|
|
|
|
|
|
memcpy(¶ms.wm_inputs.clear_color,
|
|
|
|
|
surf->clear_color.f32, sizeof(float) * 4);
|
|
|
|
|
|
2019-01-09 23:15:49 +00:00
|
|
|
|
if (!blorp_params_get_mcs_partial_resolve_kernel(batch, ¶ms))
|
2017-06-23 18:27:27 +01:00
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
batch->blorp->exec(batch, ¶ms);
|
|
|
|
|
}
|
2017-05-18 04:33:21 +01:00
|
|
|
|
|
|
|
|
|
/** Clear a CCS to the "uncompressed" state
|
|
|
|
|
*
|
|
|
|
|
* This pass is the CCS equivalent of a "HiZ resolve". It sets the CCS values
|
|
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* for a given layer/level of a surface to 0x0 which is the "uncompressed"
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* state which tells the sampler to go look at the main surface.
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*/
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void
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blorp_ccs_ambiguate(struct blorp_batch *batch,
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struct blorp_surf *surf,
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uint32_t level, uint32_t layer)
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{
|
2021-03-29 21:17:58 +01:00
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if (ISL_GFX_VER(batch->blorp->isl_dev) >= 10) {
|
2021-03-29 23:40:04 +01:00
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/* On gfx10 and above, we have a hardware resolve op for this */
|
2018-05-15 23:28:05 +01:00
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return blorp_ccs_resolve(batch, surf, level, layer, 1,
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surf->surf->format, ISL_AUX_OP_AMBIGUATE);
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}
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|
2017-05-18 04:33:21 +01:00
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struct blorp_params params;
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blorp_params_init(¶ms);
|
2020-06-30 23:00:13 +01:00
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params.snapshot_type = INTEL_SNAPSHOT_CCS_AMBIGUATE;
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2017-05-18 04:33:21 +01:00
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2021-03-29 21:17:58 +01:00
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assert(ISL_GFX_VER(batch->blorp->isl_dev) >= 7);
|
2017-05-18 04:33:21 +01:00
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const struct isl_format_layout *aux_fmtl =
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isl_format_get_layout(surf->aux_surf->format);
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assert(aux_fmtl->txc == ISL_TXC_CCS);
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params.dst = (struct brw_blorp_surface_info) {
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.enabled = true,
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.addr = surf->aux_addr,
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.view = {
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.usage = ISL_SURF_USAGE_RENDER_TARGET_BIT,
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.format = ISL_FORMAT_R32G32B32A32_UINT,
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.base_level = 0,
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.base_array_layer = 0,
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.levels = 1,
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.array_len = 1,
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.swizzle = ISL_SWIZZLE_IDENTITY,
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},
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};
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uint32_t z = 0;
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if (surf->surf->dim == ISL_SURF_DIM_3D) {
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z = layer;
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layer = 0;
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}
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uint32_t offset_B, x_offset_el, y_offset_el;
|
2018-02-21 10:23:52 +00:00
|
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isl_surf_get_image_offset_B_tile_el(surf->aux_surf, level, layer, z,
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|
|
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&offset_B, &x_offset_el, &y_offset_el);
|
2017-05-18 04:33:21 +01:00
|
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|
|
params.dst.addr.offset += offset_B;
|
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|
|
const uint32_t width_px =
|
|
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|
|
minify(surf->aux_surf->logical_level0_px.width, level);
|
|
|
|
|
const uint32_t height_px =
|
|
|
|
|
minify(surf->aux_surf->logical_level0_px.height, level);
|
|
|
|
|
const uint32_t width_el = DIV_ROUND_UP(width_px, aux_fmtl->bw);
|
|
|
|
|
const uint32_t height_el = DIV_ROUND_UP(height_px, aux_fmtl->bh);
|
|
|
|
|
|
|
|
|
|
struct isl_tile_info ccs_tile_info;
|
|
|
|
|
isl_surf_get_tile_info(surf->aux_surf, &ccs_tile_info);
|
|
|
|
|
|
|
|
|
|
/* We're going to map it as a regular RGBA32_UINT surface. We need to
|
|
|
|
|
* downscale a good deal. We start by computing the area on the CCS to
|
|
|
|
|
* clear in units of Y-tiled cache lines.
|
|
|
|
|
*/
|
|
|
|
|
uint32_t x_offset_cl, y_offset_cl, width_cl, height_cl;
|
2021-03-29 21:17:58 +01:00
|
|
|
|
if (ISL_GFX_VER(batch->blorp->isl_dev) >= 8) {
|
2017-05-18 04:33:21 +01:00
|
|
|
|
/* From the Sky Lake PRM Vol. 12 in the section on planes:
|
|
|
|
|
*
|
|
|
|
|
* "The Color Control Surface (CCS) contains the compression status
|
|
|
|
|
* of the cache-line pairs. The compression state of the cache-line
|
|
|
|
|
* pair is specified by 2 bits in the CCS. Each CCS cache-line
|
|
|
|
|
* represents an area on the main surface of 16x16 sets of 128 byte
|
|
|
|
|
* Y-tiled cache-line-pairs. CCS is always Y tiled."
|
|
|
|
|
*
|
|
|
|
|
* Each 2-bit surface element in the CCS corresponds to a single
|
|
|
|
|
* cache-line pair in the main surface. This means that 16x16 el block
|
|
|
|
|
* in the CCS maps to a Y-tiled cache line. Fortunately, CCS layouts
|
|
|
|
|
* are calculated with a very large alignment so we can round up to a
|
|
|
|
|
* whole cache line without worrying about overdraw.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
/* On Broadwell and above, a CCS tile is the same as a Y tile when
|
|
|
|
|
* viewed at the cache-line granularity. Fortunately, the horizontal
|
|
|
|
|
* and vertical alignment requirements of the CCS are such that we can
|
|
|
|
|
* align to an entire cache line without worrying about crossing over
|
|
|
|
|
* from one LOD to another.
|
|
|
|
|
*/
|
|
|
|
|
const uint32_t x_el_per_cl = ccs_tile_info.logical_extent_el.w / 8;
|
|
|
|
|
const uint32_t y_el_per_cl = ccs_tile_info.logical_extent_el.h / 8;
|
|
|
|
|
assert(surf->aux_surf->image_alignment_el.w % x_el_per_cl == 0);
|
|
|
|
|
assert(surf->aux_surf->image_alignment_el.h % y_el_per_cl == 0);
|
|
|
|
|
|
|
|
|
|
assert(x_offset_el % x_el_per_cl == 0);
|
|
|
|
|
assert(y_offset_el % y_el_per_cl == 0);
|
|
|
|
|
x_offset_cl = x_offset_el / x_el_per_cl;
|
|
|
|
|
y_offset_cl = y_offset_el / y_el_per_cl;
|
|
|
|
|
width_cl = DIV_ROUND_UP(width_el, x_el_per_cl);
|
|
|
|
|
height_cl = DIV_ROUND_UP(height_el, y_el_per_cl);
|
|
|
|
|
} else {
|
2021-03-29 23:40:04 +01:00
|
|
|
|
/* On gfx7, the CCS tiling is not so nice. However, there we are
|
2017-05-18 04:33:21 +01:00
|
|
|
|
* guaranteed that we only have a single level and slice so we don't
|
|
|
|
|
* have to worry about it and can just align to a whole tile.
|
|
|
|
|
*/
|
|
|
|
|
assert(surf->aux_surf->logical_level0_px.depth == 1);
|
|
|
|
|
assert(surf->aux_surf->logical_level0_px.array_len == 1);
|
|
|
|
|
assert(x_offset_el == 0 && y_offset_el == 0);
|
|
|
|
|
const uint32_t width_tl =
|
|
|
|
|
DIV_ROUND_UP(width_el, ccs_tile_info.logical_extent_el.w);
|
|
|
|
|
const uint32_t height_tl =
|
|
|
|
|
DIV_ROUND_UP(height_el, ccs_tile_info.logical_extent_el.h);
|
|
|
|
|
x_offset_cl = 0;
|
|
|
|
|
y_offset_cl = 0;
|
|
|
|
|
width_cl = width_tl * 8;
|
|
|
|
|
height_cl = height_tl * 8;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* We're going to use a RGBA32 format so as to write data as quickly as
|
|
|
|
|
* possible. A y-tiled cache line will then be 1x4 px.
|
|
|
|
|
*/
|
|
|
|
|
const uint32_t x_offset_rgba_px = x_offset_cl;
|
|
|
|
|
const uint32_t y_offset_rgba_px = y_offset_cl * 4;
|
|
|
|
|
const uint32_t width_rgba_px = width_cl;
|
|
|
|
|
const uint32_t height_rgba_px = height_cl * 4;
|
|
|
|
|
|
2019-06-19 12:47:19 +01:00
|
|
|
|
ASSERTED bool ok =
|
2017-05-18 04:33:21 +01:00
|
|
|
|
isl_surf_init(batch->blorp->isl_dev, ¶ms.dst.surf,
|
|
|
|
|
.dim = ISL_SURF_DIM_2D,
|
|
|
|
|
.format = ISL_FORMAT_R32G32B32A32_UINT,
|
|
|
|
|
.width = width_rgba_px + x_offset_rgba_px,
|
|
|
|
|
.height = height_rgba_px + y_offset_rgba_px,
|
|
|
|
|
.depth = 1,
|
|
|
|
|
.levels = 1,
|
|
|
|
|
.array_len = 1,
|
|
|
|
|
.samples = 1,
|
2018-09-05 20:02:12 +01:00
|
|
|
|
.row_pitch_B = surf->aux_surf->row_pitch_B,
|
2017-05-18 04:33:21 +01:00
|
|
|
|
.usage = ISL_SURF_USAGE_RENDER_TARGET_BIT,
|
|
|
|
|
.tiling_flags = ISL_TILING_Y0_BIT);
|
|
|
|
|
assert(ok);
|
|
|
|
|
|
|
|
|
|
params.x0 = x_offset_rgba_px;
|
|
|
|
|
params.y0 = y_offset_rgba_px;
|
|
|
|
|
params.x1 = x_offset_rgba_px + width_rgba_px;
|
|
|
|
|
params.y1 = y_offset_rgba_px + height_rgba_px;
|
|
|
|
|
|
|
|
|
|
/* A CCS value of 0 means "uncompressed." */
|
|
|
|
|
memset(¶ms.wm_inputs.clear_color, 0,
|
|
|
|
|
sizeof(params.wm_inputs.clear_color));
|
|
|
|
|
|
2019-01-09 23:15:49 +00:00
|
|
|
|
if (!blorp_params_get_clear_kernel(batch, ¶ms, true, false))
|
2017-05-18 04:33:21 +01:00
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
batch->blorp->exec(batch, ¶ms);
|
|
|
|
|
}
|