2016-04-01 13:57:54 +01:00
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/*
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* Copyright © 2013 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "util/ralloc.h"
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2016-08-31 00:32:51 +01:00
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#include "main/macros.h" /* Needed for MAX3 and MAX2 for format_rgb9e5 */
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#include "util/format_rgb9e5.h"
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2016-08-08 23:25:17 +01:00
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#include "blorp_priv.h"
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2016-08-19 09:58:41 +01:00
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#include "brw_defines.h"
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2016-04-01 13:57:54 +01:00
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2016-08-19 12:27:18 +01:00
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#include "compiler/nir/nir_builder.h"
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2016-04-28 01:17:11 +01:00
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2016-04-01 13:57:54 +01:00
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#define FILE_DEBUG_FLAG DEBUG_BLORP
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struct brw_blorp_const_color_prog_key
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{
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bool use_simd16_replicated_data;
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bool pad[3];
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};
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2016-04-28 01:17:11 +01:00
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static void
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2016-08-19 13:43:29 +01:00
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blorp_params_get_clear_kernel(struct blorp_context *blorp,
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struct blorp_params *params,
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bool use_replicated_data)
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2016-04-01 13:57:54 +01:00
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{
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2016-04-28 01:17:11 +01:00
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struct brw_blorp_const_color_prog_key blorp_key;
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memset(&blorp_key, 0, sizeof(blorp_key));
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blorp_key.use_simd16_replicated_data = use_replicated_data;
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2016-04-01 13:57:54 +01:00
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2016-08-19 08:54:56 +01:00
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if (blorp->lookup_shader(blorp, &blorp_key, sizeof(blorp_key),
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¶ms->wm_prog_kernel, ¶ms->wm_prog_data))
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2016-04-28 01:17:11 +01:00
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return;
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2016-04-01 13:57:54 +01:00
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2016-04-28 01:17:11 +01:00
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void *mem_ctx = ralloc_context(NULL);
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2016-04-01 13:57:54 +01:00
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2016-04-28 01:17:11 +01:00
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nir_builder b;
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nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
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b.shader->info.name = ralloc_strdup(b.shader, "BLORP-clear");
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2016-04-01 13:57:54 +01:00
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2016-05-15 05:43:39 +01:00
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nir_variable *v_color = nir_variable_create(b.shader, nir_var_shader_in,
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glsl_vec4_type(), "v_color");
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v_color->data.location = VARYING_SLOT_VAR0;
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2016-07-07 10:02:38 +01:00
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v_color->data.interpolation = INTERP_MODE_FLAT;
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2016-04-01 13:57:54 +01:00
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2016-04-28 01:17:11 +01:00
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nir_variable *frag_color = nir_variable_create(b.shader, nir_var_shader_out,
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glsl_vec4_type(),
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"gl_FragColor");
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frag_color->data.location = FRAG_RESULT_COLOR;
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2016-04-01 13:57:54 +01:00
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2016-05-15 05:43:39 +01:00
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nir_copy_var(&b, frag_color, v_color);
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2016-04-01 13:57:54 +01:00
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2016-04-28 01:17:11 +01:00
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struct brw_wm_prog_key wm_key;
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brw_blorp_init_wm_prog_key(&wm_key);
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2016-04-01 13:57:54 +01:00
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2016-04-28 01:17:11 +01:00
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struct brw_blorp_prog_data prog_data;
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unsigned program_size;
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const unsigned *program =
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2016-08-19 08:54:56 +01:00
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brw_blorp_compile_nir_shader(blorp, b.shader, &wm_key, use_replicated_data,
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2016-04-28 01:17:11 +01:00
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&prog_data, &program_size);
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2016-04-01 13:57:54 +01:00
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2016-08-19 08:54:56 +01:00
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blorp->upload_shader(blorp, &blorp_key, sizeof(blorp_key),
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program, program_size,
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&prog_data, sizeof(prog_data),
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¶ms->wm_prog_kernel, ¶ms->wm_prog_data);
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2016-04-01 13:57:54 +01:00
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2016-04-28 01:17:11 +01:00
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ralloc_free(mem_ctx);
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2016-04-22 19:38:23 +01:00
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}
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2016-08-19 11:53:33 +01:00
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/* The x0, y0, x1, and y1 parameters must already be populated with the render
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* area of the framebuffer to be cleared.
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*/
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static void
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get_fast_clear_rect(const struct isl_device *dev,
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const struct isl_surf *aux_surf,
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unsigned *x0, unsigned *y0,
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unsigned *x1, unsigned *y1)
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{
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unsigned int x_align, y_align;
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unsigned int x_scaledown, y_scaledown;
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/* Only single sampled surfaces need to (and actually can) be resolved. */
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if (aux_surf->usage == ISL_SURF_USAGE_CCS_BIT) {
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/* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
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* Target(s)", beneath the "Fast Color Clear" bullet (p327):
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*
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* Clear pass must have a clear rectangle that must follow
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* alignment rules in terms of pixels and lines as shown in the
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* table below. Further, the clear-rectangle height and width
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* must be multiple of the following dimensions. If the height
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* and width of the render target being cleared do not meet these
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* requirements, an MCS buffer can be created such that it
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* follows the requirement and covers the RT.
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*
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* The alignment size in the table that follows is related to the
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* alignment size that is baked into the CCS surface format but with X
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* alignment multiplied by 16 and Y alignment multiplied by 32.
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*/
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x_align = isl_format_get_layout(aux_surf->format)->bw;
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y_align = isl_format_get_layout(aux_surf->format)->bh;
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x_align *= 16;
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/* SKL+ line alignment requirement for Y-tiled are half those of the prior
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* generations.
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*/
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if (dev->info->gen >= 9)
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y_align *= 16;
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else
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y_align *= 32;
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/* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
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* Target(s)", beneath the "Fast Color Clear" bullet (p327):
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*
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* In order to optimize the performance MCS buffer (when bound to
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* 1X RT) clear similarly to MCS buffer clear for MSRT case,
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* clear rect is required to be scaled by the following factors
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* in the horizontal and vertical directions:
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*
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* The X and Y scale down factors in the table that follows are each
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* equal to half the alignment value computed above.
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*/
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x_scaledown = x_align / 2;
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y_scaledown = y_align / 2;
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/* From BSpec: 3D-Media-GPGPU Engine > 3D Pipeline > Pixel > Pixel
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* Backend > MCS Buffer for Render Target(s) [DevIVB+] > Table "Color
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* Clear of Non-MultiSampled Render Target Restrictions":
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*
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* Clear rectangle must be aligned to two times the number of
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* pixels in the table shown below due to 16x16 hashing across the
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* slice.
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*/
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x_align *= 2;
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y_align *= 2;
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} else {
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assert(aux_surf->usage == ISL_SURF_USAGE_MCS_BIT);
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/* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
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* Target(s)", beneath the "MSAA Compression" bullet (p326):
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*
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* Clear pass for this case requires that scaled down primitive
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* is sent down with upper left co-ordinate to coincide with
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* actual rectangle being cleared. For MSAA, clear rectangle’s
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* height and width need to as show in the following table in
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* terms of (width,height) of the RT.
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*
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* MSAA Width of Clear Rect Height of Clear Rect
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* 2X Ceil(1/8*width) Ceil(1/2*height)
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* 4X Ceil(1/8*width) Ceil(1/2*height)
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* 8X Ceil(1/2*width) Ceil(1/2*height)
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* 16X width Ceil(1/2*height)
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*
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* The text "with upper left co-ordinate to coincide with actual
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* rectangle being cleared" is a little confusing--it seems to imply
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* that to clear a rectangle from (x,y) to (x+w,y+h), one needs to
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* feed the pipeline using the rectangle (x,y) to
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* (x+Ceil(w/N),y+Ceil(h/2)), where N is either 2 or 8 depending on
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* the number of samples. Experiments indicate that this is not
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* quite correct; actually, what the hardware appears to do is to
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* align whatever rectangle is sent down the pipeline to the nearest
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* multiple of 2x2 blocks, and then scale it up by a factor of N
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* horizontally and 2 vertically. So the resulting alignment is 4
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* vertically and either 4 or 16 horizontally, and the scaledown
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* factor is 2 vertically and either 2 or 8 horizontally.
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*/
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switch (aux_surf->format) {
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case ISL_FORMAT_MCS_2X:
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case ISL_FORMAT_MCS_4X:
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x_scaledown = 8;
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break;
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case ISL_FORMAT_MCS_8X:
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x_scaledown = 2;
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break;
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case ISL_FORMAT_MCS_16X:
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x_scaledown = 1;
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break;
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default:
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unreachable("Unexpected MCS format for fast clear");
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}
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y_scaledown = 2;
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x_align = x_scaledown * 2;
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y_align = y_scaledown * 2;
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}
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*x0 = ROUND_DOWN_TO(*x0, x_align) / x_scaledown;
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*y0 = ROUND_DOWN_TO(*y0, y_align) / y_scaledown;
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*x1 = ALIGN(*x1, x_align) / x_scaledown;
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*y1 = ALIGN(*y1, y_align) / y_scaledown;
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}
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2016-08-08 23:25:17 +01:00
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void
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2016-08-19 08:54:56 +01:00
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blorp_fast_clear(struct blorp_batch *batch,
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2016-08-26 16:44:18 +01:00
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const struct blorp_surf *surf, enum isl_format format,
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uint32_t level, uint32_t start_layer, uint32_t num_layers,
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2016-07-25 22:03:49 +01:00
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uint32_t x0, uint32_t y0, uint32_t x1, uint32_t y1)
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{
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2016-08-19 13:43:29 +01:00
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struct blorp_params params;
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blorp_params_init(¶ms);
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2016-08-26 16:44:18 +01:00
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params.num_layers = num_layers;
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2016-04-22 20:55:49 +01:00
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2016-07-25 22:03:49 +01:00
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params.x0 = x0;
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params.y0 = y0;
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params.x1 = x1;
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params.y1 = y1;
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2016-04-22 20:55:49 +01:00
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2016-07-25 22:03:49 +01:00
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memset(¶ms.wm_inputs, 0xff, 4*sizeof(float));
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2016-08-19 10:23:04 +01:00
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params.fast_clear_op = BLORP_FAST_CLEAR_OP_CLEAR;
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2016-07-25 22:03:49 +01:00
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2016-08-19 11:53:33 +01:00
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get_fast_clear_rect(batch->blorp->isl_dev, surf->aux_surf,
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¶ms.x0, ¶ms.y0, ¶ms.x1, ¶ms.y1);
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2016-07-25 22:03:49 +01:00
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2016-08-19 13:43:29 +01:00
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blorp_params_get_clear_kernel(batch->blorp, ¶ms, true);
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2016-04-22 20:55:49 +01:00
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2016-08-26 16:44:18 +01:00
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brw_blorp_surface_info_init(batch->blorp, ¶ms.dst, surf, level,
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start_layer, format, true);
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2016-07-25 22:03:49 +01:00
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2016-08-19 08:54:56 +01:00
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batch->blorp->exec(batch, ¶ms);
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2016-07-25 22:03:49 +01:00
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}
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2016-08-08 23:25:17 +01:00
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void
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2016-08-19 08:54:56 +01:00
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blorp_clear(struct blorp_batch *batch,
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2016-08-19 13:43:29 +01:00
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const struct blorp_surf *surf,
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2016-08-26 16:44:18 +01:00
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uint32_t level, uint32_t start_layer, uint32_t num_layers,
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2016-07-25 22:03:49 +01:00
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uint32_t x0, uint32_t y0, uint32_t x1, uint32_t y1,
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enum isl_format format, union isl_color_value clear_color,
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bool color_write_disable[4])
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{
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2016-08-19 13:43:29 +01:00
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struct blorp_params params;
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blorp_params_init(¶ms);
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2016-07-25 22:03:49 +01:00
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params.x0 = x0;
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params.y0 = y0;
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params.x1 = x1;
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params.y1 = y1;
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2016-08-31 00:32:51 +01:00
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if (format == ISL_FORMAT_R9G9B9E5_SHAREDEXP) {
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clear_color.u32[0] = float3_to_rgb9e5(clear_color.f32);
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format = ISL_FORMAT_R32_UINT;
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}
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2016-07-25 22:03:49 +01:00
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|
|
memcpy(¶ms.wm_inputs, clear_color.f32, sizeof(float) * 4);
|
2016-04-22 20:55:49 +01:00
|
|
|
|
|
2016-04-28 01:18:02 +01:00
|
|
|
|
bool use_simd16_replicated_data = true;
|
2016-04-22 20:55:49 +01:00
|
|
|
|
|
|
|
|
|
/* From the SNB PRM (Vol4_Part1):
|
|
|
|
|
*
|
|
|
|
|
* "Replicated data (Message Type = 111) is only supported when
|
|
|
|
|
* accessing tiled memory. Using this Message Type to access linear
|
|
|
|
|
* (untiled) memory is UNDEFINED."
|
|
|
|
|
*/
|
2016-07-25 22:03:49 +01:00
|
|
|
|
if (surf->surf->tiling == ISL_TILING_LINEAR)
|
2016-04-28 01:18:02 +01:00
|
|
|
|
use_simd16_replicated_data = false;
|
2016-04-22 20:55:49 +01:00
|
|
|
|
|
|
|
|
|
/* Constant color writes ignore everyting in blend and color calculator
|
|
|
|
|
* state. This is not documented.
|
|
|
|
|
*/
|
2016-07-25 22:03:49 +01:00
|
|
|
|
for (unsigned i = 0; i < 4; i++) {
|
|
|
|
|
params.color_write_disable[i] = color_write_disable[i];
|
|
|
|
|
if (color_write_disable[i])
|
|
|
|
|
use_simd16_replicated_data = false;
|
|
|
|
|
}
|
|
|
|
|
|
2016-08-19 13:43:29 +01:00
|
|
|
|
blorp_params_get_clear_kernel(batch->blorp, ¶ms,
|
|
|
|
|
use_simd16_replicated_data);
|
2016-07-25 22:03:49 +01:00
|
|
|
|
|
2016-09-12 19:46:22 +01:00
|
|
|
|
while (num_layers > 0) {
|
|
|
|
|
brw_blorp_surface_info_init(batch->blorp, ¶ms.dst, surf, level,
|
|
|
|
|
start_layer, format, true);
|
2016-04-22 20:55:49 +01:00
|
|
|
|
|
2016-09-12 19:46:22 +01:00
|
|
|
|
/* We may be restricted on the number of layers we can bind at any one
|
|
|
|
|
* time. In particular, Sandy Bridge has a maximum number of layers of
|
|
|
|
|
* 512 but a maximum 3D texture size is much larger.
|
|
|
|
|
*/
|
|
|
|
|
params.num_layers = MIN2(params.dst.view.array_len, num_layers);
|
|
|
|
|
batch->blorp->exec(batch, ¶ms);
|
|
|
|
|
|
|
|
|
|
start_layer += params.num_layers;
|
|
|
|
|
num_layers -= params.num_layers;
|
|
|
|
|
}
|
2016-07-25 22:03:49 +01:00
|
|
|
|
}
|
|
|
|
|
|
2016-08-08 23:25:17 +01:00
|
|
|
|
void
|
2016-08-19 13:43:29 +01:00
|
|
|
|
blorp_ccs_resolve(struct blorp_batch *batch,
|
|
|
|
|
struct blorp_surf *surf, enum isl_format format)
|
2016-04-01 13:57:54 +01:00
|
|
|
|
{
|
2016-08-19 13:43:29 +01:00
|
|
|
|
struct blorp_params params;
|
|
|
|
|
blorp_params_init(¶ms);
|
2016-04-22 20:55:49 +01:00
|
|
|
|
|
2016-08-19 08:54:56 +01:00
|
|
|
|
brw_blorp_surface_info_init(batch->blorp, ¶ms.dst, surf,
|
2016-07-23 20:46:10 +01:00
|
|
|
|
0 /* level */, 0 /* layer */, format, true);
|
2016-04-22 20:55:49 +01:00
|
|
|
|
|
2016-08-19 11:49:45 +01:00
|
|
|
|
/* From the Ivy Bridge PRM, Vol2 Part1 11.9 "Render Target Resolve":
|
|
|
|
|
*
|
|
|
|
|
* A rectangle primitive must be scaled down by the following factors
|
|
|
|
|
* with respect to render target being resolved.
|
|
|
|
|
*
|
|
|
|
|
* The scaledown factors in the table that follows are related to the block
|
|
|
|
|
* size of the CCS format. For IVB and HSW, we divide by two, for BDW we
|
|
|
|
|
* multiply by 8 and 16. On Sky Lake, we multiply by 8.
|
|
|
|
|
*/
|
|
|
|
|
const struct isl_format_layout *aux_fmtl =
|
|
|
|
|
isl_format_get_layout(params.dst.aux_surf.format);
|
|
|
|
|
assert(aux_fmtl->txc == ISL_TXC_CCS);
|
|
|
|
|
|
|
|
|
|
unsigned x_scaledown, y_scaledown;
|
|
|
|
|
if (ISL_DEV_GEN(batch->blorp->isl_dev) >= 9) {
|
|
|
|
|
x_scaledown = aux_fmtl->bw * 8;
|
|
|
|
|
y_scaledown = aux_fmtl->bh * 8;
|
|
|
|
|
} else if (ISL_DEV_GEN(batch->blorp->isl_dev) >= 8) {
|
|
|
|
|
x_scaledown = aux_fmtl->bw * 8;
|
|
|
|
|
y_scaledown = aux_fmtl->bh * 16;
|
|
|
|
|
} else {
|
|
|
|
|
x_scaledown = aux_fmtl->bw / 2;
|
|
|
|
|
y_scaledown = aux_fmtl->bh / 2;
|
|
|
|
|
}
|
|
|
|
|
params.x0 = params.y0 = 0;
|
|
|
|
|
params.x1 = params.dst.aux_surf.logical_level0_px.width;
|
|
|
|
|
params.y1 = params.dst.aux_surf.logical_level0_px.height;
|
|
|
|
|
params.x1 = ALIGN(params.x1, x_scaledown) / x_scaledown;
|
|
|
|
|
params.y1 = ALIGN(params.y1, y_scaledown) / y_scaledown;
|
2016-04-22 20:55:49 +01:00
|
|
|
|
|
2016-08-19 10:23:04 +01:00
|
|
|
|
if (batch->blorp->isl_dev->info->gen >= 9) {
|
|
|
|
|
if (params.dst.aux_usage == ISL_AUX_USAGE_CCS_E)
|
|
|
|
|
params.fast_clear_op = BLORP_FAST_CLEAR_OP_RESOLVE_FULL;
|
|
|
|
|
else
|
|
|
|
|
params.fast_clear_op = BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL;
|
|
|
|
|
} else {
|
|
|
|
|
/* Broadwell and earlier do not have a partial resolve */
|
|
|
|
|
params.fast_clear_op = BLORP_FAST_CLEAR_OP_RESOLVE_FULL;
|
|
|
|
|
}
|
2016-04-22 20:55:49 +01:00
|
|
|
|
|
|
|
|
|
/* Note: there is no need to initialize push constants because it doesn't
|
|
|
|
|
* matter what data gets dispatched to the render target. However, we must
|
|
|
|
|
* ensure that the fragment shader delivers the data using the "replicated
|
|
|
|
|
* color" message.
|
|
|
|
|
*/
|
|
|
|
|
|
2016-08-19 13:43:29 +01:00
|
|
|
|
blorp_params_get_clear_kernel(batch->blorp, ¶ms, true);
|
2016-04-22 20:55:49 +01:00
|
|
|
|
|
2016-08-19 08:54:56 +01:00
|
|
|
|
batch->blorp->exec(batch, ¶ms);
|
2016-07-23 20:46:10 +01:00
|
|
|
|
}
|