2016-10-07 00:16:09 +01:00
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/*
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* Copyright © 2016 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include "radv_meta.h"
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#include "radv_private.h"
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#include "sid.h"
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2019-10-17 13:48:23 +01:00
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enum radv_depth_op {
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2021-04-10 02:24:05 +01:00
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DEPTH_DECOMPRESS,
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DEPTH_RESUMMARIZE,
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2019-10-17 13:48:23 +01:00
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};
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2021-08-18 16:02:09 +01:00
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static nir_shader *
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build_expand_depth_stencil_compute_shader(struct radv_device *dev)
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{
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const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_2D, false, GLSL_TYPE_FLOAT);
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2022-03-30 11:52:58 +01:00
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nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, "expand_depth_stencil_compute");
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2021-08-18 16:02:09 +01:00
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/* We need at least 8/8/1 to cover an entire HTILE block in a single workgroup. */
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b.shader->info.workgroup_size[0] = 8;
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b.shader->info.workgroup_size[1] = 8;
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2021-10-15 18:58:22 +01:00
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nir_variable *input_img = nir_variable_create(b.shader, nir_var_image, img_type, "in_img");
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2021-08-18 16:02:09 +01:00
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input_img->data.descriptor_set = 0;
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input_img->data.binding = 0;
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2021-10-15 18:58:22 +01:00
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nir_variable *output_img = nir_variable_create(b.shader, nir_var_image, img_type, "out_img");
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2021-08-18 16:02:09 +01:00
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output_img->data.descriptor_set = 0;
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output_img->data.binding = 1;
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nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b);
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nir_ssa_def *wg_id = nir_load_workgroup_id(&b, 32);
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nir_ssa_def *block_size =
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nir_imm_ivec4(&b, b.shader->info.workgroup_size[0], b.shader->info.workgroup_size[1],
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b.shader->info.workgroup_size[2], 0);
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nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
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nir_ssa_def *data = nir_image_deref_load(
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&b, 4, 32, &nir_build_deref_var(&b, input_img)->dest.ssa, global_id, nir_ssa_undef(&b, 1, 32),
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nir_imm_int(&b, 0), .image_dim = GLSL_SAMPLER_DIM_2D);
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/* We need a NIR_SCOPE_DEVICE memory_scope because ACO will avoid
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* creating a vmcnt(0) because it expects the L1 cache to keep memory
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* operations in-order for the same workgroup. The vmcnt(0) seems
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* necessary however. */
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nir_scoped_barrier(&b, .execution_scope = NIR_SCOPE_WORKGROUP, .memory_scope = NIR_SCOPE_DEVICE,
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.memory_semantics = NIR_MEMORY_ACQ_REL, .memory_modes = nir_var_mem_ssbo);
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nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa, global_id,
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nir_ssa_undef(&b, 1, 32), data, nir_imm_int(&b, 0),
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.image_dim = GLSL_SAMPLER_DIM_2D);
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return b.shader;
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}
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static VkResult
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create_expand_depth_stencil_compute(struct radv_device *device)
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{
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VkResult result = VK_SUCCESS;
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nir_shader *cs = build_expand_depth_stencil_compute_shader(device);
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VkDescriptorSetLayoutCreateInfo ds_create_info = {
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.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
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.flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
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.bindingCount = 2,
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.pBindings = (VkDescriptorSetLayoutBinding[]){
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{.binding = 0,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
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.descriptorCount = 1,
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.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
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.pImmutableSamplers = NULL},
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{.binding = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
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.descriptorCount = 1,
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.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
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.pImmutableSamplers = NULL},
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}};
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result = radv_CreateDescriptorSetLayout(
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radv_device_to_handle(device), &ds_create_info, &device->meta_state.alloc,
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&device->meta_state.expand_depth_stencil_compute_ds_layout);
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if (result != VK_SUCCESS)
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goto cleanup;
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VkPipelineLayoutCreateInfo pl_create_info = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
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.setLayoutCount = 1,
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.pSetLayouts = &device->meta_state.expand_depth_stencil_compute_ds_layout,
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.pushConstantRangeCount = 0,
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.pPushConstantRanges = NULL,
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};
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result = radv_CreatePipelineLayout(
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radv_device_to_handle(device), &pl_create_info, &device->meta_state.alloc,
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&device->meta_state.expand_depth_stencil_compute_p_layout);
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if (result != VK_SUCCESS)
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goto cleanup;
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/* compute shader */
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VkPipelineShaderStageCreateInfo pipeline_shader_stage = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
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.stage = VK_SHADER_STAGE_COMPUTE_BIT,
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.module = vk_shader_module_handle_from_nir(cs),
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.pName = "main",
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.pSpecializationInfo = NULL,
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};
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VkComputePipelineCreateInfo vk_pipeline_info = {
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.sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
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.stage = pipeline_shader_stage,
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.flags = 0,
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.layout = device->meta_state.expand_depth_stencil_compute_p_layout,
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};
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result = radv_CreateComputePipelines(
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radv_device_to_handle(device), radv_pipeline_cache_to_handle(&device->meta_state.cache), 1,
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&vk_pipeline_info, NULL,
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&device->meta_state.expand_depth_stencil_compute_pipeline);
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if (result != VK_SUCCESS)
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goto cleanup;
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cleanup:
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ralloc_free(cs);
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return result;
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}
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2017-12-18 18:38:52 +00:00
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static VkResult
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create_pipeline_layout(struct radv_device *device, VkPipelineLayout *layout)
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{
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2021-04-10 02:24:05 +01:00
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VkPipelineLayoutCreateInfo pl_create_info = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
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.setLayoutCount = 0,
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.pSetLayouts = NULL,
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.pushConstantRangeCount = 0,
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.pPushConstantRanges = NULL,
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};
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return radv_CreatePipelineLayout(radv_device_to_handle(device), &pl_create_info,
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&device->meta_state.alloc, layout);
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2017-12-18 18:38:52 +00:00
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}
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2016-10-07 00:16:09 +01:00
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static VkResult
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2022-03-16 15:07:58 +00:00
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create_pipeline(struct radv_device *device, uint32_t samples, VkPipelineLayout layout,
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enum radv_depth_op op, VkPipeline *pipeline)
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2016-10-07 00:16:09 +01:00
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{
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2021-04-10 02:24:05 +01:00
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VkResult result;
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VkDevice device_h = radv_device_to_handle(device);
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mtx_lock(&device->meta_state.mtx);
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if (*pipeline) {
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mtx_unlock(&device->meta_state.mtx);
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return VK_SUCCESS;
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}
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2022-03-30 11:52:58 +01:00
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nir_shader *vs_module = radv_meta_build_nir_vs_generate_vertices(device);
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nir_shader *fs_module = radv_meta_build_nir_fs_noop(device);
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2021-04-10 02:24:05 +01:00
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if (!vs_module || !fs_module) {
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/* XXX: Need more accurate error */
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result = VK_ERROR_OUT_OF_HOST_MEMORY;
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goto cleanup;
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}
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const VkPipelineSampleLocationsStateCreateInfoEXT sample_locs_create_info = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT,
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.sampleLocationsEnable = false,
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};
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2022-03-16 15:07:58 +00:00
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const VkPipelineRenderingCreateInfo rendering_create_info = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_RENDERING_CREATE_INFO,
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.depthAttachmentFormat = VK_FORMAT_D32_SFLOAT_S8_UINT,
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.stencilAttachmentFormat = VK_FORMAT_D32_SFLOAT_S8_UINT,
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};
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2021-04-10 02:24:05 +01:00
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const VkGraphicsPipelineCreateInfo pipeline_create_info = {
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.sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
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2022-03-16 15:07:58 +00:00
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.pNext = &rendering_create_info,
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2021-04-10 02:24:05 +01:00
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.stageCount = 2,
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.pStages =
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(VkPipelineShaderStageCreateInfo[]){
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{
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.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
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.stage = VK_SHADER_STAGE_VERTEX_BIT,
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.module = vk_shader_module_handle_from_nir(vs_module),
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.pName = "main",
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},
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{
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.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
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.stage = VK_SHADER_STAGE_FRAGMENT_BIT,
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.module = vk_shader_module_handle_from_nir(fs_module),
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.pName = "main",
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},
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},
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.pVertexInputState =
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&(VkPipelineVertexInputStateCreateInfo){
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.sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
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.vertexBindingDescriptionCount = 0,
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.vertexAttributeDescriptionCount = 0,
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},
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.pInputAssemblyState =
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&(VkPipelineInputAssemblyStateCreateInfo){
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.sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
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.topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
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.primitiveRestartEnable = false,
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},
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.pViewportState =
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&(VkPipelineViewportStateCreateInfo){
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.sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
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.viewportCount = 1,
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.scissorCount = 1,
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},
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.pRasterizationState =
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&(VkPipelineRasterizationStateCreateInfo){
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.sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
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.depthClampEnable = false,
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.rasterizerDiscardEnable = false,
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.polygonMode = VK_POLYGON_MODE_FILL,
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.cullMode = VK_CULL_MODE_NONE,
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.frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE,
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},
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.pMultisampleState =
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&(VkPipelineMultisampleStateCreateInfo){
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.sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
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.pNext = &sample_locs_create_info,
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.rasterizationSamples = samples,
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.sampleShadingEnable = false,
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.pSampleMask = NULL,
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.alphaToCoverageEnable = false,
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.alphaToOneEnable = false,
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},
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.pColorBlendState =
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&(VkPipelineColorBlendStateCreateInfo){
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.sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
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.logicOpEnable = false,
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.attachmentCount = 0,
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.pAttachments = NULL,
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},
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.pDepthStencilState =
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&(VkPipelineDepthStencilStateCreateInfo){
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.sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
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.depthTestEnable = false,
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.depthWriteEnable = false,
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.depthBoundsTestEnable = false,
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.stencilTestEnable = false,
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},
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.pDynamicState =
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&(VkPipelineDynamicStateCreateInfo){
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.sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
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.dynamicStateCount = 3,
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.pDynamicStates =
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(VkDynamicState[]){
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VK_DYNAMIC_STATE_VIEWPORT,
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VK_DYNAMIC_STATE_SCISSOR,
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VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT,
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},
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},
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.layout = layout,
|
2022-03-16 15:07:58 +00:00
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.renderPass = VK_NULL_HANDLE,
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2021-04-10 02:24:05 +01:00
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.subpass = 0,
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};
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struct radv_graphics_pipeline_create_info extra = {
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.use_rectlist = true,
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2021-06-09 13:29:25 +01:00
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.depth_compress_disable = true,
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.stencil_compress_disable = true,
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2021-04-10 02:24:05 +01:00
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.resummarize_enable = op == DEPTH_RESUMMARIZE,
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};
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result = radv_graphics_pipeline_create(
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device_h, radv_pipeline_cache_to_handle(&device->meta_state.cache), &pipeline_create_info,
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&extra, &device->meta_state.alloc, pipeline);
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2016-10-07 00:16:09 +01:00
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cleanup:
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2021-04-10 02:24:05 +01:00
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ralloc_free(fs_module);
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ralloc_free(vs_module);
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mtx_unlock(&device->meta_state.mtx);
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return result;
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2016-10-07 00:16:09 +01:00
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}
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void
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radv_device_finish_meta_depth_decomp_state(struct radv_device *device)
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{
|
2021-04-10 02:24:05 +01:00
|
|
|
struct radv_meta_state *state = &device->meta_state;
|
|
|
|
|
|
|
|
for (uint32_t i = 0; i < ARRAY_SIZE(state->depth_decomp); ++i) {
|
|
|
|
radv_DestroyPipelineLayout(radv_device_to_handle(device), state->depth_decomp[i].p_layout,
|
|
|
|
&state->alloc);
|
|
|
|
|
2021-06-09 13:29:25 +01:00
|
|
|
radv_DestroyPipeline(radv_device_to_handle(device),
|
|
|
|
state->depth_decomp[i].decompress_pipeline, &state->alloc);
|
2021-04-10 02:24:05 +01:00
|
|
|
radv_DestroyPipeline(radv_device_to_handle(device),
|
|
|
|
state->depth_decomp[i].resummarize_pipeline, &state->alloc);
|
|
|
|
}
|
2021-08-18 16:02:09 +01:00
|
|
|
|
|
|
|
radv_DestroyPipeline(radv_device_to_handle(device),
|
|
|
|
state->expand_depth_stencil_compute_pipeline, &state->alloc);
|
|
|
|
radv_DestroyPipelineLayout(radv_device_to_handle(device),
|
|
|
|
state->expand_depth_stencil_compute_p_layout, &state->alloc);
|
|
|
|
radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
|
|
|
|
state->expand_depth_stencil_compute_ds_layout, &state->alloc);
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
VkResult
|
2018-08-13 23:07:57 +01:00
|
|
|
radv_device_init_meta_depth_decomp_state(struct radv_device *device, bool on_demand)
|
2016-10-07 00:16:09 +01:00
|
|
|
{
|
2021-04-10 02:24:05 +01:00
|
|
|
struct radv_meta_state *state = &device->meta_state;
|
|
|
|
VkResult res = VK_SUCCESS;
|
|
|
|
|
|
|
|
for (uint32_t i = 0; i < ARRAY_SIZE(state->depth_decomp); ++i) {
|
|
|
|
uint32_t samples = 1 << i;
|
|
|
|
|
|
|
|
res = create_pipeline_layout(device, &state->depth_decomp[i].p_layout);
|
|
|
|
if (res != VK_SUCCESS)
|
2022-07-20 13:49:38 +01:00
|
|
|
return res;
|
2021-04-10 02:24:05 +01:00
|
|
|
|
|
|
|
if (on_demand)
|
|
|
|
continue;
|
|
|
|
|
2022-03-16 15:07:58 +00:00
|
|
|
res = create_pipeline(device, samples, state->depth_decomp[i].p_layout, DEPTH_DECOMPRESS,
|
2021-06-09 13:29:25 +01:00
|
|
|
&state->depth_decomp[i].decompress_pipeline);
|
|
|
|
if (res != VK_SUCCESS)
|
2022-07-20 13:49:38 +01:00
|
|
|
return res;
|
2021-04-10 02:24:05 +01:00
|
|
|
|
2022-03-16 15:07:58 +00:00
|
|
|
res = create_pipeline(device, samples, state->depth_decomp[i].p_layout, DEPTH_RESUMMARIZE,
|
2021-04-10 02:24:05 +01:00
|
|
|
&state->depth_decomp[i].resummarize_pipeline);
|
|
|
|
if (res != VK_SUCCESS)
|
2022-07-20 13:49:38 +01:00
|
|
|
return res;
|
2021-04-10 02:24:05 +01:00
|
|
|
}
|
|
|
|
|
2022-07-20 13:49:38 +01:00
|
|
|
return create_expand_depth_stencil_compute(device);
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
2019-07-02 13:50:24 +01:00
|
|
|
static VkPipeline *
|
2021-04-10 02:24:05 +01:00
|
|
|
radv_get_depth_pipeline(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
|
|
|
|
const VkImageSubresourceRange *subresourceRange, enum radv_depth_op op)
|
2019-07-02 13:50:24 +01:00
|
|
|
{
|
2021-04-10 02:24:05 +01:00
|
|
|
struct radv_meta_state *state = &cmd_buffer->device->meta_state;
|
|
|
|
uint32_t samples = image->info.samples;
|
|
|
|
uint32_t samples_log2 = ffs(samples) - 1;
|
|
|
|
VkPipeline *pipeline;
|
|
|
|
|
2021-06-09 13:29:25 +01:00
|
|
|
if (!state->depth_decomp[samples_log2].decompress_pipeline) {
|
2021-04-10 02:24:05 +01:00
|
|
|
VkResult ret;
|
|
|
|
|
2022-03-16 15:07:58 +00:00
|
|
|
ret = create_pipeline(cmd_buffer->device, samples, state->depth_decomp[samples_log2].p_layout,
|
|
|
|
DEPTH_DECOMPRESS, &state->depth_decomp[samples_log2].decompress_pipeline);
|
2021-06-09 13:29:25 +01:00
|
|
|
if (ret != VK_SUCCESS) {
|
|
|
|
cmd_buffer->record_result = ret;
|
|
|
|
return NULL;
|
2021-04-10 02:24:05 +01:00
|
|
|
}
|
|
|
|
|
2022-03-16 15:07:58 +00:00
|
|
|
ret = create_pipeline(cmd_buffer->device, samples, state->depth_decomp[samples_log2].p_layout,
|
|
|
|
DEPTH_RESUMMARIZE, &state->depth_decomp[samples_log2].resummarize_pipeline);
|
2021-04-10 02:24:05 +01:00
|
|
|
if (ret != VK_SUCCESS) {
|
|
|
|
cmd_buffer->record_result = ret;
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (op) {
|
|
|
|
case DEPTH_DECOMPRESS:
|
2021-06-09 13:29:25 +01:00
|
|
|
pipeline = &state->depth_decomp[samples_log2].decompress_pipeline;
|
2021-04-10 02:24:05 +01:00
|
|
|
break;
|
|
|
|
case DEPTH_RESUMMARIZE:
|
|
|
|
pipeline = &state->depth_decomp[samples_log2].resummarize_pipeline;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
unreachable("unknown operation");
|
|
|
|
}
|
|
|
|
|
|
|
|
return pipeline;
|
2019-07-02 13:50:24 +01:00
|
|
|
}
|
|
|
|
|
2019-06-06 10:46:21 +01:00
|
|
|
static void
|
2021-04-10 02:24:05 +01:00
|
|
|
radv_process_depth_image_layer(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
|
|
|
|
const VkImageSubresourceRange *range, int level, int layer)
|
2019-06-06 10:46:21 +01:00
|
|
|
{
|
2021-04-10 02:24:05 +01:00
|
|
|
struct radv_device *device = cmd_buffer->device;
|
|
|
|
struct radv_image_view iview;
|
|
|
|
uint32_t width, height;
|
|
|
|
|
|
|
|
width = radv_minify(image->info.width, range->baseMipLevel + level);
|
|
|
|
height = radv_minify(image->info.height, range->baseMipLevel + level);
|
|
|
|
|
|
|
|
radv_image_view_init(&iview, device,
|
|
|
|
&(VkImageViewCreateInfo){
|
|
|
|
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
|
|
|
|
.image = radv_image_to_handle(image),
|
|
|
|
.viewType = radv_meta_get_view_type(image),
|
2022-03-25 19:58:39 +00:00
|
|
|
.format = image->vk.format,
|
2021-04-10 02:24:05 +01:00
|
|
|
.subresourceRange =
|
|
|
|
{
|
|
|
|
.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT,
|
|
|
|
.baseMipLevel = range->baseMipLevel + level,
|
|
|
|
.levelCount = 1,
|
|
|
|
.baseArrayLayer = range->baseArrayLayer + layer,
|
|
|
|
.layerCount = 1,
|
|
|
|
},
|
|
|
|
},
|
2022-05-03 07:51:31 +01:00
|
|
|
0, NULL);
|
2021-04-10 02:24:05 +01:00
|
|
|
|
2022-03-16 15:07:58 +00:00
|
|
|
const VkRenderingAttachmentInfo depth_att = {
|
|
|
|
.sType = VK_STRUCTURE_TYPE_RENDERING_ATTACHMENT_INFO,
|
|
|
|
.imageView = radv_image_view_to_handle(&iview),
|
|
|
|
.imageLayout = VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL,
|
|
|
|
.loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
|
|
|
|
.storeOp = VK_ATTACHMENT_STORE_OP_STORE,
|
|
|
|
};
|
|
|
|
|
|
|
|
const VkRenderingAttachmentInfo stencil_att = {
|
|
|
|
.sType = VK_STRUCTURE_TYPE_RENDERING_ATTACHMENT_INFO,
|
|
|
|
.imageView = radv_image_view_to_handle(&iview),
|
|
|
|
.imageLayout = VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL,
|
|
|
|
.loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
|
|
|
|
.storeOp = VK_ATTACHMENT_STORE_OP_STORE,
|
|
|
|
};
|
|
|
|
|
|
|
|
const VkRenderingInfo rendering_info = {
|
|
|
|
.sType = VK_STRUCTURE_TYPE_RENDERING_INFO,
|
|
|
|
.renderArea = {
|
|
|
|
.offset = { 0, 0 },
|
|
|
|
.extent = { width, height }
|
|
|
|
},
|
|
|
|
.layerCount = 1,
|
|
|
|
.pDepthAttachment = &depth_att,
|
|
|
|
.pStencilAttachment = &stencil_att,
|
|
|
|
};
|
|
|
|
|
|
|
|
radv_CmdBeginRendering(radv_cmd_buffer_to_handle(cmd_buffer), &rendering_info);
|
2021-04-10 02:24:05 +01:00
|
|
|
|
|
|
|
radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
|
2022-03-16 15:07:58 +00:00
|
|
|
|
|
|
|
radv_CmdEndRendering(radv_cmd_buffer_to_handle(cmd_buffer));
|
2021-04-10 02:24:05 +01:00
|
|
|
|
2021-09-29 08:46:46 +01:00
|
|
|
radv_image_view_finish(&iview);
|
2019-06-06 10:46:21 +01:00
|
|
|
}
|
|
|
|
|
2021-04-10 02:24:05 +01:00
|
|
|
static void
|
|
|
|
radv_process_depth_stencil(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
|
|
|
|
const VkImageSubresourceRange *subresourceRange,
|
|
|
|
struct radv_sample_locations_state *sample_locs, enum radv_depth_op op)
|
2016-10-07 00:16:09 +01:00
|
|
|
{
|
2021-04-10 02:24:05 +01:00
|
|
|
struct radv_meta_saved_state saved_state;
|
|
|
|
VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
|
|
|
|
VkPipeline *pipeline;
|
|
|
|
|
|
|
|
radv_meta_save(
|
|
|
|
&saved_state, cmd_buffer,
|
|
|
|
RADV_META_SAVE_GRAPHICS_PIPELINE | RADV_META_SAVE_SAMPLE_LOCATIONS | RADV_META_SAVE_PASS);
|
|
|
|
|
|
|
|
pipeline = radv_get_depth_pipeline(cmd_buffer, image, subresourceRange, op);
|
|
|
|
|
|
|
|
radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_GRAPHICS,
|
|
|
|
*pipeline);
|
|
|
|
|
|
|
|
if (sample_locs) {
|
2022-03-25 19:58:39 +00:00
|
|
|
assert(image->vk.create_flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
|
2021-04-10 02:24:05 +01:00
|
|
|
|
|
|
|
/* Set the sample locations specified during explicit or
|
|
|
|
* automatic layout transitions, otherwise the depth decompress
|
|
|
|
* pass uses the default HW locations.
|
|
|
|
*/
|
|
|
|
radv_CmdSetSampleLocationsEXT(cmd_buffer_h,
|
|
|
|
&(VkSampleLocationsInfoEXT){
|
|
|
|
.sampleLocationsPerPixel = sample_locs->per_pixel,
|
|
|
|
.sampleLocationGridSize = sample_locs->grid_size,
|
|
|
|
.sampleLocationsCount = sample_locs->count,
|
|
|
|
.pSampleLocations = sample_locs->locations,
|
|
|
|
});
|
|
|
|
}
|
|
|
|
|
|
|
|
for (uint32_t l = 0; l < radv_get_levelCount(image, subresourceRange); ++l) {
|
|
|
|
|
|
|
|
/* Do not decompress levels without HTILE. */
|
|
|
|
if (!radv_htile_enabled(image, subresourceRange->baseMipLevel + l))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
uint32_t width = radv_minify(image->info.width, subresourceRange->baseMipLevel + l);
|
|
|
|
uint32_t height = radv_minify(image->info.height, subresourceRange->baseMipLevel + l);
|
|
|
|
|
|
|
|
radv_CmdSetViewport(cmd_buffer_h, 0, 1,
|
|
|
|
&(VkViewport){.x = 0,
|
|
|
|
.y = 0,
|
|
|
|
.width = width,
|
|
|
|
.height = height,
|
|
|
|
.minDepth = 0.0f,
|
|
|
|
.maxDepth = 1.0f});
|
|
|
|
|
|
|
|
radv_CmdSetScissor(cmd_buffer_h, 0, 1,
|
|
|
|
&(VkRect2D){
|
|
|
|
.offset = {0, 0},
|
|
|
|
.extent = {width, height},
|
|
|
|
});
|
|
|
|
|
|
|
|
for (uint32_t s = 0; s < radv_get_layerCount(image, subresourceRange); s++) {
|
|
|
|
radv_process_depth_image_layer(cmd_buffer, image, subresourceRange, l, s);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
radv_meta_restore(&saved_state, cmd_buffer);
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
2021-08-18 16:02:09 +01:00
|
|
|
static void
|
|
|
|
radv_expand_depth_stencil_compute(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
|
|
|
|
const VkImageSubresourceRange *subresourceRange)
|
|
|
|
{
|
|
|
|
struct radv_meta_saved_state saved_state;
|
|
|
|
struct radv_image_view load_iview = {0};
|
|
|
|
struct radv_image_view store_iview = {0};
|
|
|
|
struct radv_device *device = cmd_buffer->device;
|
|
|
|
|
|
|
|
assert(radv_image_is_tc_compat_htile(image));
|
|
|
|
|
|
|
|
cmd_buffer->state.flush_bits |=
|
2022-03-30 09:28:56 +01:00
|
|
|
radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT, image);
|
2021-08-18 16:02:09 +01:00
|
|
|
|
|
|
|
radv_meta_save(&saved_state, cmd_buffer,
|
|
|
|
RADV_META_SAVE_DESCRIPTORS | RADV_META_SAVE_COMPUTE_PIPELINE);
|
|
|
|
|
|
|
|
radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE,
|
|
|
|
device->meta_state.expand_depth_stencil_compute_pipeline);
|
|
|
|
|
|
|
|
for (uint32_t l = 0; l < radv_get_levelCount(image, subresourceRange); l++) {
|
|
|
|
uint32_t width, height;
|
|
|
|
|
|
|
|
/* Do not decompress levels without HTILE. */
|
|
|
|
if (!radv_htile_enabled(image, subresourceRange->baseMipLevel + l))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
width = radv_minify(image->info.width, subresourceRange->baseMipLevel + l);
|
|
|
|
height = radv_minify(image->info.height, subresourceRange->baseMipLevel + l);
|
|
|
|
|
|
|
|
for (uint32_t s = 0; s < radv_get_layerCount(image, subresourceRange); s++) {
|
|
|
|
radv_image_view_init(
|
|
|
|
&load_iview, cmd_buffer->device,
|
|
|
|
&(VkImageViewCreateInfo){
|
|
|
|
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
|
|
|
|
.image = radv_image_to_handle(image),
|
|
|
|
.viewType = VK_IMAGE_VIEW_TYPE_2D,
|
2022-03-25 19:58:39 +00:00
|
|
|
.format = image->vk.format,
|
2021-08-18 16:02:09 +01:00
|
|
|
.subresourceRange = {.aspectMask = subresourceRange->aspectMask,
|
|
|
|
.baseMipLevel = subresourceRange->baseMipLevel + l,
|
|
|
|
.levelCount = 1,
|
|
|
|
.baseArrayLayer = subresourceRange->baseArrayLayer + s,
|
|
|
|
.layerCount = 1},
|
|
|
|
},
|
2022-05-03 07:51:31 +01:00
|
|
|
0, &(struct radv_image_view_extra_create_info){.enable_compression = true});
|
2021-08-18 16:02:09 +01:00
|
|
|
radv_image_view_init(
|
|
|
|
&store_iview, cmd_buffer->device,
|
|
|
|
&(VkImageViewCreateInfo){
|
|
|
|
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
|
|
|
|
.image = radv_image_to_handle(image),
|
|
|
|
.viewType = VK_IMAGE_VIEW_TYPE_2D,
|
2022-03-25 19:58:39 +00:00
|
|
|
.format = image->vk.format,
|
2021-08-18 16:02:09 +01:00
|
|
|
.subresourceRange = {.aspectMask = subresourceRange->aspectMask,
|
|
|
|
.baseMipLevel = subresourceRange->baseMipLevel + l,
|
|
|
|
.levelCount = 1,
|
|
|
|
.baseArrayLayer = subresourceRange->baseArrayLayer + s,
|
|
|
|
.layerCount = 1},
|
|
|
|
},
|
2022-05-03 07:51:31 +01:00
|
|
|
0, &(struct radv_image_view_extra_create_info){.disable_compression = true});
|
2021-08-18 16:02:09 +01:00
|
|
|
|
|
|
|
radv_meta_push_descriptor_set(
|
|
|
|
cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE,
|
|
|
|
device->meta_state.expand_depth_stencil_compute_p_layout, 0, /* set */
|
|
|
|
2, /* descriptorWriteCount */
|
|
|
|
(VkWriteDescriptorSet[]){{.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
|
|
|
|
.dstBinding = 0,
|
|
|
|
.dstArrayElement = 0,
|
|
|
|
.descriptorCount = 1,
|
|
|
|
.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
|
|
|
|
.pImageInfo =
|
|
|
|
(VkDescriptorImageInfo[]){
|
|
|
|
{
|
|
|
|
.sampler = VK_NULL_HANDLE,
|
|
|
|
.imageView = radv_image_view_to_handle(&load_iview),
|
|
|
|
.imageLayout = VK_IMAGE_LAYOUT_GENERAL,
|
|
|
|
},
|
|
|
|
}},
|
|
|
|
{.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
|
|
|
|
.dstBinding = 1,
|
|
|
|
.dstArrayElement = 0,
|
|
|
|
.descriptorCount = 1,
|
|
|
|
.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
|
|
|
|
.pImageInfo = (VkDescriptorImageInfo[]){
|
|
|
|
{
|
|
|
|
.sampler = VK_NULL_HANDLE,
|
|
|
|
.imageView = radv_image_view_to_handle(&store_iview),
|
|
|
|
.imageLayout = VK_IMAGE_LAYOUT_GENERAL,
|
|
|
|
},
|
|
|
|
}}});
|
|
|
|
|
|
|
|
radv_unaligned_dispatch(cmd_buffer, width, height, 1);
|
2021-09-29 08:46:46 +01:00
|
|
|
|
|
|
|
radv_image_view_finish(&load_iview);
|
|
|
|
radv_image_view_finish(&store_iview);
|
2021-08-18 16:02:09 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
radv_meta_restore(&saved_state, cmd_buffer);
|
|
|
|
|
|
|
|
cmd_buffer->state.flush_bits |=
|
|
|
|
RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_INV_VCACHE |
|
2022-03-30 09:28:56 +01:00
|
|
|
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT, image);
|
2021-08-18 16:02:09 +01:00
|
|
|
|
|
|
|
/* Initialize the HTILE metadata as "fully expanded". */
|
|
|
|
uint32_t htile_value = radv_get_htile_initial_value(cmd_buffer->device, image);
|
|
|
|
|
|
|
|
cmd_buffer->state.flush_bits |= radv_clear_htile(cmd_buffer, image, subresourceRange, htile_value);
|
|
|
|
}
|
|
|
|
|
2021-04-10 02:24:05 +01:00
|
|
|
void
|
2021-08-18 15:48:31 +01:00
|
|
|
radv_expand_depth_stencil(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
|
|
|
|
const VkImageSubresourceRange *subresourceRange,
|
|
|
|
struct radv_sample_locations_state *sample_locs)
|
2016-10-07 00:16:09 +01:00
|
|
|
{
|
2021-04-10 02:24:05 +01:00
|
|
|
struct radv_barrier_data barrier = {0};
|
2020-03-03 14:53:20 +00:00
|
|
|
|
2021-04-10 02:24:05 +01:00
|
|
|
barrier.layout_transitions.depth_stencil_expand = 1;
|
|
|
|
radv_describe_layout_transition(cmd_buffer, &barrier);
|
2020-03-03 14:53:20 +00:00
|
|
|
|
radv: abstract queue family away from queue family index.
If we introduce another queue type (video decode) we can have a
disconnect between the RADV_QUEUE_ enum and the API queue_family_index.
currently the driver has
GENERAL, COMPUTE, TRANSFER which would end up at QFI 0, 1, <nothing>
since we don't create transfer.
Now if I add VDEC we get
GENERAL, COMPUTE, TRANSFER, VDEC at QFI 0, 1, <nothing>, 2
or if you do nocompute
GENERAL, COMPUTE, TRANSFER, VDEC at QFI 0, <nothing>, <nothing>, 1
This means we have to add a remapping table between the API qfi
and the internal qf.
This patches tries to do that, in theory right now it just adds
overhead, but I'd like to exercise these paths.
v2: add radv_queue_ring abstraction, and pass physical device in,
as it makes adding uvd later easier.
v3: rename, and drop one direction as unneeded now, drop queue_family_index
from cmd_buffers.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13687>
2021-11-05 06:03:24 +00:00
|
|
|
if (cmd_buffer->qf == RADV_QUEUE_GENERAL) {
|
2021-08-18 16:02:09 +01:00
|
|
|
radv_process_depth_stencil(cmd_buffer, image, subresourceRange, sample_locs, DEPTH_DECOMPRESS);
|
|
|
|
} else {
|
|
|
|
radv_expand_depth_stencil_compute(cmd_buffer, image, subresourceRange);
|
|
|
|
}
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
2021-04-10 02:24:05 +01:00
|
|
|
void
|
|
|
|
radv_resummarize_depth_stencil(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
|
|
|
|
const VkImageSubresourceRange *subresourceRange,
|
|
|
|
struct radv_sample_locations_state *sample_locs)
|
2016-10-07 00:16:09 +01:00
|
|
|
{
|
2021-04-10 02:24:05 +01:00
|
|
|
struct radv_barrier_data barrier = {0};
|
2020-03-03 14:53:20 +00:00
|
|
|
|
2021-04-10 02:24:05 +01:00
|
|
|
barrier.layout_transitions.depth_stencil_resummarize = 1;
|
|
|
|
radv_describe_layout_transition(cmd_buffer, &barrier);
|
2020-03-03 14:53:20 +00:00
|
|
|
|
radv: abstract queue family away from queue family index.
If we introduce another queue type (video decode) we can have a
disconnect between the RADV_QUEUE_ enum and the API queue_family_index.
currently the driver has
GENERAL, COMPUTE, TRANSFER which would end up at QFI 0, 1, <nothing>
since we don't create transfer.
Now if I add VDEC we get
GENERAL, COMPUTE, TRANSFER, VDEC at QFI 0, 1, <nothing>, 2
or if you do nocompute
GENERAL, COMPUTE, TRANSFER, VDEC at QFI 0, <nothing>, <nothing>, 1
This means we have to add a remapping table between the API qfi
and the internal qf.
This patches tries to do that, in theory right now it just adds
overhead, but I'd like to exercise these paths.
v2: add radv_queue_ring abstraction, and pass physical device in,
as it makes adding uvd later easier.
v3: rename, and drop one direction as unneeded now, drop queue_family_index
from cmd_buffers.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13687>
2021-11-05 06:03:24 +00:00
|
|
|
assert(cmd_buffer->qf == RADV_QUEUE_GENERAL);
|
2021-04-10 02:24:05 +01:00
|
|
|
radv_process_depth_stencil(cmd_buffer, image, subresourceRange, sample_locs, DEPTH_RESUMMARIZE);
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|