radv: implement depth/stencil expand on compute
This works as long as the image is TC-compatible HTILE. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12452>
This commit is contained in:
Samuel Pitoiset
Marge Bot
parent
966b780992
commit
0ac8731b6c
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@ -33,6 +33,123 @@ enum radv_depth_op {
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DEPTH_RESUMMARIZE,
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};
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static nir_shader *
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build_expand_depth_stencil_compute_shader(struct radv_device *dev)
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{
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const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_2D, false, GLSL_TYPE_FLOAT);
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nir_builder b =
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nir_builder_init_simple_shader(MESA_SHADER_COMPUTE, NULL, "expand_depth_stencil_compute");
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/* We need at least 8/8/1 to cover an entire HTILE block in a single workgroup. */
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b.shader->info.workgroup_size[0] = 8;
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b.shader->info.workgroup_size[1] = 8;
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b.shader->info.workgroup_size[2] = 1;
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nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform, img_type, "in_img");
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input_img->data.descriptor_set = 0;
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input_img->data.binding = 0;
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nir_variable *output_img = nir_variable_create(b.shader, nir_var_uniform, img_type, "out_img");
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output_img->data.descriptor_set = 0;
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output_img->data.binding = 1;
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nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b);
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nir_ssa_def *wg_id = nir_load_workgroup_id(&b, 32);
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nir_ssa_def *block_size =
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nir_imm_ivec4(&b, b.shader->info.workgroup_size[0], b.shader->info.workgroup_size[1],
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b.shader->info.workgroup_size[2], 0);
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nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
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nir_ssa_def *data = nir_image_deref_load(
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&b, 4, 32, &nir_build_deref_var(&b, input_img)->dest.ssa, global_id, nir_ssa_undef(&b, 1, 32),
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nir_imm_int(&b, 0), .image_dim = GLSL_SAMPLER_DIM_2D);
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/* We need a NIR_SCOPE_DEVICE memory_scope because ACO will avoid
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* creating a vmcnt(0) because it expects the L1 cache to keep memory
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* operations in-order for the same workgroup. The vmcnt(0) seems
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* necessary however. */
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nir_scoped_barrier(&b, .execution_scope = NIR_SCOPE_WORKGROUP, .memory_scope = NIR_SCOPE_DEVICE,
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.memory_semantics = NIR_MEMORY_ACQ_REL, .memory_modes = nir_var_mem_ssbo);
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nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa, global_id,
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nir_ssa_undef(&b, 1, 32), data, nir_imm_int(&b, 0),
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.image_dim = GLSL_SAMPLER_DIM_2D);
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return b.shader;
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}
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static VkResult
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create_expand_depth_stencil_compute(struct radv_device *device)
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{
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VkResult result = VK_SUCCESS;
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nir_shader *cs = build_expand_depth_stencil_compute_shader(device);
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VkDescriptorSetLayoutCreateInfo ds_create_info = {
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.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
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.flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
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.bindingCount = 2,
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.pBindings = (VkDescriptorSetLayoutBinding[]){
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{.binding = 0,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
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.descriptorCount = 1,
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.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
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.pImmutableSamplers = NULL},
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{.binding = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
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.descriptorCount = 1,
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.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
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.pImmutableSamplers = NULL},
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}};
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result = radv_CreateDescriptorSetLayout(
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radv_device_to_handle(device), &ds_create_info, &device->meta_state.alloc,
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&device->meta_state.expand_depth_stencil_compute_ds_layout);
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if (result != VK_SUCCESS)
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goto cleanup;
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VkPipelineLayoutCreateInfo pl_create_info = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
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.setLayoutCount = 1,
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.pSetLayouts = &device->meta_state.expand_depth_stencil_compute_ds_layout,
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.pushConstantRangeCount = 0,
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.pPushConstantRanges = NULL,
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};
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result = radv_CreatePipelineLayout(
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radv_device_to_handle(device), &pl_create_info, &device->meta_state.alloc,
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&device->meta_state.expand_depth_stencil_compute_p_layout);
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if (result != VK_SUCCESS)
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goto cleanup;
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/* compute shader */
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VkPipelineShaderStageCreateInfo pipeline_shader_stage = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
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.stage = VK_SHADER_STAGE_COMPUTE_BIT,
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.module = vk_shader_module_handle_from_nir(cs),
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.pName = "main",
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.pSpecializationInfo = NULL,
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};
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VkComputePipelineCreateInfo vk_pipeline_info = {
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.sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
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.stage = pipeline_shader_stage,
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.flags = 0,
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.layout = device->meta_state.expand_depth_stencil_compute_p_layout,
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};
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result = radv_CreateComputePipelines(
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radv_device_to_handle(device), radv_pipeline_cache_to_handle(&device->meta_state.cache), 1,
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&vk_pipeline_info, NULL,
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&device->meta_state.expand_depth_stencil_compute_pipeline);
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if (result != VK_SUCCESS)
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goto cleanup;
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cleanup:
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ralloc_free(cs);
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return result;
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}
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static VkResult
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create_pass(struct radv_device *device, uint32_t samples, VkRenderPass *pass)
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{
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@ -263,6 +380,13 @@ radv_device_finish_meta_depth_decomp_state(struct radv_device *device)
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radv_DestroyPipeline(radv_device_to_handle(device),
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state->depth_decomp[i].resummarize_pipeline, &state->alloc);
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}
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radv_DestroyPipeline(radv_device_to_handle(device),
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state->expand_depth_stencil_compute_pipeline, &state->alloc);
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radv_DestroyPipelineLayout(radv_device_to_handle(device),
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state->expand_depth_stencil_compute_p_layout, &state->alloc);
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radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
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state->expand_depth_stencil_compute_ds_layout, &state->alloc);
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}
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VkResult
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@ -298,6 +422,10 @@ radv_device_init_meta_depth_decomp_state(struct radv_device *device, bool on_dem
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goto fail;
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}
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res = create_expand_depth_stencil_compute(device);
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if (res != VK_SUCCESS)
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goto fail;
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return VK_SUCCESS;
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fail:
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@ -481,6 +609,112 @@ radv_process_depth_stencil(struct radv_cmd_buffer *cmd_buffer, struct radv_image
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radv_meta_restore(&saved_state, cmd_buffer);
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}
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static void
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radv_expand_depth_stencil_compute(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
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const VkImageSubresourceRange *subresourceRange)
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{
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struct radv_meta_saved_state saved_state;
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struct radv_image_view load_iview = {0};
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struct radv_image_view store_iview = {0};
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struct radv_device *device = cmd_buffer->device;
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assert(radv_image_is_tc_compat_htile(image));
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cmd_buffer->state.flush_bits |=
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radv_dst_access_flush(cmd_buffer, VK_ACCESS_SHADER_WRITE_BIT, image);
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radv_meta_save(&saved_state, cmd_buffer,
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RADV_META_SAVE_DESCRIPTORS | RADV_META_SAVE_COMPUTE_PIPELINE);
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radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE,
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device->meta_state.expand_depth_stencil_compute_pipeline);
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for (uint32_t l = 0; l < radv_get_levelCount(image, subresourceRange); l++) {
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uint32_t width, height;
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/* Do not decompress levels without HTILE. */
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if (!radv_htile_enabled(image, subresourceRange->baseMipLevel + l))
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continue;
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width = radv_minify(image->info.width, subresourceRange->baseMipLevel + l);
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height = radv_minify(image->info.height, subresourceRange->baseMipLevel + l);
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for (uint32_t s = 0; s < radv_get_layerCount(image, subresourceRange); s++) {
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radv_image_view_init(
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&load_iview, cmd_buffer->device,
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&(VkImageViewCreateInfo){
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.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
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.image = radv_image_to_handle(image),
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.viewType = VK_IMAGE_VIEW_TYPE_2D,
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.format = image->vk_format,
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.subresourceRange = {.aspectMask = subresourceRange->aspectMask,
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.baseMipLevel = subresourceRange->baseMipLevel + l,
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.levelCount = 1,
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.baseArrayLayer = subresourceRange->baseArrayLayer + s,
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.layerCount = 1},
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},
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&(struct radv_image_view_extra_create_info){.enable_compression = true});
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radv_image_view_init(
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&store_iview, cmd_buffer->device,
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&(VkImageViewCreateInfo){
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.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
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.image = radv_image_to_handle(image),
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.viewType = VK_IMAGE_VIEW_TYPE_2D,
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.format = image->vk_format,
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.subresourceRange = {.aspectMask = subresourceRange->aspectMask,
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.baseMipLevel = subresourceRange->baseMipLevel + l,
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.levelCount = 1,
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.baseArrayLayer = subresourceRange->baseArrayLayer + s,
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.layerCount = 1},
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},
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&(struct radv_image_view_extra_create_info){.disable_compression = true});
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radv_meta_push_descriptor_set(
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cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE,
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device->meta_state.expand_depth_stencil_compute_p_layout, 0, /* set */
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2, /* descriptorWriteCount */
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(VkWriteDescriptorSet[]){{.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
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.dstBinding = 0,
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.dstArrayElement = 0,
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.descriptorCount = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
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.pImageInfo =
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(VkDescriptorImageInfo[]){
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{
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.sampler = VK_NULL_HANDLE,
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.imageView = radv_image_view_to_handle(&load_iview),
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.imageLayout = VK_IMAGE_LAYOUT_GENERAL,
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},
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}},
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{.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
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.dstBinding = 1,
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.dstArrayElement = 0,
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.descriptorCount = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
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.pImageInfo = (VkDescriptorImageInfo[]){
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{
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.sampler = VK_NULL_HANDLE,
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.imageView = radv_image_view_to_handle(&store_iview),
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.imageLayout = VK_IMAGE_LAYOUT_GENERAL,
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},
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}}});
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radv_unaligned_dispatch(cmd_buffer, width, height, 1);
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}
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}
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radv_meta_restore(&saved_state, cmd_buffer);
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cmd_buffer->state.flush_bits |=
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RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_INV_VCACHE |
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radv_src_access_flush(cmd_buffer, VK_ACCESS_SHADER_WRITE_BIT, image);
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/* Initialize the HTILE metadata as "fully expanded". */
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uint32_t htile_value = radv_get_htile_initial_value(cmd_buffer->device, image);
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cmd_buffer->state.flush_bits |= radv_clear_htile(cmd_buffer, image, subresourceRange, htile_value);
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}
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void
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radv_expand_depth_stencil(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
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const VkImageSubresourceRange *subresourceRange,
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@ -491,8 +725,11 @@ radv_expand_depth_stencil(struct radv_cmd_buffer *cmd_buffer, struct radv_image
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barrier.layout_transitions.depth_stencil_expand = 1;
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radv_describe_layout_transition(cmd_buffer, &barrier);
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assert(cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL);
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radv_process_depth_stencil(cmd_buffer, image, subresourceRange, sample_locs, DEPTH_DECOMPRESS);
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if (cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
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radv_process_depth_stencil(cmd_buffer, image, subresourceRange, sample_locs, DEPTH_DECOMPRESS);
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} else {
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radv_expand_depth_stencil_compute(cmd_buffer, image, subresourceRange);
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}
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}
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void
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@ -619,6 +619,10 @@ struct radv_meta_state {
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VkRenderPass pass;
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} depth_decomp[MAX_SAMPLES_LOG2];
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VkDescriptorSetLayout expand_depth_stencil_compute_ds_layout;
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VkPipelineLayout expand_depth_stencil_compute_p_layout;
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VkPipeline expand_depth_stencil_compute_pipeline;
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struct {
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VkPipelineLayout p_layout;
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VkPipeline cmask_eliminate_pipeline;
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