Qiang Yu 45826e42c5 ac,aco: move gfx10 ngg prim count zero workaround to nir ... To simplify both llvm and aco backend and remove unnecessary workaround code where prim count is known to be not zero. Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Qiang Yu <yuq825@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22381>		2023-04-13 08:12:03 +00:00
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addrlib	amd: update addrlib	2023-03-29 20:36:09 +00:00
ci	radv: fix pipeline creation feedback with imported graphics libs	2023-04-12 15:03:42 +00:00
common	ac,aco: move gfx10 ngg prim count zero workaround to nir	2023-04-13 08:12:03 +00:00
compiler	ac,aco: move gfx10 ngg prim count zero workaround to nir	2023-04-13 08:12:03 +00:00
drm-shim	…
llvm	ac,aco: move gfx10 ngg prim count zero workaround to nir	2023-04-13 08:12:03 +00:00
registers	amd/registers: use gfx9 packet definitions for gfx940	2023-04-06 15:00:54 +00:00
vulkan	radv: cleanup after splitting radv_pipeline.c	2023-04-13 02:21:44 +00:00
.clang-format	amd: Add radv_foreach_stage to ForEachMacros.	2023-03-27 08:29:35 +00:00
meson.build	…