mesa/src/freedreno
Connor Abbott 0f7392147d ir3/ra: Sanitize parallel copy flags better
For pcopies we only care about the register's type, i.e. whether its a
half-register and whether it's an array (plus its size). Copying over
other flags like IR3_REG_RELATIV just leads to sadness and validator
assertions.

Fixes: 0ffcb19b9d ("ir3: Rewrite register allocation")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14107>
(cherry picked from commit ab0ed4ff3f)
2022-03-10 23:24:02 +00:00
..
.gitlab-ci freedreno/a5xx,a6xx: rename MSAA_ENABLE to LINE_MODE in GRAS_SU_CNTL 2021-10-13 12:18:01 +00:00
afuc freedreno/afuc: Disable the disassembler on 32-bit builds. 2022-01-12 19:54:24 +00:00
ci ir3/nir: Fix 1d array readonly images 2022-03-10 23:23:57 +00:00
common freedreno, turnip: Set TPL1_DBG_ECO_CNTL better 2021-09-21 09:08:20 +00:00
computerator freedreno/computerator/a4xx: Fix enum mismatch warning 2021-09-18 20:24:49 +00:00
decode freedreno/tools: Fix build failure when cffdump isn't built but tests are. 2021-10-05 00:06:14 +00:00
drm freedreno/drm: Move pipe unref after fence removal 2021-10-08 07:40:14 +00:00
drm-shim
ds freedreno: Add valgrind dependency. 2021-10-11 19:20:23 +00:00
fdl freedreno/a6xx: Add support for A/XRGB1555 formats. 2021-10-05 20:09:17 +00:00
ir2
ir3 ir3/ra: Sanitize parallel copy flags better 2022-03-10 23:24:02 +00:00
isa ir3/freedreno: handle non-uniform a1en instructions 2021-10-12 17:43:52 +00:00
perfcntrs freedreno/all: Introduce fd_dev_id 2021-08-06 18:51:50 +00:00
registers freedreno/a5xx,a6xx: rename MSAA_ENABLE to LINE_MODE in GRAS_SU_CNTL 2021-10-13 12:18:01 +00:00
rnn freedreno: Move the headergen2 test to be meson unit tests. 2021-10-01 23:16:04 +00:00
vulkan turnip: Use LATE_Z when there might be depth/stencil feedback loop 2022-03-10 23:23:56 +00:00
.clang-format
.dir-locals.el
.editorconfig
meson.build