mirror of https://gitlab.freedesktop.org/mesa/mesa
158 lines
4.4 KiB
C
158 lines
4.4 KiB
C
/*
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* Copyright © 2019 Valve Corporation.
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*
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* SPDX-License-Identifier: MIT
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*/
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#ifndef RADV_SHADER_ARGS_H
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#define RADV_SHADER_ARGS_H
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#include "compiler/shader_enums.h"
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#include "util/list.h"
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#include "util/macros.h"
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#include "ac_shader_args.h"
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#include "amd_family.h"
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#include "radv_constants.h"
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enum radv_ud_index {
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AC_UD_SCRATCH_RING_OFFSETS = 0,
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AC_UD_PUSH_CONSTANTS = 1,
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AC_UD_INLINE_PUSH_CONSTANTS = 2,
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AC_UD_INDIRECT_DESCRIPTOR_SETS = 3,
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AC_UD_VIEW_INDEX = 4,
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AC_UD_STREAMOUT_BUFFERS = 5,
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AC_UD_SHADER_QUERY_STATE = 6,
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AC_UD_NGG_PROVOKING_VTX = 7,
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AC_UD_NGG_CULLING_SETTINGS = 8,
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AC_UD_NGG_VIEWPORT = 9,
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AC_UD_NGG_LDS_LAYOUT = 10,
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AC_UD_VGT_ESGS_RING_ITEMSIZE = 11,
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AC_UD_FORCE_VRS_RATES = 12,
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AC_UD_TASK_RING_ENTRY = 13,
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AC_UD_NUM_VERTS_PER_PRIM = 14,
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AC_UD_NEXT_STAGE_PC = 15,
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AC_UD_EPILOG_PC = 16,
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AC_UD_SHADER_START = 17,
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AC_UD_VS_VERTEX_BUFFERS = AC_UD_SHADER_START,
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AC_UD_VS_BASE_VERTEX_START_INSTANCE,
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AC_UD_VS_PROLOG_INPUTS,
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AC_UD_VS_MAX_UD,
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AC_UD_PS_STATE,
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AC_UD_PS_MAX_UD,
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AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START,
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AC_UD_CS_SBT_DESCRIPTORS,
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AC_UD_CS_RAY_LAUNCH_SIZE_ADDR,
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AC_UD_CS_RAY_DYNAMIC_CALLABLE_STACK_BASE,
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AC_UD_CS_TRAVERSAL_SHADER_ADDR,
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AC_UD_CS_TASK_RING_OFFSETS,
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AC_UD_CS_TASK_DRAW_ID,
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AC_UD_CS_TASK_IB,
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AC_UD_CS_MAX_UD,
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AC_UD_GS_MAX_UD,
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AC_UD_TCS_OFFCHIP_LAYOUT = AC_UD_VS_MAX_UD,
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AC_UD_TCS_MAX_UD,
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/* We might not know the previous stage when compiling a geometry shader, so we just
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* declare both TES and VS user SGPRs.
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*/
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AC_UD_TES_MAX_UD = AC_UD_TCS_MAX_UD,
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AC_UD_MAX_UD = AC_UD_CS_MAX_UD,
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};
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struct radv_userdata_info {
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int8_t sgpr_idx;
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uint8_t num_sgprs;
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};
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struct radv_userdata_locations {
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struct radv_userdata_info descriptor_sets[MAX_SETS];
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struct radv_userdata_info shader_data[AC_UD_MAX_UD];
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uint32_t descriptor_sets_enabled;
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};
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struct radv_shader_args {
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struct ac_shader_args ac;
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struct ac_arg descriptor_sets[MAX_SETS];
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/* User data 2/3. same as ring_offsets but for task shaders. */
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struct ac_arg task_ring_offsets;
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/* Streamout */
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struct ac_arg streamout_buffers;
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/* Emulated query */
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struct ac_arg shader_query_state;
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/* NGG */
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struct ac_arg ngg_provoking_vtx;
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struct ac_arg ngg_lds_layout;
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/* NGG GS */
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struct ac_arg ngg_culling_settings;
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struct ac_arg ngg_viewport_scale[2];
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struct ac_arg ngg_viewport_translate[2];
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/* Fragment shaders */
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struct ac_arg ps_state;
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struct ac_arg prolog_inputs;
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struct ac_arg vs_inputs[MAX_VERTEX_ATTRIBS];
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/* PS epilogs */
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struct ac_arg colors[MAX_RTS];
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struct ac_arg depth;
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struct ac_arg stencil;
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struct ac_arg sample_mask;
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/* TCS */
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/* # [0:6] = the number of tessellation patches minus one, max = 127
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* # [7:11] = the number of output patch control points minus one, max = 31
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* # [12:16] = the number of input patch control points minus one, max = 31
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* # [17:22] = the number of LS outputs, up to 32
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* # [23:28] = the number of HS per-vertex outputs, up to 32
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* # [29:30] = tess_primitive_mode
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* # [31] = whether TES reads tess factors
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*/
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struct ac_arg tcs_offchip_layout;
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/* GS */
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struct ac_arg vgt_esgs_ring_itemsize;
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/* NGG VS streamout */
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struct ac_arg num_verts_per_prim;
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/* For non-monolithic VS or TES on GFX9+. */
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struct ac_arg next_stage_pc;
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/* PS/TCS epilogs PC. */
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struct ac_arg epilog_pc;
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struct radv_userdata_locations user_sgprs_locs;
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unsigned num_user_sgprs;
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bool explicit_scratch_args;
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bool remap_spi_ps_input;
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bool load_grid_size_from_user_sgpr;
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};
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static inline struct radv_shader_args *
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radv_shader_args_from_ac(struct ac_shader_args *args)
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{
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return container_of(args, struct radv_shader_args, ac);
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}
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struct radv_graphics_state_key;
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struct radv_shader_info;
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struct radv_ps_epilog_key;
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struct radv_device;
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void radv_declare_shader_args(const struct radv_device *device, const struct radv_graphics_state_key *gfx_state,
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const struct radv_shader_info *info, gl_shader_stage stage,
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gl_shader_stage previous_stage, struct radv_shader_args *args);
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void radv_declare_ps_epilog_args(const struct radv_device *device, const struct radv_ps_epilog_key *key,
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struct radv_shader_args *args);
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void radv_declare_rt_shader_args(enum amd_gfx_level gfx_level, struct radv_shader_args *args);
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#endif /* RADV_SHADER_ARGS_H */
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