mirror of https://gitlab.freedesktop.org/mesa/mesa
666 lines
22 KiB
C
666 lines
22 KiB
C
/*
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* Copyright © 2016 Red Hat.
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* Copyright © 2016 Bas Nieuwenhuizen
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*
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* based in part on anv driver which is:
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* Copyright © 2015 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*/
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#ifndef RADV_PIPELINE_GRAPHICS_H
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#define RADV_PIPELINE_GRAPHICS_H
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#include "sid.h"
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#include "radv_descriptor_set.h"
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#include "radv_pipeline.h"
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#include "radv_shader.h"
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#include "vk_graphics_state.h"
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struct radv_sample_locations_state {
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VkSampleCountFlagBits per_pixel;
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VkExtent2D grid_size;
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uint32_t count;
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VkSampleLocationEXT locations[MAX_SAMPLE_LOCATIONS];
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};
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struct radv_dynamic_state {
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struct vk_dynamic_graphics_state vk;
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/**
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* Bitmask of (1ull << VK_DYNAMIC_STATE_*).
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* Defines the set of saved dynamic state.
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*/
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uint64_t mask;
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struct {
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struct {
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float scale[3];
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float translate[3];
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} xform[MAX_VIEWPORTS];
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} hw_vp;
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struct radv_sample_locations_state sample_location;
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VkImageAspectFlags feedback_loop_aspects;
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};
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struct radv_multisample_state {
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bool sample_shading_enable;
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float min_sample_shading;
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};
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struct radv_ia_multi_vgt_param_helpers {
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uint32_t base;
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bool partial_es_wave;
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bool ia_switch_on_eoi;
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bool partial_vs_wave;
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};
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struct radv_sqtt_shaders_reloc {
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struct radeon_winsys_bo *bo;
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union radv_shader_arena_block *alloc;
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uint64_t va[MESA_VULKAN_SHADER_STAGES];
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};
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struct radv_graphics_pipeline {
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struct radv_pipeline base;
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bool uses_drawid;
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bool uses_baseinstance;
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/* Whether the pipeline forces per-vertex VRS (GFX10.3+). */
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bool force_vrs_per_vertex;
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/* Whether the pipeline uses NGG (GFX10+). */
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bool is_ngg;
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bool has_ngg_culling;
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uint8_t vtx_emit_num;
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uint32_t vtx_base_sgpr;
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uint64_t dynamic_states;
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uint64_t needed_dynamic_state;
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VkShaderStageFlags active_stages;
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/* Used for rbplus */
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uint32_t col_format_non_compacted;
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struct radv_dynamic_state dynamic_state;
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struct radv_vs_input_state vs_input_state;
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struct radv_multisample_state ms;
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struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
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uint32_t binding_stride[MAX_VBS];
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uint8_t attrib_bindings[MAX_VERTEX_ATTRIBS];
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uint32_t attrib_ends[MAX_VERTEX_ATTRIBS];
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uint32_t attrib_index_offset[MAX_VERTEX_ATTRIBS];
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uint32_t db_render_control;
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/* Last pre-PS API stage */
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gl_shader_stage last_vgt_api_stage;
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unsigned rast_prim;
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/* For vk_graphics_pipeline_state */
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void *state_data;
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/* Custom blend mode for internal operations. */
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unsigned custom_blend_mode;
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/* Whether the pipeline uses out-of-order rasterization. */
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bool uses_out_of_order_rast;
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/* Whether the pipeline uses a VRS attachment. */
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bool uses_vrs_attachment;
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/* For graphics pipeline library */
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bool retain_shaders;
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/* For relocation of shaders with RGP. */
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struct radv_sqtt_shaders_reloc *sqtt_shaders_reloc;
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};
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RADV_DECL_PIPELINE_DOWNCAST(graphics, RADV_PIPELINE_GRAPHICS)
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struct radv_retained_shaders {
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struct {
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void *serialized_nir;
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size_t serialized_nir_size;
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unsigned char shader_sha1[SHA1_DIGEST_LENGTH];
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struct radv_shader_stage_key key;
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} stages[MESA_VULKAN_SHADER_STAGES];
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};
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struct radv_graphics_lib_pipeline {
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struct radv_graphics_pipeline base;
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struct radv_pipeline_layout layout;
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struct vk_graphics_pipeline_state graphics_state;
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VkGraphicsPipelineLibraryFlagsEXT lib_flags;
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struct radv_retained_shaders retained_shaders;
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void *mem_ctx;
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unsigned stage_count;
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VkPipelineShaderStageCreateInfo *stages;
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struct radv_shader_stage_key stage_keys[MESA_VULKAN_SHADER_STAGES];
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};
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RADV_DECL_PIPELINE_DOWNCAST(graphics_lib, RADV_PIPELINE_GRAPHICS_LIB)
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static inline bool
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radv_pipeline_has_stage(const struct radv_graphics_pipeline *pipeline, gl_shader_stage stage)
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{
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return pipeline->base.shaders[stage];
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}
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static inline uint32_t
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radv_conv_prim_to_gs_out(uint32_t topology, bool is_ngg)
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{
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switch (topology) {
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case V_008958_DI_PT_POINTLIST:
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case V_008958_DI_PT_PATCH:
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return V_028A6C_POINTLIST;
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case V_008958_DI_PT_LINELIST:
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case V_008958_DI_PT_LINESTRIP:
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case V_008958_DI_PT_LINELIST_ADJ:
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case V_008958_DI_PT_LINESTRIP_ADJ:
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return V_028A6C_LINESTRIP;
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case V_008958_DI_PT_TRILIST:
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case V_008958_DI_PT_TRISTRIP:
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case V_008958_DI_PT_TRIFAN:
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case V_008958_DI_PT_TRILIST_ADJ:
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case V_008958_DI_PT_TRISTRIP_ADJ:
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return V_028A6C_TRISTRIP;
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case V_008958_DI_PT_RECTLIST:
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return is_ngg ? V_028A6C_RECTLIST : V_028A6C_TRISTRIP;
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default:
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assert(0);
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return 0;
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}
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}
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static inline uint32_t
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radv_translate_prim(unsigned topology)
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{
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switch (topology) {
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case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
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return V_008958_DI_PT_POINTLIST;
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case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
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return V_008958_DI_PT_LINELIST;
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case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
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return V_008958_DI_PT_LINESTRIP;
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case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
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return V_008958_DI_PT_TRILIST;
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case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
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return V_008958_DI_PT_TRISTRIP;
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case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
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return V_008958_DI_PT_TRIFAN;
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case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
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return V_008958_DI_PT_LINELIST_ADJ;
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case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
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return V_008958_DI_PT_LINESTRIP_ADJ;
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case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
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return V_008958_DI_PT_TRILIST_ADJ;
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case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
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return V_008958_DI_PT_TRISTRIP_ADJ;
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case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
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return V_008958_DI_PT_PATCH;
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default:
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unreachable("unhandled primitive type");
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}
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}
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static inline bool
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radv_prim_is_points_or_lines(unsigned topology)
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{
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switch (topology) {
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case V_008958_DI_PT_POINTLIST:
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case V_008958_DI_PT_LINELIST:
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case V_008958_DI_PT_LINESTRIP:
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case V_008958_DI_PT_LINELIST_ADJ:
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case V_008958_DI_PT_LINESTRIP_ADJ:
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return true;
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default:
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return false;
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}
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}
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static inline bool
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radv_rast_prim_is_point(unsigned rast_prim)
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{
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return rast_prim == V_028A6C_POINTLIST;
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}
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static inline bool
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radv_rast_prim_is_line(unsigned rast_prim)
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{
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return rast_prim == V_028A6C_LINESTRIP;
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}
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static inline bool
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radv_rast_prim_is_points_or_lines(unsigned rast_prim)
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{
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return radv_rast_prim_is_point(rast_prim) || radv_rast_prim_is_line(rast_prim);
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}
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static inline bool
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radv_polygon_mode_is_point(unsigned polygon_mode)
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{
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return polygon_mode == V_028814_X_DRAW_POINTS;
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}
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static inline bool
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radv_polygon_mode_is_line(unsigned polygon_mode)
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{
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return polygon_mode == V_028814_X_DRAW_LINES;
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}
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static inline bool
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radv_polygon_mode_is_points_or_lines(unsigned polygon_mode)
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{
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return radv_polygon_mode_is_point(polygon_mode) || radv_polygon_mode_is_line(polygon_mode);
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}
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static inline bool
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radv_primitive_topology_is_line_list(unsigned primitive_topology)
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{
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return primitive_topology == V_008958_DI_PT_LINELIST || primitive_topology == V_008958_DI_PT_LINELIST_ADJ;
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}
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static inline unsigned
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radv_get_num_vertices_per_prim(const struct radv_graphics_state_key *gfx_state)
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{
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if (gfx_state->ia.topology == V_008958_DI_PT_NONE) {
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/* When the topology is unknown (with graphics pipeline library), return the maximum number of
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* vertices per primitives for VS. This is used to lower NGG (the HW will ignore the extra
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* bits for points/lines) and also to enable NGG culling unconditionally (it will be disabled
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* dynamically for points/lines).
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*/
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return 3;
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} else {
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/* Need to add 1, because: V_028A6C_POINTLIST=0, V_028A6C_LINESTRIP=1, V_028A6C_TRISTRIP=2, etc. */
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return radv_conv_prim_to_gs_out(gfx_state->ia.topology, false) + 1;
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}
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}
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static inline uint32_t
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radv_translate_fill(VkPolygonMode func)
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{
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switch (func) {
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case VK_POLYGON_MODE_FILL:
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return V_028814_X_DRAW_TRIANGLES;
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case VK_POLYGON_MODE_LINE:
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return V_028814_X_DRAW_LINES;
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case VK_POLYGON_MODE_POINT:
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return V_028814_X_DRAW_POINTS;
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default:
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assert(0);
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return V_028814_X_DRAW_POINTS;
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}
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}
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static inline uint32_t
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radv_translate_stencil_op(enum VkStencilOp op)
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{
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switch (op) {
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case VK_STENCIL_OP_KEEP:
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return V_02842C_STENCIL_KEEP;
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case VK_STENCIL_OP_ZERO:
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return V_02842C_STENCIL_ZERO;
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case VK_STENCIL_OP_REPLACE:
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return V_02842C_STENCIL_REPLACE_TEST;
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case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
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return V_02842C_STENCIL_ADD_CLAMP;
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case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
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return V_02842C_STENCIL_SUB_CLAMP;
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case VK_STENCIL_OP_INVERT:
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return V_02842C_STENCIL_INVERT;
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case VK_STENCIL_OP_INCREMENT_AND_WRAP:
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return V_02842C_STENCIL_ADD_WRAP;
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case VK_STENCIL_OP_DECREMENT_AND_WRAP:
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return V_02842C_STENCIL_SUB_WRAP;
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default:
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return 0;
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}
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}
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static inline uint32_t
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radv_translate_blend_logic_op(VkLogicOp op)
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{
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switch (op) {
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case VK_LOGIC_OP_CLEAR:
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return V_028808_ROP3_CLEAR;
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case VK_LOGIC_OP_AND:
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return V_028808_ROP3_AND;
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case VK_LOGIC_OP_AND_REVERSE:
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return V_028808_ROP3_AND_REVERSE;
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case VK_LOGIC_OP_COPY:
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return V_028808_ROP3_COPY;
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case VK_LOGIC_OP_AND_INVERTED:
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return V_028808_ROP3_AND_INVERTED;
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case VK_LOGIC_OP_NO_OP:
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return V_028808_ROP3_NO_OP;
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case VK_LOGIC_OP_XOR:
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return V_028808_ROP3_XOR;
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case VK_LOGIC_OP_OR:
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return V_028808_ROP3_OR;
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case VK_LOGIC_OP_NOR:
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return V_028808_ROP3_NOR;
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case VK_LOGIC_OP_EQUIVALENT:
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return V_028808_ROP3_EQUIVALENT;
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case VK_LOGIC_OP_INVERT:
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return V_028808_ROP3_INVERT;
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case VK_LOGIC_OP_OR_REVERSE:
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return V_028808_ROP3_OR_REVERSE;
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case VK_LOGIC_OP_COPY_INVERTED:
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return V_028808_ROP3_COPY_INVERTED;
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case VK_LOGIC_OP_OR_INVERTED:
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return V_028808_ROP3_OR_INVERTED;
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case VK_LOGIC_OP_NAND:
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return V_028808_ROP3_NAND;
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case VK_LOGIC_OP_SET:
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return V_028808_ROP3_SET;
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default:
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unreachable("Unhandled logic op");
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}
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}
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static inline uint32_t
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radv_translate_blend_function(VkBlendOp op)
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{
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switch (op) {
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case VK_BLEND_OP_ADD:
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return V_028780_COMB_DST_PLUS_SRC;
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case VK_BLEND_OP_SUBTRACT:
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return V_028780_COMB_SRC_MINUS_DST;
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case VK_BLEND_OP_REVERSE_SUBTRACT:
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return V_028780_COMB_DST_MINUS_SRC;
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case VK_BLEND_OP_MIN:
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return V_028780_COMB_MIN_DST_SRC;
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case VK_BLEND_OP_MAX:
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return V_028780_COMB_MAX_DST_SRC;
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default:
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return 0;
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}
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}
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static inline uint32_t
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radv_translate_blend_factor(enum amd_gfx_level gfx_level, VkBlendFactor factor)
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{
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switch (factor) {
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case VK_BLEND_FACTOR_ZERO:
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return V_028780_BLEND_ZERO;
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case VK_BLEND_FACTOR_ONE:
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return V_028780_BLEND_ONE;
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case VK_BLEND_FACTOR_SRC_COLOR:
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return V_028780_BLEND_SRC_COLOR;
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case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
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return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
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case VK_BLEND_FACTOR_DST_COLOR:
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return V_028780_BLEND_DST_COLOR;
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case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
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return V_028780_BLEND_ONE_MINUS_DST_COLOR;
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case VK_BLEND_FACTOR_SRC_ALPHA:
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return V_028780_BLEND_SRC_ALPHA;
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case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
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return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
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case VK_BLEND_FACTOR_DST_ALPHA:
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return V_028780_BLEND_DST_ALPHA;
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case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
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return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
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case VK_BLEND_FACTOR_CONSTANT_COLOR:
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return gfx_level >= GFX11 ? V_028780_BLEND_CONSTANT_COLOR_GFX11 : V_028780_BLEND_CONSTANT_COLOR_GFX6;
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case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
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return gfx_level >= GFX11 ? V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR_GFX11
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: V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR_GFX6;
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case VK_BLEND_FACTOR_CONSTANT_ALPHA:
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return gfx_level >= GFX11 ? V_028780_BLEND_CONSTANT_ALPHA_GFX11 : V_028780_BLEND_CONSTANT_ALPHA_GFX6;
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case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
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return gfx_level >= GFX11 ? V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA_GFX11
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: V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA_GFX6;
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case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
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return V_028780_BLEND_SRC_ALPHA_SATURATE;
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case VK_BLEND_FACTOR_SRC1_COLOR:
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return gfx_level >= GFX11 ? V_028780_BLEND_SRC1_COLOR_GFX11 : V_028780_BLEND_SRC1_COLOR_GFX6;
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case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
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return gfx_level >= GFX11 ? V_028780_BLEND_INV_SRC1_COLOR_GFX11 : V_028780_BLEND_INV_SRC1_COLOR_GFX6;
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case VK_BLEND_FACTOR_SRC1_ALPHA:
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return gfx_level >= GFX11 ? V_028780_BLEND_SRC1_ALPHA_GFX11 : V_028780_BLEND_SRC1_ALPHA_GFX6;
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case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
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return gfx_level >= GFX11 ? V_028780_BLEND_INV_SRC1_ALPHA_GFX11 : V_028780_BLEND_INV_SRC1_ALPHA_GFX6;
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default:
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return 0;
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}
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}
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static inline uint32_t
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radv_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
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{
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switch (factor) {
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case VK_BLEND_FACTOR_ZERO:
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return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
|
|
case VK_BLEND_FACTOR_ONE:
|
|
return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
|
|
case VK_BLEND_FACTOR_SRC_COLOR:
|
|
return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
|
|
case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
|
|
return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
|
|
case VK_BLEND_FACTOR_SRC_ALPHA:
|
|
return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
|
|
case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
|
|
return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
|
|
case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
|
|
return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
|
|
default:
|
|
return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
|
|
}
|
|
}
|
|
|
|
static inline uint32_t
|
|
radv_translate_blend_opt_function(VkBlendOp op)
|
|
{
|
|
switch (op) {
|
|
case VK_BLEND_OP_ADD:
|
|
return V_028760_OPT_COMB_ADD;
|
|
case VK_BLEND_OP_SUBTRACT:
|
|
return V_028760_OPT_COMB_SUBTRACT;
|
|
case VK_BLEND_OP_REVERSE_SUBTRACT:
|
|
return V_028760_OPT_COMB_REVSUBTRACT;
|
|
case VK_BLEND_OP_MIN:
|
|
return V_028760_OPT_COMB_MIN;
|
|
case VK_BLEND_OP_MAX:
|
|
return V_028760_OPT_COMB_MAX;
|
|
default:
|
|
return V_028760_OPT_COMB_BLEND_DISABLED;
|
|
}
|
|
}
|
|
|
|
static inline bool
|
|
radv_blend_factor_uses_dst(VkBlendFactor factor)
|
|
{
|
|
return factor == VK_BLEND_FACTOR_DST_COLOR || factor == VK_BLEND_FACTOR_DST_ALPHA ||
|
|
factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE || factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
|
|
factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
|
|
}
|
|
|
|
static inline bool
|
|
radv_is_dual_src(VkBlendFactor factor)
|
|
{
|
|
switch (factor) {
|
|
case VK_BLEND_FACTOR_SRC1_COLOR:
|
|
case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
|
|
case VK_BLEND_FACTOR_SRC1_ALPHA:
|
|
case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
static ALWAYS_INLINE bool
|
|
radv_can_enable_dual_src(const struct vk_color_blend_attachment_state *att)
|
|
{
|
|
VkBlendOp eqRGB = att->color_blend_op;
|
|
VkBlendFactor srcRGB = att->src_color_blend_factor;
|
|
VkBlendFactor dstRGB = att->dst_color_blend_factor;
|
|
VkBlendOp eqA = att->alpha_blend_op;
|
|
VkBlendFactor srcA = att->src_alpha_blend_factor;
|
|
VkBlendFactor dstA = att->dst_alpha_blend_factor;
|
|
bool eqRGB_minmax = eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX;
|
|
bool eqA_minmax = eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX;
|
|
|
|
if (!eqRGB_minmax && (radv_is_dual_src(srcRGB) || radv_is_dual_src(dstRGB)))
|
|
return true;
|
|
if (!eqA_minmax && (radv_is_dual_src(srcA) || radv_is_dual_src(dstA)))
|
|
return true;
|
|
return false;
|
|
}
|
|
|
|
static inline void
|
|
radv_normalize_blend_factor(VkBlendOp op, VkBlendFactor *src_factor, VkBlendFactor *dst_factor)
|
|
{
|
|
if (op == VK_BLEND_OP_MIN || op == VK_BLEND_OP_MAX) {
|
|
*src_factor = VK_BLEND_FACTOR_ONE;
|
|
*dst_factor = VK_BLEND_FACTOR_ONE;
|
|
}
|
|
}
|
|
|
|
bool radv_pipeline_has_ngg(const struct radv_graphics_pipeline *pipeline);
|
|
|
|
bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline);
|
|
|
|
void radv_blend_remove_dst(VkBlendOp *func, VkBlendFactor *src_factor, VkBlendFactor *dst_factor,
|
|
VkBlendFactor expected_dst, VkBlendFactor replacement_src);
|
|
|
|
unsigned radv_compact_spi_shader_col_format(const struct radv_shader *ps, uint32_t spi_shader_col_format);
|
|
|
|
unsigned radv_format_meta_fs_key(struct radv_device *device, VkFormat format);
|
|
|
|
struct radv_ia_multi_vgt_param_helpers radv_compute_ia_multi_vgt_param(const struct radv_device *device,
|
|
struct radv_shader *const *shaders);
|
|
|
|
void radv_get_viewport_xform(const VkViewport *viewport, float scale[3], float translate[3]);
|
|
|
|
struct radv_shader *radv_get_shader(struct radv_shader *const *shaders, gl_shader_stage stage);
|
|
|
|
struct radv_ps_epilog_state {
|
|
uint8_t color_attachment_count;
|
|
VkFormat color_attachment_formats[MAX_RTS];
|
|
|
|
uint32_t color_write_mask;
|
|
uint32_t color_blend_enable;
|
|
|
|
uint32_t colors_written;
|
|
bool mrt0_is_dual_src;
|
|
bool export_depth;
|
|
bool export_stencil;
|
|
bool export_sample_mask;
|
|
bool alpha_to_coverage_via_mrtz;
|
|
bool alpha_to_one;
|
|
uint8_t need_src_alpha;
|
|
};
|
|
|
|
struct radv_ps_epilog_key radv_generate_ps_epilog_key(const struct radv_device *device,
|
|
const struct radv_ps_epilog_state *state);
|
|
|
|
void radv_graphics_shaders_compile(struct radv_device *device, struct vk_pipeline_cache *cache,
|
|
struct radv_shader_stage *stages, const struct radv_graphics_state_key *gfx_state,
|
|
bool keep_executable_info, bool keep_statistic_info, bool is_internal,
|
|
struct radv_retained_shaders *retained_shaders, bool noop_fs,
|
|
struct radv_shader **shaders, struct radv_shader_binary **binaries,
|
|
struct radv_shader **gs_copy_shader, struct radv_shader_binary **gs_copy_binary);
|
|
|
|
void radv_emit_blend_state(struct radeon_cmdbuf *ctx_cs, const struct radv_shader *ps, uint32_t spi_shader_col_format,
|
|
uint32_t cb_shader_mask);
|
|
|
|
void radv_emit_vgt_gs_mode(const struct radv_device *device, struct radeon_cmdbuf *ctx_cs,
|
|
const struct radv_shader *last_vgt_api_shader);
|
|
|
|
void radv_emit_vertex_shader(const struct radv_device *device, struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf *cs,
|
|
const struct radv_shader *vs, const struct radv_shader *next_stage);
|
|
|
|
void radv_emit_tess_ctrl_shader(const struct radv_device *device, struct radeon_cmdbuf *cs,
|
|
const struct radv_shader *tcs);
|
|
|
|
void radv_emit_tess_eval_shader(const struct radv_device *device, struct radeon_cmdbuf *ctx_cs,
|
|
struct radeon_cmdbuf *cs, const struct radv_shader *tes, const struct radv_shader *gs);
|
|
|
|
void radv_emit_geometry_shader(const struct radv_device *device, struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf *cs,
|
|
const struct radv_shader *gs, const struct radv_shader *es,
|
|
const struct radv_shader *gs_copy_shader);
|
|
|
|
void radv_emit_mesh_shader(const struct radv_device *device, struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf *cs,
|
|
const struct radv_shader *ms);
|
|
|
|
void radv_emit_ps_inputs(const struct radv_device *device, struct radeon_cmdbuf *cs,
|
|
const struct radv_shader *last_vgt_shader, const struct radv_shader *ps);
|
|
|
|
void radv_emit_fragment_shader(const struct radv_device *device, struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf *cs,
|
|
const struct radv_shader *ps);
|
|
|
|
struct radv_vgt_shader_key {
|
|
uint8_t tess : 1;
|
|
uint8_t gs : 1;
|
|
uint8_t mesh_scratch_ring : 1;
|
|
uint8_t mesh : 1;
|
|
uint8_t ngg_passthrough : 1;
|
|
uint8_t ngg : 1; /* gfx10+ */
|
|
uint8_t ngg_streamout : 1;
|
|
uint8_t hs_wave32 : 1;
|
|
uint8_t gs_wave32 : 1;
|
|
uint8_t vs_wave32 : 1;
|
|
};
|
|
|
|
void radv_emit_vgt_reuse(const struct radv_device *device, struct radeon_cmdbuf *ctx_cs, const struct radv_shader *tes,
|
|
const struct radv_vgt_shader_key *key);
|
|
|
|
struct radv_vgt_shader_key radv_get_vgt_shader_key(const struct radv_device *device, struct radv_shader **shaders,
|
|
const struct radv_shader *gs_copy_shader);
|
|
|
|
void radv_emit_vgt_shader_config(const struct radv_device *device, struct radeon_cmdbuf *ctx_cs,
|
|
const struct radv_vgt_shader_key *key);
|
|
|
|
void radv_emit_vgt_gs_out(const struct radv_device *device, struct radeon_cmdbuf *ctx_cs,
|
|
uint32_t vgt_gs_out_prim_type);
|
|
|
|
void gfx103_emit_vgt_draw_payload_cntl(struct radeon_cmdbuf *ctx_cs, const struct radv_shader *mesh_shader,
|
|
bool enable_vrs);
|
|
|
|
void gfx103_emit_vrs_state(const struct radv_device *device, struct radeon_cmdbuf *ctx_cs, const struct radv_shader *ps,
|
|
bool enable_vrs, bool enable_vrs_coarse_shading, bool force_vrs_per_vertex);
|
|
|
|
uint32_t radv_get_vgt_gs_out(struct radv_shader **shaders, uint32_t primitive_topology);
|
|
|
|
bool radv_needs_null_export_workaround(const struct radv_device *device, const struct radv_shader *ps,
|
|
unsigned custom_blend_mode);
|
|
|
|
struct radv_graphics_pipeline_create_info {
|
|
bool use_rectlist;
|
|
bool db_depth_clear;
|
|
bool db_stencil_clear;
|
|
bool depth_compress_disable;
|
|
bool stencil_compress_disable;
|
|
bool resummarize_enable;
|
|
uint32_t custom_blend_mode;
|
|
};
|
|
|
|
VkResult radv_graphics_pipeline_create(VkDevice device, VkPipelineCache cache,
|
|
const VkGraphicsPipelineCreateInfo *pCreateInfo,
|
|
const struct radv_graphics_pipeline_create_info *extra,
|
|
const VkAllocationCallbacks *alloc, VkPipeline *pPipeline);
|
|
|
|
void radv_destroy_graphics_pipeline(struct radv_device *device, struct radv_graphics_pipeline *pipeline);
|
|
|
|
void radv_destroy_graphics_lib_pipeline(struct radv_device *device, struct radv_graphics_lib_pipeline *pipeline);
|
|
|
|
#endif /* RADV_PIPELINE_GRAPHICS_H */
|