mirror of https://gitlab.freedesktop.org/mesa/mesa
257 lines
7.2 KiB
C
257 lines
7.2 KiB
C
/*
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* Copyright © 2016 Red Hat.
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* Copyright © 2016 Bas Nieuwenhuizen
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*
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* based in part on anv driver which is:
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* Copyright © 2015 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*/
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#ifndef RADV_PHYSICAL_DEVICE_H
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#define RADV_PHYSICAL_DEVICE_H
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#include "ac_gpu_info.h"
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#include "ac_perfcounter.h"
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#include "radv_instance.h"
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#include "radv_queue.h"
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#include "radv_radeon_winsys.h"
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#include "wsi_common.h"
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#include "nir.h"
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#include "vk_physical_device.h"
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#ifndef _WIN32
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#include <amdgpu.h>
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#include <xf86drm.h>
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#endif
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/* The "RAW" clocks on Linux are called "FAST" on FreeBSD */
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#if !defined(CLOCK_MONOTONIC_RAW) && defined(CLOCK_MONOTONIC_FAST)
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#define CLOCK_MONOTONIC_RAW CLOCK_MONOTONIC_FAST
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#endif
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struct radv_binning_settings {
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unsigned context_states_per_bin; /* allowed range: [1, 6] */
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unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
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unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
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};
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struct radv_physical_device_cache_key {
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enum radeon_family family;
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uint32_t ptr_size;
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uint32_t conformant_trunc_coord : 1;
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uint32_t clear_lds : 1;
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uint32_t cs_wave32 : 1;
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uint32_t disable_aniso_single_level : 1;
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uint32_t disable_shrink_image_store : 1;
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uint32_t disable_sinking_load_input_fs : 1;
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uint32_t dual_color_blend_by_location : 1;
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uint32_t emulate_rt : 1;
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uint32_t ge_wave32 : 1;
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uint32_t invariant_geom : 1;
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uint32_t lower_discard_to_demote : 1;
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uint32_t mesh_fast_launch_2 : 1;
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uint32_t no_fmask : 1;
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uint32_t no_ngg_gs : 1;
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uint32_t no_rt : 1;
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uint32_t ps_wave32 : 1;
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uint32_t rt_wave64 : 1;
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uint32_t split_fma : 1;
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uint32_t ssbo_non_uniform : 1;
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uint32_t tex_non_uniform : 1;
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uint32_t use_llvm : 1;
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uint32_t use_ngg : 1;
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uint32_t use_ngg_culling : 1;
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};
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struct radv_physical_device {
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struct vk_physical_device vk;
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struct radeon_winsys *ws;
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struct radeon_info info;
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char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
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char marketing_name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
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uint8_t driver_uuid[VK_UUID_SIZE];
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uint8_t device_uuid[VK_UUID_SIZE];
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uint8_t cache_uuid[VK_UUID_SIZE];
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int local_fd;
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int master_fd;
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struct wsi_device wsi_device;
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/* Whether DCC should be enabled for MSAA textures. */
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bool dcc_msaa_allowed;
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/* Whether to enable FMASK compression for MSAA textures (GFX6-GFX10.3) */
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bool use_fmask;
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/* Whether to enable NGG. */
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bool use_ngg;
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/* Whether to enable NGG culling. */
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bool use_ngg_culling;
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/* Whether to enable NGG streamout. */
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bool use_ngg_streamout;
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/* Whether to emulate the number of primitives generated by GS. */
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bool emulate_ngg_gs_query_pipeline_stat;
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/* Whether to use GS_FAST_LAUNCH(2) for mesh shaders. */
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bool mesh_fast_launch_2;
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/* Whether to emulate mesh/task shader queries. */
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bool emulate_mesh_shader_queries;
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/* Number of threads per wave. */
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uint8_t ps_wave_size;
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uint8_t cs_wave_size;
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uint8_t ge_wave_size;
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uint8_t rt_wave_size;
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/* Maximum compute shared memory size. */
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uint32_t max_shared_size;
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/* Whether to use the LLVM compiler backend */
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bool use_llvm;
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/* Whether to emulate ETC2 image support on HW without support. */
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bool emulate_etc2;
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/* Whether to emulate ASTC image support on HW without support. */
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bool emulate_astc;
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VkPhysicalDeviceMemoryProperties memory_properties;
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enum radeon_bo_domain memory_domains[VK_MAX_MEMORY_TYPES];
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enum radeon_bo_flag memory_flags[VK_MAX_MEMORY_TYPES];
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unsigned heaps;
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/* Bitmask of memory types that use the 32-bit address space. */
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uint32_t memory_types_32bit;
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#ifndef _WIN32
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int available_nodes;
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drmPciBusInfo bus_info;
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dev_t primary_devid;
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dev_t render_devid;
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#endif
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nir_shader_compiler_options nir_options[MESA_VULKAN_SHADER_STAGES];
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enum radv_queue_family vk_queue_to_radv[RADV_MAX_QUEUE_FAMILIES];
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uint32_t num_queues;
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uint32_t gs_table_depth;
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struct ac_hs_info hs;
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struct ac_task_info task_info;
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struct radv_binning_settings binning_settings;
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/* Performance counters. */
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struct ac_perfcounters ac_perfcounters;
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uint32_t num_perfcounters;
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struct radv_perfcounter_desc *perfcounters;
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struct {
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unsigned data0;
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unsigned data1;
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unsigned cmd;
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unsigned cntl;
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} vid_dec_reg;
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enum amd_ip_type vid_decode_ip;
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uint32_t vid_addr_gfx_mode;
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uint32_t stream_handle_base;
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uint32_t stream_handle_counter;
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uint32_t av1_version;
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struct radv_physical_device_cache_key cache_key;
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};
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VK_DEFINE_HANDLE_CASTS(radv_physical_device, vk.base, VkPhysicalDevice, VK_OBJECT_TYPE_PHYSICAL_DEVICE)
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static inline struct radv_instance *
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radv_physical_device_instance(const struct radv_physical_device *pdev)
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{
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return (struct radv_instance *)pdev->vk.instance;
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}
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static inline bool
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radv_sparse_queue_enabled(const struct radv_physical_device *pdev)
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{
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const struct radv_instance *instance = radv_physical_device_instance(pdev);
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/* Dedicated sparse queue requires VK_QUEUE_SUBMIT_MODE_THREADED, which is incompatible with
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* VK_DEVICE_TIMELINE_MODE_EMULATED. */
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return pdev->info.has_timeline_syncobj && !instance->drirc.legacy_sparse_binding;
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}
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static inline bool
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radv_has_shader_buffer_float_minmax(const struct radv_physical_device *pdev, unsigned bitsize)
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{
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return (pdev->info.gfx_level <= GFX7 && !pdev->use_llvm) || pdev->info.gfx_level == GFX10 ||
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pdev->info.gfx_level == GFX10_3 || (pdev->info.gfx_level == GFX11 && bitsize == 32);
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}
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static inline bool
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radv_has_pops(const struct radv_physical_device *pdev)
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{
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return pdev->info.gfx_level >= GFX9 && !pdev->use_llvm;
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}
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static inline bool
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radv_has_uvd(struct radv_physical_device *pdev)
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{
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enum radeon_family family = pdev->info.family;
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/* Only support UVD on TONGA+ */
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if (family < CHIP_TONGA)
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return false;
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return pdev->info.ip[AMD_IP_UVD].num_queues > 0;
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}
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static inline enum radv_queue_family
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vk_queue_to_radv(const struct radv_physical_device *pdev, int queue_family_index)
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{
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if (queue_family_index == VK_QUEUE_FAMILY_EXTERNAL || queue_family_index == VK_QUEUE_FAMILY_FOREIGN_EXT)
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return RADV_QUEUE_FOREIGN;
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if (queue_family_index == VK_QUEUE_FAMILY_IGNORED)
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return RADV_QUEUE_IGNORED;
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assert(queue_family_index < RADV_MAX_QUEUE_FAMILIES);
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return pdev->vk_queue_to_radv[queue_family_index];
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}
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/**
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* Helper used for debugging compiler issues by enabling/disabling LLVM for a
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* specific shader stage (developers only).
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*/
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static inline bool
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radv_use_llvm_for_stage(const struct radv_physical_device *pdev, UNUSED gl_shader_stage stage)
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{
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return pdev->use_llvm;
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}
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bool radv_enable_rt(const struct radv_physical_device *pdev, bool rt_pipelines);
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bool radv_emulate_rt(const struct radv_physical_device *pdev);
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bool radv_device_supports_etc(const struct radv_physical_device *pdev);
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uint32_t radv_find_memory_index(const struct radv_physical_device *pdev, VkMemoryPropertyFlags flags);
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VkResult create_null_physical_device(struct vk_instance *vk_instance);
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VkResult create_drm_physical_device(struct vk_instance *vk_instance, struct _drmDevice *device,
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struct vk_physical_device **out);
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void radv_physical_device_destroy(struct vk_physical_device *vk_pdev);
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#endif /* RADV_PHYSICAL_DEVICE_H */
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