mirror of https://gitlab.freedesktop.org/mesa/mesa
652 lines
19 KiB
C
652 lines
19 KiB
C
/*
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* Copyright © 2016 Red Hat.
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* Copyright © 2016 Bas Nieuwenhuizen
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*
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* based in part on anv driver which is:
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* Copyright © 2015 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*/
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#ifndef RADV_DEVICE_H
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#define RADV_DEVICE_H
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#include "ac_spm.h"
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#include "ac_sqtt.h"
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#include "util/mesa-blake3.h"
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#include "radv_printf.h"
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#include "radv_queue.h"
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#include "radv_radeon_winsys.h"
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#include "radv_rra.h"
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#include "radv_shader.h"
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#include "vk_device.h"
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#include "vk_texcompress_astc.h"
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#include "vk_texcompress_etc2.h"
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#define RADV_NUM_HW_CTX (RADEON_CTX_PRIORITY_REALTIME + 1)
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struct radv_image_view;
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enum radv_dispatch_table {
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RADV_DEVICE_DISPATCH_TABLE,
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RADV_ANNOTATE_DISPATCH_TABLE,
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RADV_APP_DISPATCH_TABLE,
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RADV_RGP_DISPATCH_TABLE,
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RADV_RRA_DISPATCH_TABLE,
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RADV_RMV_DISPATCH_TABLE,
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RADV_CTX_ROLL_DISPATCH_TABLE,
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RADV_DISPATCH_TABLE_COUNT,
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};
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struct radv_layer_dispatch_tables {
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struct vk_device_dispatch_table annotate;
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struct vk_device_dispatch_table app;
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struct vk_device_dispatch_table rgp;
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struct vk_device_dispatch_table rra;
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struct vk_device_dispatch_table rmv;
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struct vk_device_dispatch_table ctx_roll;
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};
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enum radv_buffer_robustness {
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RADV_BUFFER_ROBUSTNESS_DISABLED,
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RADV_BUFFER_ROBUSTNESS_1, /* robustBufferAccess */
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RADV_BUFFER_ROBUSTNESS_2, /* robustBufferAccess2 */
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};
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struct radv_device_cache_key {
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uint32_t disable_trunc_coord : 1;
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uint32_t image_2d_view_of_3d : 1;
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uint32_t mesh_shader_queries : 1;
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uint32_t primitives_generated_query : 1;
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};
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enum radv_force_vrs {
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RADV_FORCE_VRS_1x1 = 0,
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RADV_FORCE_VRS_2x2,
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RADV_FORCE_VRS_2x1,
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RADV_FORCE_VRS_1x2,
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};
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struct radv_notifier {
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int fd;
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int watch;
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bool quit;
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thrd_t thread;
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};
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struct radv_meta_state {
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VkAllocationCallbacks alloc;
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VkPipelineCache cache;
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uint32_t initial_cache_entries;
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/*
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* For on-demand pipeline creation, makes sure that
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* only one thread tries to build a pipeline at the same time.
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*/
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mtx_t mtx;
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/**
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* Use array element `i` for images with `2^i` samples.
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*/
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struct {
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VkPipeline color_pipelines[NUM_META_FS_KEYS];
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} color_clear[MAX_SAMPLES_LOG2][MAX_RTS];
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struct {
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VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
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VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
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VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
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VkPipeline depth_only_unrestricted_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
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VkPipeline stencil_only_unrestricted_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
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VkPipeline depthstencil_unrestricted_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
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} ds_clear[MAX_SAMPLES_LOG2];
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VkPipelineLayout clear_color_p_layout;
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VkPipelineLayout clear_depth_p_layout;
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VkPipelineLayout clear_depth_unrestricted_p_layout;
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/* Optimized compute fast HTILE clear for stencil or depth only. */
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VkPipeline clear_htile_mask_pipeline;
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VkPipelineLayout clear_htile_mask_p_layout;
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VkDescriptorSetLayout clear_htile_mask_ds_layout;
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/* Copy VRS into HTILE. */
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VkPipeline copy_vrs_htile_pipeline;
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VkPipelineLayout copy_vrs_htile_p_layout;
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VkDescriptorSetLayout copy_vrs_htile_ds_layout;
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/* Clear DCC with comp-to-single. */
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VkPipeline clear_dcc_comp_to_single_pipeline[2]; /* 0: 1x, 1: 2x/4x/8x */
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VkPipelineLayout clear_dcc_comp_to_single_p_layout;
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VkDescriptorSetLayout clear_dcc_comp_to_single_ds_layout;
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struct {
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/** Pipeline that blits from a 1D image. */
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VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
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/** Pipeline that blits from a 2D image. */
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VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
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/** Pipeline that blits from a 3D image. */
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VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
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VkPipeline depth_only_1d_pipeline;
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VkPipeline depth_only_2d_pipeline;
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VkPipeline depth_only_3d_pipeline;
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VkPipeline stencil_only_1d_pipeline;
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VkPipeline stencil_only_2d_pipeline;
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VkPipeline stencil_only_3d_pipeline;
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VkPipelineLayout pipeline_layout;
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VkDescriptorSetLayout ds_layout;
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} blit;
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struct {
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VkPipelineLayout p_layouts[5];
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VkDescriptorSetLayout ds_layouts[5];
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VkPipeline pipelines[5][NUM_META_FS_KEYS];
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VkPipeline depth_only_pipeline[5];
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VkPipeline stencil_only_pipeline[5];
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} blit2d[MAX_SAMPLES_LOG2];
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struct {
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VkPipelineLayout img_p_layout;
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VkDescriptorSetLayout img_ds_layout;
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VkPipeline pipeline;
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VkPipeline pipeline_3d;
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} itob;
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struct {
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VkPipelineLayout img_p_layout;
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VkDescriptorSetLayout img_ds_layout;
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VkPipeline pipeline;
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VkPipeline pipeline_3d;
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} btoi;
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struct {
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VkPipelineLayout img_p_layout;
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VkDescriptorSetLayout img_ds_layout;
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VkPipeline pipeline;
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} btoi_r32g32b32;
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struct {
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VkPipelineLayout img_p_layout;
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VkDescriptorSetLayout img_ds_layout;
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VkPipeline pipeline[MAX_SAMPLES_LOG2];
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VkPipeline pipeline_3d;
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} itoi;
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struct {
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VkPipelineLayout img_p_layout;
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VkDescriptorSetLayout img_ds_layout;
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VkPipeline pipeline;
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} itoi_r32g32b32;
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struct {
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VkPipelineLayout img_p_layout;
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VkDescriptorSetLayout img_ds_layout;
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VkPipeline pipeline[MAX_SAMPLES_LOG2];
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VkPipeline pipeline_3d;
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} cleari;
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struct {
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VkPipelineLayout img_p_layout;
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VkDescriptorSetLayout img_ds_layout;
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VkPipeline pipeline;
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} cleari_r32g32b32;
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struct {
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VkPipelineLayout p_layout;
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VkDescriptorSetLayout ds_layout;
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VkPipeline pipeline[MAX_SAMPLES_LOG2];
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} fmask_copy;
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struct {
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VkPipelineLayout p_layout;
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VkPipeline pipeline[NUM_META_FS_KEYS];
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} resolve;
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struct {
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VkDescriptorSetLayout ds_layout;
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VkPipelineLayout p_layout;
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struct {
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VkPipeline pipeline;
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VkPipeline i_pipeline;
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VkPipeline srgb_pipeline;
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} rc[MAX_SAMPLES_LOG2];
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VkPipeline depth_zero_pipeline;
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struct {
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VkPipeline average_pipeline;
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VkPipeline max_pipeline;
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VkPipeline min_pipeline;
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} depth[MAX_SAMPLES_LOG2];
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VkPipeline stencil_zero_pipeline;
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struct {
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VkPipeline max_pipeline;
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VkPipeline min_pipeline;
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} stencil[MAX_SAMPLES_LOG2];
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} resolve_compute;
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struct {
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VkDescriptorSetLayout ds_layout;
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VkPipelineLayout p_layout;
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struct {
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VkPipeline pipeline[NUM_META_FS_KEYS];
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} rc[MAX_SAMPLES_LOG2];
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VkPipeline depth_zero_pipeline;
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struct {
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VkPipeline average_pipeline;
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VkPipeline max_pipeline;
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VkPipeline min_pipeline;
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} depth[MAX_SAMPLES_LOG2];
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VkPipeline stencil_zero_pipeline;
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struct {
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VkPipeline max_pipeline;
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VkPipeline min_pipeline;
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} stencil[MAX_SAMPLES_LOG2];
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} resolve_fragment;
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struct {
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VkPipelineLayout p_layout;
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VkPipeline decompress_pipeline;
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VkPipeline resummarize_pipeline;
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} depth_decomp[MAX_SAMPLES_LOG2];
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VkDescriptorSetLayout expand_depth_stencil_compute_ds_layout;
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VkPipelineLayout expand_depth_stencil_compute_p_layout;
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VkPipeline expand_depth_stencil_compute_pipeline;
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struct {
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VkPipelineLayout p_layout;
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VkPipeline cmask_eliminate_pipeline;
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VkPipeline fmask_decompress_pipeline;
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VkPipeline dcc_decompress_pipeline;
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VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
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VkPipelineLayout dcc_decompress_compute_p_layout;
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VkPipeline dcc_decompress_compute_pipeline;
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} fast_clear_flush;
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struct {
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VkPipelineLayout fill_p_layout;
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VkPipelineLayout copy_p_layout;
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VkPipeline fill_pipeline;
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VkPipeline copy_pipeline;
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} buffer;
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struct {
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VkDescriptorSetLayout ds_layout;
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VkPipelineLayout p_layout;
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VkPipeline occlusion_query_pipeline;
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VkPipeline pipeline_statistics_query_pipeline;
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VkPipeline tfb_query_pipeline;
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VkPipeline timestamp_query_pipeline;
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VkPipeline pg_query_pipeline;
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VkPipeline ms_prim_gen_query_pipeline;
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} query;
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struct {
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VkDescriptorSetLayout ds_layout;
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VkPipelineLayout p_layout;
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VkPipeline pipeline[MAX_SAMPLES_LOG2];
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} fmask_expand;
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struct {
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VkDescriptorSetLayout ds_layout;
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VkPipelineLayout p_layout;
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VkPipeline pipeline[32];
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} dcc_retile;
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struct {
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VkPipelineLayout leaf_p_layout;
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VkPipeline leaf_pipeline;
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VkPipeline leaf_updateable_pipeline;
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VkPipelineLayout morton_p_layout;
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VkPipeline morton_pipeline;
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VkPipelineLayout lbvh_main_p_layout;
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VkPipeline lbvh_main_pipeline;
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VkPipelineLayout lbvh_generate_ir_p_layout;
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VkPipeline lbvh_generate_ir_pipeline;
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VkPipelineLayout ploc_p_layout;
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VkPipeline ploc_pipeline;
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VkPipelineLayout encode_p_layout;
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VkPipeline encode_pipeline;
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VkPipeline encode_compact_pipeline;
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VkPipelineLayout header_p_layout;
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VkPipeline header_pipeline;
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VkPipelineLayout update_p_layout;
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VkPipeline update_pipeline;
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VkPipelineLayout copy_p_layout;
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VkPipeline copy_pipeline;
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struct radix_sort_vk *radix_sort;
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struct {
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VkBuffer buffer;
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VkDeviceMemory memory;
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VkAccelerationStructureKHR accel_struct;
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} null;
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} accel_struct_build;
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struct vk_texcompress_etc2_state etc_decode;
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struct vk_texcompress_astc_state *astc_decode;
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struct {
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VkDescriptorSetLayout ds_layout;
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VkPipelineLayout p_layout;
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VkPipeline pipeline;
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} dgc_prepare;
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};
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struct radv_memory_trace_data {
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/* ID of the PTE update event in ftrace data */
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uint16_t ftrace_update_ptes_id;
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uint32_t num_cpus;
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int *pipe_fds;
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};
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struct radv_sqtt_timestamp {
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uint8_t *map;
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unsigned offset;
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uint64_t size;
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struct radeon_winsys_bo *bo;
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struct list_head list;
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};
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#define RADV_BORDER_COLOR_COUNT 4096
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#define RADV_BORDER_COLOR_BUFFER_SIZE (sizeof(VkClearColorValue) * RADV_BORDER_COLOR_COUNT)
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struct radv_device_border_color_data {
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bool used[RADV_BORDER_COLOR_COUNT];
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struct radeon_winsys_bo *bo;
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VkClearColorValue *colors_gpu_ptr;
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/* Mutex is required to guarantee vkCreateSampler thread safety
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* given that we are writing to a buffer and checking color occupation */
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mtx_t mutex;
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};
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struct radv_device {
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struct vk_device vk;
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struct radeon_winsys *ws;
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struct radv_layer_dispatch_tables layer_dispatch;
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struct radeon_winsys_ctx *hw_ctx[RADV_NUM_HW_CTX];
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struct radv_meta_state meta_state;
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struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
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int queue_count[RADV_MAX_QUEUE_FAMILIES];
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bool pbb_allowed;
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uint32_t scratch_waves;
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uint32_t dispatch_initiator;
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uint32_t dispatch_initiator_task;
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/* MSAA sample locations.
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* The first index is the sample index.
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* The second index is the coordinate: X, Y. */
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float sample_locations_1x[1][2];
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float sample_locations_2x[2][2];
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float sample_locations_4x[4][2];
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float sample_locations_8x[8][2];
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/* GFX7 and later */
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uint32_t gfx_init_size_dw;
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struct radeon_winsys_bo *gfx_init;
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struct radeon_winsys_bo *trace_bo;
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uint32_t *trace_id_ptr;
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/* Whether to keep shader debug info, for debugging. */
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bool keep_shader_info;
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/* Backup in-memory cache to be used if the app doesn't provide one */
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struct vk_pipeline_cache *mem_cache;
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/*
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* use different counters so MSAA MRTs get consecutive surface indices,
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* even if MASK is allocated in between.
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*/
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uint32_t image_mrt_offset_counter;
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uint32_t fmask_mrt_offset_counter;
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struct list_head shader_arenas;
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struct hash_table_u64 *capture_replay_arena_vas;
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unsigned shader_arena_shift;
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uint8_t shader_free_list_mask;
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struct radv_shader_free_list shader_free_list;
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struct radv_shader_free_list capture_replay_free_list;
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struct list_head shader_block_obj_pool;
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mtx_t shader_arena_mutex;
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mtx_t shader_upload_hw_ctx_mutex;
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struct radeon_winsys_ctx *shader_upload_hw_ctx;
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VkSemaphore shader_upload_sem;
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uint64_t shader_upload_seq;
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struct list_head shader_dma_submissions;
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mtx_t shader_dma_submission_list_mutex;
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cnd_t shader_dma_submission_list_cond;
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/* Whether to DMA shaders to invisible VRAM or to upload directly through BAR. */
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bool shader_use_invisible_vram;
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/* Whether the app has enabled the robustBufferAccess/robustBufferAccess2 features. */
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enum radv_buffer_robustness buffer_robustness;
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/* Whether to inline the compute dispatch size in user sgprs. */
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bool load_grid_size_from_user_sgpr;
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/* Whether the driver uses a global BO list. */
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bool use_global_bo_list;
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/* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
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int force_aniso;
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/* Always disable TRUNC_COORD. */
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bool disable_trunc_coord;
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struct radv_device_border_color_data border_color_data;
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/* Thread trace. */
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struct ac_sqtt sqtt;
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bool sqtt_enabled;
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bool sqtt_triggered;
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/* SQTT timestamps for queue events. */
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simple_mtx_t sqtt_timestamp_mtx;
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struct radv_sqtt_timestamp sqtt_timestamp;
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/* SQTT timed cmd buffers. */
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simple_mtx_t sqtt_command_pool_mtx;
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struct vk_command_pool *sqtt_command_pool[2];
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/* Memory trace. */
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struct radv_memory_trace_data memory_trace;
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/* SPM. */
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struct ac_spm spm;
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/* Radeon Raytracing Analyzer trace. */
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struct radv_rra_trace_data rra_trace;
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FILE *ctx_roll_file;
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simple_mtx_t ctx_roll_mtx;
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/* Trap handler. */
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struct radv_shader *trap_handler_shader;
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struct radeon_winsys_bo *tma_bo; /* Trap Memory Address */
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uint32_t *tma_ptr;
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/* Overallocation. */
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bool overallocation_disallowed;
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uint64_t allocated_memory_size[VK_MAX_MEMORY_HEAPS];
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mtx_t overallocation_mutex;
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/* RADV_FORCE_VRS. */
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struct radv_notifier notifier;
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enum radv_force_vrs force_vrs;
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/* Depth image for VRS when not bound by the app. */
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struct {
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struct radv_image *image;
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struct radv_buffer *buffer; /* HTILE */
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struct radv_device_memory *mem;
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} vrs;
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/* Prime blit sdma queue */
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struct radv_queue *private_sdma_queue;
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struct radv_shader_part_cache vs_prologs;
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struct radv_shader_part *simple_vs_prologs[MAX_VERTEX_ATTRIBS];
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struct radv_shader_part *instance_rate_vs_prologs[816];
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struct radv_shader_part_cache ps_epilogs;
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|
|
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simple_mtx_t trace_mtx;
|
|
|
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/* Whether per-vertex VRS is forced. */
|
|
bool force_vrs_enabled;
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|
|
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simple_mtx_t pstate_mtx;
|
|
unsigned pstate_cnt;
|
|
|
|
/* BO to contain some performance counter helpers:
|
|
* - A lock for profiling cmdbuffers.
|
|
* - a temporary fence for the end query synchronization.
|
|
* - the pass to use for profiling. (as an array of bools)
|
|
*/
|
|
struct radeon_winsys_bo *perf_counter_bo;
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|
|
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/* Interleaved lock/unlock commandbuffers for perfcounter passes. */
|
|
struct radeon_cmdbuf **perf_counter_lock_cs;
|
|
|
|
bool uses_shadow_regs;
|
|
|
|
struct hash_table *rt_handles;
|
|
simple_mtx_t rt_handles_mtx;
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|
|
|
struct radv_printf_data printf;
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|
|
|
struct radv_device_cache_key cache_key;
|
|
blake3_hash cache_hash;
|
|
|
|
/* Not NULL if a GPU hang report has been generated for VK_EXT_device_fault. */
|
|
char *gpu_hang_report;
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|
|
|
/* For indirect compute pipeline binds with DGC only. */
|
|
simple_mtx_t compute_scratch_mtx;
|
|
uint32_t compute_scratch_size_per_wave;
|
|
uint32_t compute_scratch_waves;
|
|
};
|
|
|
|
VK_DEFINE_HANDLE_CASTS(radv_device, vk.base, VkDevice, VK_OBJECT_TYPE_DEVICE)
|
|
|
|
static inline struct radv_physical_device *
|
|
radv_device_physical(const struct radv_device *dev)
|
|
{
|
|
return (struct radv_physical_device *)dev->vk.physical;
|
|
}
|
|
|
|
static inline bool
|
|
radv_uses_device_generated_commands(const struct radv_device *device)
|
|
{
|
|
return device->vk.enabled_features.deviceGeneratedCommands || device->vk.enabled_features.deviceGeneratedCompute;
|
|
}
|
|
|
|
static inline bool
|
|
radv_uses_primitives_generated_query(const struct radv_device *device)
|
|
{
|
|
return device->vk.enabled_features.primitivesGeneratedQuery ||
|
|
device->vk.enabled_features.primitivesGeneratedQueryWithRasterizerDiscard ||
|
|
device->vk.enabled_features.primitivesGeneratedQueryWithNonZeroStreams;
|
|
}
|
|
|
|
static inline bool
|
|
radv_uses_image_float32_atomics(const struct radv_device *device)
|
|
{
|
|
return device->vk.enabled_features.shaderImageFloat32Atomics ||
|
|
device->vk.enabled_features.sparseImageFloat32Atomics ||
|
|
device->vk.enabled_features.shaderImageFloat32AtomicMinMax ||
|
|
device->vk.enabled_features.sparseImageFloat32AtomicMinMax;
|
|
}
|
|
|
|
VkResult radv_device_init_vrs_state(struct radv_device *device);
|
|
|
|
unsigned radv_get_default_max_sample_dist(int log_samples);
|
|
|
|
void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples);
|
|
|
|
bool radv_get_memory_fd(struct radv_device *device, struct radv_device_memory *memory, int *pFD);
|
|
|
|
unsigned radv_get_dcc_max_uncompressed_block_size(const struct radv_device *device, const struct radv_image *image);
|
|
|
|
struct radv_color_buffer_info {
|
|
uint64_t cb_color_base;
|
|
uint64_t cb_color_cmask;
|
|
uint64_t cb_color_fmask;
|
|
uint64_t cb_dcc_base;
|
|
uint32_t cb_color_slice;
|
|
uint32_t cb_color_view;
|
|
uint32_t cb_color_info;
|
|
uint32_t cb_color_attrib;
|
|
uint32_t cb_color_attrib2; /* GFX9 and later */
|
|
uint32_t cb_color_attrib3; /* GFX10 and later */
|
|
uint32_t cb_dcc_control;
|
|
uint32_t cb_color_cmask_slice;
|
|
uint32_t cb_color_fmask_slice;
|
|
union {
|
|
uint32_t cb_color_pitch; // GFX6-GFX8
|
|
uint32_t cb_mrt_epitch; // GFX9+
|
|
};
|
|
};
|
|
|
|
struct radv_ds_buffer_info {
|
|
uint64_t db_z_read_base;
|
|
uint64_t db_stencil_read_base;
|
|
uint64_t db_z_write_base;
|
|
uint64_t db_stencil_write_base;
|
|
uint64_t db_htile_data_base;
|
|
uint32_t db_depth_info;
|
|
uint32_t db_z_info;
|
|
uint32_t db_stencil_info;
|
|
uint32_t db_depth_view;
|
|
uint32_t db_depth_size;
|
|
uint32_t db_depth_slice;
|
|
uint32_t db_htile_surface;
|
|
uint32_t db_z_info2; /* GFX9 only */
|
|
uint32_t db_stencil_info2; /* GFX9 only */
|
|
uint32_t db_render_override2;
|
|
uint32_t db_render_control;
|
|
};
|
|
|
|
void radv_initialise_color_surface(struct radv_device *device, struct radv_color_buffer_info *cb,
|
|
struct radv_image_view *iview);
|
|
|
|
void radv_initialise_vrs_surface(struct radv_image *image, struct radv_buffer *htile_buffer,
|
|
struct radv_ds_buffer_info *ds);
|
|
|
|
|
|
void radv_initialise_ds_surface(const struct radv_device *device, struct radv_ds_buffer_info *ds,
|
|
struct radv_image_view *iview, VkImageAspectFlags ds_aspects);
|
|
|
|
void radv_gfx11_set_db_render_control(const struct radv_device *device, unsigned num_samples,
|
|
unsigned *db_render_control);
|
|
|
|
bool radv_device_set_pstate(struct radv_device *device, bool enable);
|
|
|
|
bool radv_device_acquire_performance_counters(struct radv_device *device);
|
|
|
|
void radv_device_release_performance_counters(struct radv_device *device);
|
|
|
|
#endif /* RADV_DEVICE_H */
|