Commit Graph

157557 Commits

Author SHA1 Message Date
Emma Anholt fcd96ce002 turnip: Use the GMEM CCU space for attachments when the stores won't.
Since the CCU only gets used for unaligned attachment stores or resolves
with the wrong formats, we can use that space for attachments in many
cases.

This gets two more of vk-5-normal's main renderpass's attachments to fit
in the next gmem_pixels increment, leaving 1 to go.  Other renderpasses do
get better gmem_pixels, and a few get better tile sizes as a result, but
the fps increase from those looks to be <.2% at least.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16921>
2022-08-03 16:54:15 +00:00
Emma Anholt b8a334b547 turnip: Split the tiling config into separate layouts based on CCU usage.
We now choose between two (equal as of this commit) layouts based on
whether the renderpass's stores will use the CCU space, and assert that we
always know the chosen layout when we go using the gmem offsets.

This required making vkCmdClearAttachments in a secondary take the 3D path
instead of gmem blits, since secondaries only have to be compatible with
the primary's renderpass, rather than equal.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16921>
2022-08-03 16:54:15 +00:00
Emma Anholt a1db4fcab7 ci/freedreno: Update a630 s8 resolve xfails.
These tests are all only run in a full vk run.  These removed ones were
fixed in https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17684
and I'm betting the bypass ones were pre-existing (we hadn't updated 630's
full vk run list for these new stencil tests, I belive -- my previous full
run update was just from one of the two jobs).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16921>
2022-08-03 16:54:15 +00:00
Connor Abbott 19418adfba tu: Restore formatting of tu_clear_blit.c
Conflict resolution appears to have gone awry.  Use my previous resolution
of that rebase instead.

Fixes: 89263fde20 ("tu: Use common vk_image struct")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16921>
2022-08-03 16:54:15 +00:00
Nanley Chery 6875e07538 iris: Dedent enum iris_depth_reg_mode
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17859>
2022-08-03 15:31:10 +00:00
Nanley Chery a75cd15b94 iris: Make the D16 reg mode single-sampled
Wa_14010455700 is dependent on the format and sample count, but our
code to track whether or not it had been applied was only dependent on
the format.

As a result, we failed to enable the workaround when an app used a D16
2xMSAA buffer, then a D16 1xMSAA buffer right afterwards.

Make the workaround tracking code sample-dependent to fix this.

Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17859>
2022-08-03 15:31:10 +00:00
Nanley Chery e7419c11ae anv: Make the D16 reg mode single-sampled
Wa_14010455700 is dependent on the format and sample count, but our
code to track whether or not it had been applied was only dependent on
the format.

As a result, we failed to enable the workaround when an app used a D16
2xMSAA buffer, then a D16 1xMSAA buffer right afterwards.

Make the workaround tracking code sample-dependent to fix this.

Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17859>
2022-08-03 15:31:10 +00:00
Alyssa Rosenzweig a4a15f500c nir/lower_idiv: Be less creative about signs
I'm sorry to whoever wrote this, but

   (x - (int) (x < 0)) ^ -((int) (x < 0))

is not an acceptable way to write iabs.

Shader-db results on Intel Tiger Lake with lower_idiv enabled:

    total instructions in shared programs: 21122548 -> 21122570 (<.01%)
    instructions in affected programs: 2369 -> 2391 (0.93%)
    helped: 2
    HURT: 8

    total cycles in shared programs: 791609360 -> 791608062 (<.01%)
    cycles in affected programs: 114106 -> 112808 (-1.14%)
    helped: 9
    HURT: 1

If we make the Intel back-end less stupid, we get to 9/1 helped/HURT for
instructions as well but that's for a different MR.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17845>
2022-08-03 14:24:38 +00:00
Mike Blumenkrantz e13c9d2168 zink: combine loops for lazy descriptor program deinit
the bindless and push sets don't have update templates stored to
the program, so merging these loops avoids trying to destroy them

cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17866>
2022-08-03 12:24:46 +00:00
Mike Blumenkrantz 7450990558 zink: don't flag lazy push constant set dirty on batch change
this has its own flag

cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17866>
2022-08-03 12:24:46 +00:00
Mike Blumenkrantz c7ef4f9735 zink: fix gfx program cache pruning with generated tcs
if the tcs was generated, then the prgram was added to the non-tcs cache,
which means deleting it from the tcs+tes cache will fail and then
context_destroy will explode

Fixes: 4123ee3c71 ("zink: invoke descriptor_program_deinit for programs on context destroy")

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17866>
2022-08-03 12:24:46 +00:00
Danylo Piliaiev e1c89abd86 ir3: Never remove GS_HEADER_IR3 sysval input
Without GS header geometry shader is never invoked which may cause
issues if it has side-effects.

Fixes GL CTS tests running via Zink:
 KHR-GL46.shader_image_load_store.multiple-uniforms
 KHR-GL46.texture_cube_map_array.image_op_geometry_sh

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6940

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17771>
2022-08-03 10:51:58 +00:00
Danylo Piliaiev ed7814def7 ir3/ra: Always insert interval for precolored inputs
insert_dst checked whether dst is unused, however for precolored
inputs we always want to reserve a reg for them. Input could be
unused only if we explicitly want it.

Suggested-by: Connor Abbott <cwabbott0@gmail.com>
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17771>
2022-08-03 10:51:58 +00:00
Marek Olšák ff8e52541d radeonsi: move small prim precision computation out of si_emit_cull_state
to put it next to its only use and remove the structure fields

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
2022-08-03 00:57:16 +00:00
Marek Olšák fa46f3d40e radeonsi: move the no-AA small prim precision cull constant into an SGPR
This reduces the scalar load from vec4 to vec2.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
2022-08-03 00:57:16 +00:00
Marek Olšák 788dce46a3 radeonsi: add a randomized blit test
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
2022-08-03 00:57:16 +00:00
Marek Olšák a42be1efdc radeonsi: allow texture_map to upload only 1 sample for MSAA instead of all
Reuse the level parameter to do that, which allows us to keep
the pipe_transfer size unchanged. It's kinda hacky, but it's the simplest
way to do it. This will be used by the blit test to initialize MSAA textures.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
2022-08-03 00:57:16 +00:00
Marek Olšák 2afaedf1d6 radeonsi: make various blit functions non-static
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
2022-08-03 00:57:16 +00:00
Marek Olšák f129db911b radeonsi/gfx11: use a better workaround for the export conflict bug
This is recommended for better performance.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
2022-08-03 00:57:16 +00:00
Marek Olšák 2ed9eb1b63 radeonsi/gfx11: enable shader prefetch except for initial chip revisions
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
2022-08-03 00:57:16 +00:00
Marek Olšák a09d971007 radeonsi/gfx11: rename si_calc_inst_pref_size -> si_get_shader_prefetch_size
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
2022-08-03 00:57:16 +00:00
Marek Olšák a791e7f37f radeonsi/gfx11: skip code in si_update_shaders that has no effect
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
2022-08-03 00:57:16 +00:00
Marek Olšák 34196148c1 radeonsi/gfx11: use better PRIM_GRP_SIZE_GFX11 setting
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
2022-08-03 00:57:16 +00:00
Marek Olšák 23a1dca8c6 radeonsi/gfx11: set SAMPLE_MASK_TRACKER_WATERMARK = 15 and clean up
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
2022-08-03 00:57:16 +00:00
Marek Olšák b1af36163c radeonsi/gfx11: use correct VGT_TESS_DISTRIBUTION settings
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
2022-08-03 00:57:16 +00:00
Marek Olšák 28842d96df radeonsi: cosmetic changes around do_hardware_msaa_resolve
- move gfx_level checking into the function
- rename the function
- call it in si_blit later
- set the SQTT event

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
2022-08-03 00:57:16 +00:00
Marek Olšák b1b0a860a5 radeonsi: fold async_copy into the preceding conditional in si_blit
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
2022-08-03 00:57:16 +00:00
Marek Olšák 7f1485d5ea radeonsi: move compute-related code from si_blit.c to si_compute_blit.c
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
2022-08-03 00:57:16 +00:00
Marek Olšák 3b7512cacf radeonsi: check for 16-bit hw support instead of relying on options.fp16
options.fp16 can be true even when the hw doesn't support FP16.
options.fp16 should only affect the CAP because 16-bit ops can still be
used by internal shaders.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
2022-08-03 00:57:16 +00:00
Marek Olšák 2847106b94 radeonsi: add need_fmask_expand parameter into si_decompress_subresource
This is required by MSAA image stores for internal compute blits.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
2022-08-03 00:57:16 +00:00
Marek Olšák 9e9cc62912 radeonsi: follow shader_info.float_controls_execution_mode (mostly)
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
2022-08-03 00:57:16 +00:00
Marek Olšák 0482ff3158 radeonsi: don't do image stores with RGBX, L, LA, I, and SRGB formats
The only change in behavior is that RGBX stores now overwrite X, which is
what CB does and it's faster.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
2022-08-03 00:57:16 +00:00
Marek Olšák b42a4a7f07 radeonsi: remove compute-based DCC decompression because it's broken
The new blit test discovered that it doesn't always work.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
2022-08-03 00:57:16 +00:00
Marek Olšák 9da309a7f4 radeonsi: add common helper si_launch_grid_internal_images that is more robust
It does things in the correct order, which isn't easy to get right.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
2022-08-03 00:57:16 +00:00
Marek Olšák 2a854647c0 radeonsi: make si_launch_grid_internal static
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
2022-08-03 00:57:16 +00:00
Marek Olšák 233b4271dc radeonsi: call pipe->blit instead of util_blitter_blit after MSAA resolving
This fixes a problem where the destination has a DCC-incompatible view
format and triggers a DCC decompression using a custom u_blitter path, which
is disallowed inside u_blitter due to it being a u_blitter recursion that
always crashes.

This is also better because we'll get the best codepath (u_blitter or
compute) instead of just u_blitter,

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
2022-08-03 00:57:16 +00:00
Marek Olšák 922f54a0c8 radeonsi: move SI_MAX_VRAM_MAP_SIZE to si_debug_options.h
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
2022-08-03 00:57:16 +00:00
Marek Olšák 38cd2a610a radeonsi: unify VGT_TESS_DISTRIBUTION programming
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
2022-08-03 00:57:16 +00:00
Marek Olšák 5c0b0f0058 ac/surface: don't forbid 256KB swizzle modes on smaller gfx11 chips
let addrlib make the right choice

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
2022-08-03 00:57:16 +00:00
Marek Olšák 2c25dd0f27 amd/addrlib: fix 3D texture allocation failures on gfx11
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
2022-08-03 00:57:16 +00:00
Marek Olšák 2208ff7a5b util/format: add util_format_rgbx_to_rgba helper
Image stores don't like RGBX on AMD. This is required by compute blits.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
2022-08-03 00:57:16 +00:00
Marek Olšák 91a3a38d5c glthread: don't sync on IsEnabled(GL_DEPTH_TEST) by tracking it in glthread
Discovered with viewperf.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17781>
2022-08-03 00:14:33 +00:00
Marek Olšák a4ee818b18 glthread: don't ignore glPushAttrib/glPopAttrib when tracking GL_CULL_FACE
Fixes: f4348ef60d - glthread: don't sync for glIsEnabled with a few enums

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17781>
2022-08-03 00:14:33 +00:00
Gert Wollny 51a8e9feb5 r600: increase possible stack size in binary code
With the trace posted in #6969 we get a nesting level of 149,
so make it a round 256 of stack entries.

Related: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6969

Fixes: a4840e15ab
  r600: Use nir-to-tgsi instead of TGSI when the NIR debug opt is disabled.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17849>
2022-08-03 00:05:08 +00:00
Rob Clark 3f5d84fb37 freedreno/registers/a6xx: Some reg64 conversion
Reduce the spurious delta from a7xx regs.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17817>
2022-08-02 23:46:15 +00:00
Rob Clark 73ca381d7a freedreno/registers: Move varset to <enum>
De-noisify the enum values that are generation specific.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17817>
2022-08-02 23:46:15 +00:00
Rob Clark 0cd8ce6ce3 freedreno/registers: Allow varset to be specified on enum
It gets a bit repetitive to specify the same varset on each value.  The
rnn decode already handles it when specified on the enum, we just need
to relax the schema to allow this.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17817>
2022-08-02 23:46:15 +00:00
Rob Clark 98b84ef286 freedreno/registers: Whitespace fix for gen_header.py
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17817>
2022-08-02 23:46:15 +00:00
Rob Clark ba85272cb6 freedreno/ci: Update unit test reference decodes
Apparently we aren't running unit tests in CI?

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17817>
2022-08-02 23:46:15 +00:00
Rob Clark 7381e06d81 freedreno: Use enum for primtypes table
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17817>
2022-08-02 23:46:15 +00:00