Commit Graph

103093 Commits

Author SHA1 Message Date
Danylo Piliaiev e7cdaa895a mesa: Return number of result bits for GL_ANY_SAMPLES_PASSED_CONSERVATIVE
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106986
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2018-06-27 11:02:34 +03:00
Samuel Pitoiset 7a57c82767 radv: use separate bind points for the dynamic buffers
The Vulkan spec says:

   "pipelineBindPoint is a VkPipelineBindPoint indicating whether
    the descriptors will be used by graphics pipelines or compute
    pipelines. There is a separate set of bind points for each of
    graphics and compute, so binding one does not disturb the other."

CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-06-27 09:48:31 +02:00
Samuel Pitoiset 9c09e7d66e radv: remove unused 'predicated' parameter from some functions
It's always false.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-06-27 09:48:15 +02:00
Dave Airlie a6b64d6dde virgl: add ARB_texture_view support
Reviewed-By: Gert Wollny <gert.wollny@collabora.com>
2018-06-27 14:08:00 +10:00
Jason Ekstrand ff6db94c18 nir/opt_if: Remove unneeded phis if we make progress
Now that SSA values can be derefs and they have special rules, we have
to be a bit more careful about our LCSSA phis.  In particular, we need
to clean up in case LCSSA ended up creating a phi node for a deref.
This fixes validation issues with some Vulkan CTS tests with the new
deref instructions.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
2018-06-26 10:47:26 -07:00
Samuel Pitoiset fa42fa1a60 radv: emit PIPELINESTAT_{START,STOP} events for pipeline stats queries
Ported from RadeonSI.
This appears to fix some random fails with:
dEQP-VK.query_pool.statistics_query.*

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-06-26 18:23:16 +02:00
Tapani Pälli ab2643e4b0 glsl: serialize data from glTransformFeedbackVaryings
While XFB has been enabled for cache, we did not serialize enough
data for the whole API to work (such as glGetProgramiv).

Fixes: 6d830940f7 "Allow shader cache usage with transform feedback"
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106907
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2018-06-26 12:44:22 +03:00
Samuel Pitoiset bcbd8dd6c9 radv: enable VK_EXT_shader_stencil_export
The driver already supports exporting the stencil value.

The following CTS test now pass:
dEQP-VK.pipeline.shader_stencil_export.op_replace

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-06-26 10:40:10 +02:00
Samuel Pitoiset ba5e25ed29 radv: ignore pInheritanceInfo for primary command buffers
From the Vulkan spec:
"If this is a primary command buffer, then this value is ignored."

CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-06-26 10:39:43 +02:00
Andrii Simiklit 232c5d75ea i965/gen6/gs: Handle case where a GS doesn't allocate VUE
We can not use the VUE Dereference flags combination for EOT
message under ILK and SNB because the threads are not initialized
there with initial VUE handle unlike Pre-IL.
So to avoid GPU hangs on SNB and ILK we need
to avoid usage of the VUE Dereference flags combination.
(Was tested only on SNB but according to the specification
SNB Volume 2 Part 1: 1.6.5.3, 1.6.5.6
the ILK must behave itself in the similar way)

v2: Approach to fix this issue was changed.
Instead of different EOT flags in the program end
we will create VUE every time even if GS produces no output.

v3: Clean up the patch.
Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105399
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Tested-by: Mark Janes <mark.a.janes@intel.com>
2018-06-26 08:18:55 +02:00
Dave Airlie 318ff60ccd radeon: duplicate cmask surface for now.
The radeon winsys isn't linked against the ac code, I have vague
memories of this causing some problems before, for now fix the build
but just duplicating the code.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-06-26 11:26:35 +10:00
Marek Olšák bd963f8430 radeonsi: rename r600_transfer -> si_transfer
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-06-25 18:33:58 -04:00
Marek Olšák eabeeb86b2 radeonsi: properly set cmask_buffer in si_reallocate_texture_inplace
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-06-25 18:33:58 -04:00
Marek Olšák d4755ef389 radeonsi: remove redundant si_texture::cmask_size
cmask_buffer and surface.cmask_size can replace its role.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-06-25 18:33:58 -04:00
Marek Olšák 2a8d1039b6 radeonsi: inline struct r600_cmask_info
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-06-25 18:33:58 -04:00
Marek Olšák 166250f4e5 radeonsi: move CMASK size computation into ac_surface
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-06-25 18:33:58 -04:00
Marek Olšák 3da693b7d9 ac/surface: move cmask_size/alignment into radeon_surf
cmask_size is changed to uint32_t because it can't be greater than 4GB.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-06-25 18:33:58 -04:00
Marek Olšák 2d64a68c6f radeonsi: rename r600_surface -> si_surface
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-06-25 18:33:58 -04:00
Marek Olšák 218e133695 radeonsi: rename r600_memory_object -> si_memory_object
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-06-25 18:33:58 -04:00
Marek Olšák e5df04f13d radeonsi: remove unused r600_memory_object::offset
The real offset is passed through resource_from_memobj.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-06-25 18:33:58 -04:00
Marek Olšák 45004abfd5 radeonsi: unify duplicated texture_from_handle & texture_from_memobj
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-06-25 18:33:58 -04:00
Marek Olšák cac7ab1192 radeonsi: reorder and initialize more fields in si_reallocate_texture_inplace
Some fields shouldn't be initialized, like framebuffers_bound and other stats.
It's hopefully complete now.

Cc: 18.1 <mesa-stable@lists.freedesktop.org>
2018-06-25 18:33:58 -04:00
Marek Olšák 7888245ef3 radeonsi: stop using lp_build_emit_llvm_unary/binary
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-06-25 18:33:58 -04:00
Marek Olšák 0810f15046 radeonsi: stop using lp_build_alloc
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-06-25 18:33:58 -04:00
Marek Olšák 21ba8a204e radeonsi: use gallivm less
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-06-25 18:33:58 -04:00
Marek Olšák 965904eebd radeonsi: stop using lp_bld_intr.h
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-06-25 18:33:58 -04:00
Marek Olšák 6ab54d25a6 radeonsi: remove last uses of lp_build_context::undef
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-06-25 18:33:58 -04:00
Marek Olšák 30f3e2200a radeonsi: stop using lp_bld_arit.h
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-06-25 18:33:58 -04:00
Marek Olšák 5f54fc3ad1 radeonsi: stop using lp_build_gather_values
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-06-25 18:33:58 -04:00
Marek Olšák 7bd40dc2f2 radeonsi: clean up some #includes
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-06-25 18:33:58 -04:00
Marek Olšák f154555733 radeonsi: clean up passing the is_monolithic flag for compilation
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-06-25 18:33:58 -04:00
Robert Foss c7bb82136b
egl/android: Add DRM node probing and filtering
This patch both adds support for probing & filtering DRM nodes
and switches away from using the GRALLOC_MODULE_PERFORM_GET_DRM_FD
gralloc call.

Currently the filtering is based just on the driver name,
and the desired name is supplied using the "drm.gpu.vendor_name"
Android property.

Signed-off-by: Robert Foss <robert.foss@collabora.com>
Reviewed-by: Tomasz Figa <tfiga@chromium.org>
2018-06-25 18:54:10 +02:00
Rob Herring 3f7bca44d9
egl/android: #ifdef out flink name support
Maintaining both flink names and prime fd support which are provided by
2 different gralloc implementations is problematic because we have a
dependency on a specific gralloc implementation header.

This mostly disables the dependency on the gralloc implementation and
headers. The dependency on GRALLOC_MODULE_PERFORM_GET_DRM_FD remains for
now, but the definition is added locally to remove the header
dependency.

drm_gralloc support can be enabled by setting
BOARD_USES_DRM_GRALLOC=true in BoardConfig.mk.

Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Robert Foss <robert.foss@collabora.com>
Reviewed-by: Tomasz Figa <tfiga@chromium.org>
2018-06-25 18:54:09 +02:00
Robert Foss 5a34aba07d
gallium/util: Fix build error due to cast to different size
Signed-off-by: Robert Foss <robert.foss@collabora.com>
Reviewed-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-06-25 18:54:09 +02:00
Samuel Pitoiset 07cb1373a2 radv: fix HTILE metadata initialization in presence of subpass clears
If the driver ends up by performing a slow depthstencil clear,
the HTILE metadata won't be initialized correctly.

This fixes random VM faults on Polaris while running CTS
with Bas's runner. This doesn't seem to regress performance.

CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-06-25 17:38:59 +02:00
Gert Wollny eebb65258d r600/sb: give the scheduler more margin to find valid instructions groups
For instruction sequences that change the address register with every load
the current limit to bail out of the scheduler and reject the optimisation
was too tight, i.e. it was expected that at least one pending instruction
would be scheduled each time.

Give the scheduler more margin to sort out these load sequences by allowing
a number of rounds where no instruction is scheduled.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106163

Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-06-25 05:40:19 +01:00
Gert Wollny cd7db0ab0a r600/sb: fix rotated register in while loop
This patch is based on
https://lists.freedesktop.org/archives/mesa-dev/2018-February/185805.html

Dave Airlie:

 "A bunch of CTS tests led me to write
  tests/shaders/ssa/fs-while-loop-rotate-value.shader_test
  which r600/sb always fell over on.

  GCM seems to move some of the copies into other basic blocks,
  if we don't allow this to happen then it doesn't seem to schedule
  them badly.

  Everything I've read on SSA/phi copies say they have to happen
  in parallel, so keeping them in the same basic block seems like
  a good way to keep some of that property."

This patch differs from the one proposed by Dave in that it only adds
the NF_DONT_MOVE flag to copy_move instructions that are created by split_phi*
and that are located in loops.

Fixes piglit: tests/shaders/ssa/fs-while-loop-rotate-value.shader_test
(no regressions in the shader set). It also fixes all failing tests from

  dEQP-GLES3.functional.shaders.loops.*

Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-06-25 05:39:41 +01:00
Rob Clark 1977e92ee3 freedreno/ir3: fix deref conversion fallout
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-06-23 18:23:11 -04:00
Rob Clark 445871de94 freedreno/ir3: fix unused variable warning
Fixes: cf0c7258ee freedreno/a5xx: MSAA
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-06-23 18:23:11 -04:00
Rob Clark 868ca81cbe freedreno: fix HW_ATOMIC_COUNTERS cap
This was mistakenly exposed, even though we want atomic counters to be
lowered to atomic ops on an SSBO like nearly every other GPU.  Which
somehow recently started getting segfaults due to calling a null
pipe->set_hw_atomic_buffers().

Fixes a crash in stk, and probably other things.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-06-23 18:23:11 -04:00
Keith Packard 1df586be12 radv: add VK_EXT_display_control to radv driver [v5]
This extension provides fences and frame count information to direct
display contexts. It uses new kernel ioctls to provide 64-bits of
vblank sequence and nanosecond resolution.

v2:
	Rework fence integration into the driver so that waiting for
	any of a mixture of fence types (wsi, driver or syncobjs)
	causes the driver to poll, while a list of just syncobjs or
	just driver fences will block. When we get syncobjs for wsi
	fences, we'll adapt to use them.

v3:	Adopt Jason Ekstrand's coding conventions

	Declare variables at first use, eliminate extra whitespace between
	types and names. Wrap lines to 80 columns.

	Suggested-by: Jason Ekstrand <jason.ekstrand@intel.com>

v4:	Adapt to WSI fence API change. It now returns VkResult and
	no longer has an option for relative timeouts.

v5:	wsi_register_display_event and wsi_register_device_event now
	use the default allocator when NULL is provided, so remove the
	computation of 'alloc' here.

Signed-off-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-06-23 07:59:00 -07:00
Keith Packard 16eb390834 anv: add VK_EXT_display_control to anv driver [v5]
This extension provides fences and frame count information to direct
display contexts. It uses new kernel ioctls to provide 64-bits of
vblank sequence and nanosecond resolution.

v2:	Adopt Jason Ekstrand's coding conventions

	Declare variables at first use, eliminate extra whitespace between
	types and names. Wrap lines to 80 columns.

	Add extension to list in alphabetical order

	Suggested-by: Jason Ekstrand <jason.ekstrand@intel.com>

v3:	Adapt to WSI fence API change. It now returns VkResult and
	no longer has an option for relative timeouts.

v4:	wsi_register_display_event and wsi_register_device_event now
	use the default allocator when NULL is provided, so remove the
	computation of 'alloc' here.

v5:	use zalloc2 instead of alloc2 for the WSI fence.

	Suggested-by: Jason Ekstrand <jason.ekstrand@intel.com>

Signed-off-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2018-06-23 07:59:00 -07:00
Keith Packard 86c8d93e5a vulkan: add VK_EXT_display_control [v10]
This extension provides fences and frame count information to direct
display contexts. It uses new kernel ioctls to provide 64-bits of
vblank sequence and nanosecond resolution.

v2: Remove DRM_CRTC_SEQUENCE_FIRST_PIXEL_OUT flag. This has
    been removed from the proposed kernel API.

    Add NULL parameter to drmCrtcQueueSequence ioctl as we
    don't care what sequence the event was actually queued to.

v3: Adapt to pthread clock switch to MONOTONIC

v4: Fix scope for wsi_display_mode andwsi_display_connector allocs

    Suggested-by: Jason Ekstrand <jason@jlekstrand.net>

v5: Adopt Jason Ekstrand's coding conventions

    Declare variables at first use, eliminate extra whitespace between
    types and names. Wrap lines to 80 columns.

    Use wsi_rel_to_abs_time helper function to convert relative
    timeouts to absolute timeouts without causing overflow.

    Suggested-by: Jason Ekstrand <jason.ekstrand@intel.com>

v6:
    Change WSI fence wait function to return VkResult instead of
    bool. This makes the meaning of the return value easier to
    understand, and allows for the indication of failure.

    Also change the WSI fence wait function to take only absolute
    timeouts and not provide an option for a relative timeout. No
    users wanted relative timeouts, and it's simpler if that option
    isn't available.

    Terminate the DPMS property loop once we've found the property.

    Assert that the fence hasn't already been destroyed in
    wsi_display_fence_destroy.

    Rearrange the event handler function order in the file to place
    routines in an easier to find order.

    Suggested-by: Jason Ekstrand <jason.ekstrand@intel.com>

v7:
    Adapt to API changes for surface_get_capabilities

v8:
    Use wsi->alloc in register_display_event so that callers
    don't have to dig out an allocator for us.

v9:
    Fix a few minor formatting issues

    Suggested-by: Jason Ekstrand <jason.ekstrand@intel.com>

v10:
    Use wsi->alloc if none provided in wsi_display_fence_alloc.

    Now that drivers are expected to pass the allocator argument
    straight through from the application, we need to check those
    for NULL everywhere.

Signed-off-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2018-06-23 07:59:00 -07:00
Keith Packard 5581dd5c32 anv: Support wait for heterogeneous list of fences [v3]
Handle the case where the set of fences to wait for is not all of the
same type by either waiting for them sequentially (waitAll), or
polling them until the timer has expired (!waitAll). We hope the
latter case is not common.

While the current code makes sure that it always has fences of only
one type, that will not be true when we add WSI fences. Split out this
refactoring to make merging that clearer.

v2: Adopt Jason Ekstrand's coding conventions

    Declare variables at first use, eliminate extra whitespace between
    types and names. Wrap lines to 80 columns.

    Suggested-by: Jason Ekstrand <jason.ekstrand@intel.com>

v2:
    Cast INT64_MAX to uint64_t to make of its use as the maximum
    possible timeout clearly unsigned to the reader.

    Suggested-by: Jason Ekstrand <jason.ekstrand@intel.com>

    Make anv_wait_for_fences with !waitAll check all fences at least
    once, even if the requested timeout has already passed.

Signed-off-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2018-06-23 07:59:00 -07:00
Bas Nieuwenhuizen 8c4f430d43 radv: Enable lower_io_to_temporaries after deref changes.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-06-22 21:23:06 -07:00
Jason Ekstrand aef4213fca nir/lower_system_values: Assert/assume direct var derefs
System values are never arrays or structs so we can assume a direct var
deref.  This simplifies things a bit and prevents us from accidentally
throwing away an array index.

Suggested-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Acked-by: Rob Clark <robdclark@gmail.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-06-22 21:23:06 -07:00
Jason Ekstrand a331d7d1cd nir: Remove old-school deref chain support
Acked-by: Rob Clark <robdclark@gmail.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-06-22 21:23:06 -07:00
Jason Ekstrand 9800b81ffb nir: Remove deref chain support from analyze_loops
Note that this patch needs to come late in the series since this pass
can be run after any pass that damages nir_metadata_loop_analysis.

Acked-by: Rob Clark <robdclark@gmail.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-06-22 21:23:06 -07:00
Rob Clark 2db8784167 freedreno/ir3: convert to deref instructions
Signed-off-by: Rob Clark <robdclark@gmail.com>
Acked-by: Rob Clark <robdclark@gmail.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-06-22 21:23:05 -07:00
Rob Clark 95683bdce3 nir: promote intrinsic_get_var() to helper
Useful in a few other places.. let's not copy-pasta

Signed-off-by: Rob Clark <robdclark@gmail.com>
Acked-by: Rob Clark <robdclark@gmail.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-06-22 20:54:00 -07:00