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159949 Commits

Author SHA1 Message Date
Marcin Ślusarz dedd8affd8 anv: fix emission of primitive replication packet for mesh stage 
anv_pipeline_get_last_vue_prog_data (used by emit_3dstate_primitive_replication)
doesn't work for mesh stage.

Fixes: ae57628dd5 ("anv: Drop anv_pipeline::use_primitive_replication")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18495>
 2022-09-19 09:44:00 +00:00
Dave Airlie 9452e5e03a lavapipe: fix 3d depth stencil image clearing. 
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18665>
 2022-09-19 17:26:57 +10:00
Mike Blumenkrantz 73797c2f46 zink: use screen interfaces for pipeline barriers 
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18628>
 2022-09-19 01:42:28 +00:00
Mike Blumenkrantz 8c4aaa154a zink: add screen interfaces for pipeline barriers 
this will enable direct calling of the right function without the overhead
of having conditionals in the barrier functions themselves

eventually, the '2' variants will be widely enough deployed that
this can be deleted

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18628>
 2022-09-19 01:42:28 +00:00
Mike Blumenkrantz 5a78fe4445 zink: add functions for using '2' variants of pipeline barriers 
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18628>
 2022-09-19 01:42:28 +00:00
Mike Blumenkrantz 9b0b8cad60 zink: add have_vulkan13 to device info 
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18628>
 2022-09-19 01:42:28 +00:00
Mike Blumenkrantz 95ea41dff9 zink: rewrite clears on fb bind if only the format has changed 
in some apps (hl2), there's a weird sequence like:
* bind attachment with srgb view
* clear
* bind attachment with base format
* draw

rewriting the clear color like this avoids unnecessarily triggering
a renderpass

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18627>
 2022-09-19 01:00:43 +00:00
Mike Blumenkrantz 13a19ad90c zink: make void clears more robust 
void clears are intended to be the first clear applied to a surface,
so ensure that these don't clobber any scissored clears

cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18627>
 2022-09-19 01:00:43 +00:00
Mike Blumenkrantz d7c64ffcb8 zink: split up get_clear_data() 
make the array extension part reusable

cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18627>
 2022-09-19 01:00:43 +00:00
Mike Blumenkrantz 11a5297ef5 zink: don't add void clears if a full clear already exists 
this otherwise may clobber other clears or add unnecessary duplicates

Fixes: 7ea7d0687b ("zink: inject a 0,0,0,1 clear for RGBX formats")

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18627>
 2022-09-19 01:00:43 +00:00
David Heidelberg f380a2d63e ci/intel: drop glmark2 terrain trace 
See: https://gitlab.freedesktop.org/gfx-ci/tracie/traces-db/-/merge_requests/50

Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18633>
 2022-09-18 18:51:14 +00:00
David Heidelberg ce05ed1866 ci/panfrost: drop glmark2 terrain trace 
See: https://gitlab.freedesktop.org/gfx-ci/tracie/traces-db/-/merge_requests/50

Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18633>
 2022-09-18 18:51:14 +00:00
David Heidelberg f4eea9ebc2 ci/radeonsi: drop glmark2 terrain trace 
See: https://gitlab.freedesktop.org/gfx-ci/tracie/traces-db/-/merge_requests/50

Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18633>
 2022-09-18 18:51:14 +00:00
Alyssa Rosenzweig f06809cdca panfrost: Evict the BO cache when allocation fails 
If memory allocation fails, we look for a suitable sized BO in the BO cache and
wait until we can use its memory. That usually works, but there's a case when it
can fail despite sufficient memory in the system: BOs in the BO cache
contributing to memory pressure but none of them being of sufficient size. This
case is not just theoretical: it's seen in the OpenCL
test_non_uniform_work_group, which puts the system under considerable memory
pressure with an unusual allocation pattern.

To handle this case, try evicting *everything* from the BO cache and stalling
in order to allocate, if the above attempts failed. Fixes the following error:

   DRM_IOCTL_PANFROST_CREATE_BO failed: No space left on device

on the aforementioned OpenCL test.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18579>
 2022-09-18 18:34:21 +00:00
Pavel Ondračka a1b55fde93 r300: fix register rewrite when converting rbg instructions to alpha 
Example from dEQP-GLES2.functional.shaders.indexing.tmp_array.float_dynamic_write_dynamic_loop_read_fragment

Fragment Program: after 'pair translate'
  0: src0.xyz = input[0], src1.xyz = const[5]
     MAD temp[0].xyz, src0.xxx, src1.Hyz, src0.000
  1: src0.xyz = const[1], src1.xyz = const[6]
     MAD temp[1].xyz, src0.xxx, src0.111, -src1.x1z
  2: src0.xyz = temp[1]
     CMP temp[1].xyz, src0.000, src0.111, src0.xyz
  3: src0.xyz = temp[0], src1.xyz = input[0], src2.xyz = temp[1]
     CMP temp[2].x, src0.x__, src1.x__, -src2.y__
  4: src0.xyz = input[0], src1.xyz = temp[0], src2.xyz = temp[1]
     CMP temp[3].x, src0.x__, src1.x__, -src2.z__
  5: src0.xyz = temp[1]
     MAX temp[4].x, src0.x__, src0.z__
  6: src0.xyz = temp[0], src1.xyz = input[0], src2.xyz = temp[4]
     CMP temp[4].x, src0.x__, src1.x__, -src2.x__
  7: src0.xyz = temp[3], src1.xyz = input[0], src2.xyz = temp[1]
     CMP temp[3].x, src0.x__, src1.x__, -src2.x__
  8: src0.xyz = input[0], src1.xyz = temp[2], src2.xyz = temp[1]
     CMP temp[2].x, src0.x__, src1.x__, -src2.x__
  9: src0.xyz = temp[1]
     MAD temp[1].x, src0.x__, src0.y__, src0.000
 10: src0.xyz = input[0], src1.xyz = temp[0], src2.xyz = temp[1]
     CMP temp[1].x, src0.x__, src1.x__, -src2.x__
 11: src0.xyz = const[2], src1.xyz = const[6]
     MAD temp[5].xyz, src0.xxx, src0.111, -src1.x1z
 12: src0.xyz = temp[5]
     CMP temp[5].xyz, src0.000, src0.111, src0.xyz
 13: src0.xyz = temp[0], src1.xyz = temp[2], src2.xyz = temp[5]
     CMP temp[6].x, src0.y__, src1.x__, -src2.y__
 14: src0.xyz = temp[3], src1.xyz = temp[0], src2.xyz = temp[5]
     CMP temp[7].x, src0.x__, src1.y__, -src2.z__
 15: src0.xyz = temp[5]
     MAX temp[8].x, src0.x__, src0.z__
 16: src0.xyz = temp[0], src1.xyz = temp[4], src2.xyz = temp[8]
     CMP temp[4].x, src0.y__, src1.x__, -src2.x__
 17: src0.xyz = temp[7], src1.xyz = temp[3], src2.xyz = temp[5]
     CMP temp[3].x, src0.x__, src1.x__, -src2.x__
 18: src0.xyz = temp[2], src1.xyz = temp[6], src2.xyz = temp[5]
     CMP temp[2].x, src0.x__, src1.x__, -src2.x__
....

This will be pair scheduled to:
Fragment Program: after 'pair scheduling'
  0: src0.xyz = input[0], src1.xyz = const[5]       // original inst 0
     MAD temp[0].xyz, src0.xxx, src1.Hyz, src0.000
  1: src0.xyz = const[1], src1.xyz = const[6]       // original inst 1
     MAD temp[1].xyz, src0.xxx, src0.111, -src1.x1z
  2: src0.xyz = const[2], src1.xyz = const[6]       // original inst 11
     MAD temp[5].xyz, src0.xxx, src0.111, -src1.x1
  3: src0.xyz = temp[1]                             // original inst 2
     CMP temp[1].xyz, src0.000, src0.111, src0.xyz
  4: src0.xyz = temp[1], src1.xyz = temp[0], src2.xyz = input[0]
     MAX temp[4].x, src0.x__, src0.z__              // original inst 5
     CMP temp[2].w, src1.x, src2.x, -src0.y         // original inst 3
  5: src0.xyz = input[0], src1.xyz = temp[0], src2.xyz = temp[1]
     CMP temp[3].w, src0.x, src1.x, -src2.z         // original inst 4
  6: src0.xyz = temp[5], src0.w = temp[2], src1.xyz = input[0], src2.xyz = temp[1]
     CMP temp[5].xyz, src0.000, src0.111, src0.xyz  // original inst 12
     CMP temp[5].w, src1.x, src0.w, -src2.x         // original inst 8
  7: src0.xyz = temp[0], src0.w = temp[5], src1.xyz = temp[2], src2.xyz = temp[5]
     CMP temp[6].x, src0.y__, src0.w__, -src2.y__   // original inst 13
  8: src0.xyz = temp[5], src0.w = temp[3], src1.xyz = input[0], src2.xyz = temp[1]
     MAX temp[8].x, src0.x__, src0.z__              // original inst 15
     CMP temp[5].w, src0.w, src1.x, -src2.x         // original inst 7
  9: src0.xyz = temp[3], src0.w = temp[5], src1.xyz = temp[0], src2.xyz = temp[5]
     CMP temp[7].x, src0.w__, src1.y__, -src2.z__   // original inst 14
 10: src0.xyz = temp[2], src0.w = temp[5], src1.xyz = temp[6], src2.xyz = temp[5]
     CMP temp[2].x, src0.w__, src1.x__, -src2.x__   // original inst 18
 11: src0.xyz = temp[7], src0.w = temp[5], src1.xyz = temp[3], src2.xyz = temp[5]
     CMP temp[3].x, src0.x__, src0.w__, -src2.x__   // original inst 17
....

The problem is that instruction 11 (which was instruction 17 before the scheduling) now reads
a wrong source for src0. It initially used the result of instruction 8 (now scheduled as 6),
but now it reads from instruction 8 (corresponding to instruction 7 before the scheduling).

The bug is quite subtle and needs few conditions to reproduce:
- there is a loop, therefore we skip the the register rename
  pass and hence don't have the ssa-like form,
- there are at least two rgb instructions writing the same register
  and both are convertible to alpha instruction,
- there is excess of rgb instructions, so that the conversion actually
  happens.

So what happens, while scheduling instructions, the scheduler will
recognize there are no alpha instruction to pair the rgb ones with
and convert some to alpha. It primarily tries to use the same register,
just reuse the alpha channel.

Why it happens? We are tracking the usage of registers in the block
being scheduled and when we rewrite something we move the users tracked
by the reg_value structures to the new register. The problem is that when
we do this, the current code expects that the code is in the ssa-like
form. Here it is not (because of the loop) and when we convert the
original instruction 2, we move the dependency information about the
temp[2].x to temp[2].w. When we later convert instruction 8, which also
writes temp[2].x, the original dependency info is gone, and when we copy
that to the new reg (temp[5].w), we just set it to NULL and it means we
don't mark it as used effectively, and later wrongly use it again when
we look for a next empty register.

Fix this by not deleting the original dependency info. We can't reuse the
reg now, but it doesn't matter, because the regalloc later can sort it out.
There are no changes in the shader-db.

Fixes: dEQP-GLES2.functional.shaders.indexing.tmp_array.float_dynamic_write_dynamic_loop_read_fragment
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6508

Reviewed-by: Filip Gawin <filip@gawin.net>
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18621>
 2022-09-18 18:25:08 +00:00
Vinson Lee bbd549205c pan/bi: Fix memory leaks. 
Fix defects reported by Coverity Scan.

Resource leak (RESOURCE_LEAK)
leaked_storage: Variable used going out of scope leaks the storage it points to.
leaked_storage: Variable multiple_uses going out of scope leaks the storage it points to.

Fixes: 8fb415fee2 ("pan/bi: Reduce some moves when going out-of-SSA")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18653>
 2022-09-18 10:18:04 -07:00
Alyssa Rosenzweig bcd75a13e0 asahi: Identify shared memory layouts 
Somehow maps to the tile size. Not sure about the details yet.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
 2022-09-18 10:34:37 -04:00
Alyssa Rosenzweig b8b3c9fa2a asahi: Identify pixel stride 
Number of bytes in a pixel in the tilebuffer, does not depend on the
tile size.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
 2022-09-18 10:34:37 -04:00
Alyssa Rosenzweig 933a9e350e asahi: Overhaul USC control packing 
Break up the monolithic SET_SHADER_EXTENDED packet into the separate
underlying commands (some only 2-byte sized and aligned), and add a
builder for USC control streams like we did for PPP updates to make that
change manageable.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
 2022-09-18 10:34:37 -04:00
Alyssa Rosenzweig 35d5558fa5 asahi/genxml: Overflow up to words when packing 
So we can pack things that aren't 4-byte sized. Note this doesn't help
with alignment.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
 2022-09-18 10:34:37 -04:00
Alyssa Rosenzweig 22d3756207 asahi: Consolidate magic numbers for USC controls 
Aka "pipeline" states. It's another command/control stream.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
 2022-09-18 10:34:37 -04:00
Alyssa Rosenzweig 09cc736c42 asahi: Identify shared memory fields 
For compute kernels, this encodes how much workgroup-local memory is
used ("shared memory" or "threadgroup memory" or "local memory"). This
memory is partitioned by the hardware.

For fragment shaders, this... encodes exactly the same thing. There is
no traditional tilebuffer in AGX, instead local memory is interpreted as
an imageblock, where each workgroup is a tile. This is a nifty design.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
 2022-09-18 10:34:37 -04:00
Alyssa Rosenzweig 43ed48d169 asahi: Simplify IOGPU attachment packing 
Give bigger ranges, it's simpler and less broken for layered
framebuffers.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
 2022-09-18 10:34:37 -04:00
Alyssa Rosenzweig 2fbe1ae09c asahi: Identify spill buffer histogram 
Histogram of sizes of the spill buffer, with logarithmic bucket sizes
(relative to the amount spilled from the perspective of a single thread).
Pretty funny.

Also mark a few unknowns that are nonzero when spilling is used.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
 2022-09-18 10:34:37 -04:00
Alyssa Rosenzweig 22de011675 asahi: Use the internal format internally 
Confusingly, after creation rsrc->base.format will contain the external
format due to u_transfer_helper quirks. For our internal use, we need to
look at the internal format, rsrc->layout.format. With the new layout
code, the rsrc->internal_format property is redundant, so we delete
that to reduce confusion.

Fixes dEQP-GLES3.functional.texture.format.sized.2d.depth32f_stencil8_*

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
 2022-09-18 10:34:29 -04:00
Alyssa Rosenzweig dc05b042ab asahi: Assert that u_transfer_helper is well-behaved 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
 2022-09-18 10:34:29 -04:00
Alyssa Rosenzweig adfd213241 asahi: Decode IOGPU compute header 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
 2022-09-18 10:34:25 -04:00
Alyssa Rosenzweig a9c26df462 asahi: Identify IOGPU compute header 
Much simpler than the graphics one.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
 2022-09-18 10:34:25 -04:00
Alyssa Rosenzweig 58d138334d asahi: Shuffle IOGPU structs 
We need the header to be common between gfx and compute, but everything
else seems to be different. Shuffle so we can decode compute without any
terrible hacks.

I don't know the exact layout and don't care: the layout of the fields
here is all software defined in macOS, even though the *values* are
defined by hardware (or firmware in a few cases).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
 2022-09-18 10:34:25 -04:00
Alyssa Rosenzweig 287a0d4f40 asahi: Decode CDM commands separate from VDM 
This gets correct handling of CDM stream link/terminate, which are
encoded in a slightly different way from VDM.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
 2022-09-18 10:34:25 -04:00
Alyssa Rosenzweig 4e8a586fd3 asahi: Identify CDM block types 
Same enum as PowerVR CDM, annoyingly different from the VDM block types.
Split out the stream link / terminate structs (both observed with Metal
for copious amounts of compute), in preparation for decoding "properly".

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
 2022-09-18 10:34:25 -04:00
Alyssa Rosenzweig 1400733320 asahi: Identify ZLS Control word from PowerVR 
We're into the cr.xml file now, which is the blob that gets passed
through the kernel.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
 2022-09-18 10:34:25 -04:00
Alyssa Rosenzweig b0f8639382 asahi: Assert cache line alignment on Z/S buffers 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
 2022-09-18 10:34:25 -04:00
Erik Faye-Lund 8a8fe0594c u_transfer_helper: rip out fake_rgtc code 
This is no longer in use, so let's get rid of it!

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18564>
 2022-09-18 13:46:25 +02:00
Erik Faye-Lund 719294ea51 freedreno: do not fake rgtc-support 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18564>
 2022-09-18 13:46:25 +02:00
Erik Faye-Lund 84a30f0372 mesa/st: enable latc extensions with fallback 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18564>
 2022-09-18 13:46:23 +02:00
Erik Faye-Lund 559d68d25c mesa/st: do not fall back to uncompressed for latc 
This logic doesn't really do what it pretends to; we don't expose the
RGTC features unless we actually have LATC support. This is about to
change, but for that logic to work, we need to be able to tell if we're
using a fallback-format or not, and we can't do that unless we keep the
format as LATC.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18564>
 2022-09-18 13:45:56 +02:00
Erik Faye-Lund 1b72045393 mesa/st: implement fallback for latc 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18564>
 2022-09-18 13:45:56 +02:00
Erik Faye-Lund 6553e02a0b mesa/main: add support for latc in _mesa_unpack_rgtc 
RGTC and LATC unpacks in the same way, just to different formats. So
let's add support for unpacking that in this helper.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18564>
 2022-09-18 13:45:56 +02:00
Erik Faye-Lund e92a1308d5 mesa: add format-helper for latc 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18564>
 2022-09-18 13:45:56 +02:00
Erik Faye-Lund b511671d03 mesa/st: add context-flag for latc 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18564>
 2022-09-18 13:45:56 +02:00
Erik Faye-Lund a8e35ee904 lima: do not align width/height for non-shared resources 
Otherwise we end up computing the wrong pitch for miplevels on NPOT
textures.

This fixes a bunch of piglit.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18618>
 2022-09-18 12:47:39 +02:00
Erik Faye-Lund 1e19e99ea7 lima: don't store width in resource-level 
We only write to it, we never read from it. Just drop it.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18618>
 2022-09-18 12:47:39 +02:00
Dmitry Baryshkov 9d3a5c916c freedreno/registers: update hdmi registers to add more 8x74 regs 
Define more HDMI PHY/PLL registers used on msm8x74/apq8084 platforms.
Register names are defined in clock-mdss-8974.c (msm-3.10).

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18629>
 2022-09-17 17:12:13 +00:00
Kai Wasserbäch e4c7cf1568 chore(docs): rusticl: improve list of build dependencies 
v2:
 - added more requirements for LLVM (thanks Mike Lothian (@FireBurn)).
v3:
 - note the optional cases for rustfmt (thanks @LingMan)
 - remove the part about the SPIR-V target for LLVM (thanks Karol Herbst
   (@karolherbst))
v4:
 - added minimum version requirements (thanks Karol Herbst
   (@karolherbst))

Signed-off-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18640>
 2022-09-17 15:20:37 +02:00
Erik Faye-Lund 345f52661c docs: update staus of mark GL_ARB_texture_compression_bptc 
This is now done for all drivers that supports half-float and sRGB
textures. Update features.txt to reflect this.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18574>
 2022-09-17 10:03:12 +00:00
Thomas H.P. Andersen 569ade73b4 panvk: Implement VK_KHR_descriptor_update_template 
Based on original patch by Jason Ekstrand

Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14780>
 2022-09-17 03:32:29 +00:00
Jason Ekstrand 42d60aa0bc panvk: Fix buffer views 
Instead of overwriting the BO map pointer, write into the BO map
pointer. Drp...  Also, drop an unnecessary & accessing
panvk_buffer_view::tex.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14780>
 2022-09-17 03:32:29 +00:00
Jason Ekstrand c63cb7f4d2 vulkan/runtime: Compact descriptor update templates 
Get rid of any zero-sized entries so drivers never even have to think
about this case when using templates.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14780>
 2022-09-17 03:32:29 +00:00
Thomas H.P. Andersen 74cebc5d5d hasvk: Switch to the common descriptor update template struct 
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14780>
 2022-09-17 03:32:29 +00:00