Commit Graph

138994 Commits

Author SHA1 Message Date
Alyssa Rosenzweig c06dcaf0a0 agx: Implement native int->float conversions
This time 8, 16, and 32-bit sources are supported natively, but not
64-bit.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-05-02 17:41:15 -04:00
Alyssa Rosenzweig 2126848771 agx: Implement native float->int conversions
No 8-bit or 64-bit yet since those need lowerings.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-05-02 17:41:14 -04:00
Alyssa Rosenzweig 8191adb0d9 agx: Add minifloat tests
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-05-02 17:41:14 -04:00
Alyssa Rosenzweig c89ab07996 agx: Add 8-bit AGX minifloat routines
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-05-02 17:41:14 -04:00
Alyssa Rosenzweig 1f77aa95ec agx: Implement fsin/fcos
First, we lower to fsin_agx and some ALU in NIR. Then, we implement
fsin_agx with the underlying transcental ops.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-05-02 17:41:14 -04:00
Alyssa Rosenzweig b5a3845f9a agx: Implement simple floating point ops
These are all direct translations of NIR->AIR.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-05-02 17:41:14 -04:00
Alyssa Rosenzweig 8648b2be0b agx: Implement ld_vary
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-05-02 17:41:13 -04:00
Alyssa Rosenzweig e54fdc0fac agx: Terminate programs with stop and traps
The function of stop is clear. The function of trap, let alone a whole
sled of them, is less so. Maybe a debugging feature for later.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-05-02 17:41:13 -04:00
Alyssa Rosenzweig 5b34cc40ca agx: Add st_vary(_final) instruction packing
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-05-02 17:41:13 -04:00
Alyssa Rosenzweig 7832945747 agx: Add packing for memory loads/stores
Encoding is dramatically different from ALU.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-05-02 17:41:13 -04:00
Alyssa Rosenzweig f2d264e191 agx: Add instruction packing
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-05-02 17:41:13 -04:00
Alyssa Rosenzweig c215895eae agx: Add a trivial register allocator
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-05-02 17:41:12 -04:00
Alyssa Rosenzweig 583684b5a7 agx: Add instruction printing
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-05-02 17:41:12 -04:00
Alyssa Rosenzweig 8af9822d14 agx: Implement fragment_out
For a single colour render target.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-05-02 17:41:12 -04:00
Alyssa Rosenzweig 0079783428 agx: Implement vec2/vec3/vec4 ops
As p_combine, to un-stub emit_alu.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-05-02 17:41:12 -04:00
Alyssa Rosenzweig 7ad11e3923 agx: Add agx_alu_src_index helper for emit_alu
Since we don't use abs/neg in NIR, this just needs to construct
p_extract ops to deal with swizzles.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-05-02 17:41:12 -04:00
Alyssa Rosenzweig 22886f50f9 agx: Implement direct st_vary
Indirection can come later, if at all..

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-05-02 17:41:11 -04:00
Alyssa Rosenzweig fde66f0aa8 agx: Implement load_const as mov
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-05-02 17:41:11 -04:00
Alyssa Rosenzweig 2bfe1a61c5 agx: Stub emit_intrinsic
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-05-02 17:41:11 -04:00
Alyssa Rosenzweig 075e6be90c agx: Stub NIR instruction iteration
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-05-02 17:41:11 -04:00
Alyssa Rosenzweig 186c56a2d4 agx: Stub control flow walking
From Bifrost. We'll need to diverge (no pun intended) due to exec_mask
handling specific to Apple.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-05-02 17:41:10 -04:00
Alyssa Rosenzweig 8b8c1a2827 agx: Remap varyings to match AGX ABI
It's not clear if this is software or hardware defined, but until we
know more about linkage, let's match the blob. Fixes dEQP issues with
gl_PointSize.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-05-02 17:41:10 -04:00
Alyssa Rosenzweig 2470a080d2 agx: Stub NIR backend compiler
A fork of the Bifrost compiler, tailored to AGX. nir_register support is
removed, as I want to use an SSA-based allocator for AGX. (There are no
VLIW-like requirements and extremely limited vector semantics, so we can
use an ACO approach with ease.)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-05-02 17:41:10 -04:00
Alyssa Rosenzweig 719bf5152f agx: Generate builder routines
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-05-02 17:41:10 -04:00
Alyssa Rosenzweig 07f87500e3 agx: Generate runtime-accessible opcode table
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-05-02 17:41:10 -04:00
Alyssa Rosenzweig c9fe9ce998 agx: Generate opcode list
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-05-02 17:41:09 -04:00
Alyssa Rosenzweig 50b5c94885 agx: Add opcode descriptions as Python
Pattern lifted from NIR.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-05-02 17:41:09 -04:00
Alyssa Rosenzweig 972409dacb asahi: Stub command-line compiler for AGX G13B
Based on the Bifrost standalone compiler, which was based on Midgard's
standalone compiler, which was based on Freedreno's standalone compiler,
which was.....

It's like sour dough!

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-05-02 17:41:09 -04:00
Alyssa Rosenzweig 0ea67e57e5 nir: Add fsin_agx opcode
Used to split up the fsin/fcos lowering for AGX between NIR and the
backend, to permit algebraic optimizations without polluting NIR with
too many hardware details. The backend NIR lowering produces an
fmul/ffma of the input so we can optimize code like sin(2*x).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-05-02 17:41:09 -04:00
Alyssa Rosenzweig e07a2a0f18 util/bitset: Add BITSET_COUNT helper
Expressible as a prefix sum but that's a bit unnatural, so add a
convenience helper.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mike Blumenkrants <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10581>
2021-05-02 20:38:28 +00:00
Lionel Landwerlin 231651fd89 anv: implement VK_KHR_fragment_shading_rate
Available on Gen11+.

v2: Order shading rate in correct order (Samuel)

v3: Move CPS_STATE emission to genX_state.c

v4: Don't override various output structures (Jason)

v5: Rebase on top master (Lionel)

v6: Fix invalid VkPhysicalDeviceFragmentShadingRatePropertiesKHR
    (min|max)FragmentShadingRateAttachmentTexelSize values (Ken)
    Drop #endif comment

v7: Limit extension to Gfx11+ (Lionel)
    Support conservative raster (Lionel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
2021-05-02 20:20:06 +00:00
Jason Ekstrand 34c560ae95 intel/fs: Stop using brw_dp_read/write_desc in Gen7+ only code
Those helpers exist primarily to sort out some of the weirdness around
Gen4-6 dataport access.  On Gen5 and earlier, everything was called
"dataport" and, instead of the SFID we have today there was a "target
cache" parameter in the descriptor.  There are also some bits that moved
around on various gens depending on read vs. write.  Starting with Gen6,
most things which target one of the data cache SFIDs should use
brw_dp_desc() instead.

v2: Drop backward comment (Ken)

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
2021-05-02 20:20:06 +00:00
Jason Ekstrand 2e7656ae2f intel/eu: SVB writes only happen on Gen6
It's a Gen6 XFB thing.  It's never used for anything else so there's no
point in having a target cache switch.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
2021-05-02 20:20:06 +00:00
Lionel Landwerlin 0421690f83 intel/compiler: add restrictions related to coarse pixel shading
v2: Update to BITSET_TEST()

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
2021-05-02 20:20:06 +00:00
Lionel Landwerlin 81f369c93b intel/compiler: add coarse pixel offset on Gfx12.5+
Gfx12.5 has a slightly different code path.

v2: Document the oddness

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
2021-05-02 20:20:06 +00:00
Lionel Landwerlin 6d4070f3dd intel/compiler: add support for fragment coordinate with coarse pixels
v2: Drop new internal opcodes (Jason)
    Simplify code (Jason)

v3: Add Z computation for coarse pixels

v4: Document things a little

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
2021-05-02 20:20:06 +00:00
Lionel Landwerlin a297061524 intel/compiler: add support for fragment shading rate variable
v2: Drop old register type initializers (Jason)
    Simplify instruction snippet (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
2021-05-02 20:20:06 +00:00
Lionel Landwerlin b6332fc4a8 intel/compiler: handle coarse pixel in render target writes descriptors
v2: Use the new inst->ex_desc field (Jason)

v3: Drop CPS LoD compensation from sampler messages (Lionel)

v4: Drop useless uses_rate_shading (Ken)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
2021-05-02 20:20:06 +00:00
Lionel Landwerlin d665c2dcf0 intel/compiler: use existing helpers to pull bits of descriptors
v2: Use new RT descriptor helper

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
2021-05-02 20:20:06 +00:00
Lionel Landwerlin 64551610d1 intel/compiler: rework message descriptors for render targets
Render target message descriptors are slightly different from the
dataport ones. In particular the msg_type field is on bits 14:17 for
RT while bits 14:18 for DP.

v2: Drop unused send_commit_msg field in brw_fb_write_desc() (Ken)

v3: Rebase on top renaming (Lionel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
2021-05-02 20:20:06 +00:00
Lionel Landwerlin dabaaaf6c7 intel/compiler: make sure we keep the lowest dispatch limit
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
2021-05-02 20:20:06 +00:00
Lionel Landwerlin 4dcfb18a82 intel/decoder: decode CPS_STATE
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
2021-05-02 20:20:06 +00:00
Lionel Landwerlin b1622af394 intel/genxml: Add coarse pixel shading instructions
v2: Add Gen12.5

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
2021-05-02 20:20:06 +00:00
Lionel Landwerlin bbfc959d03 intel/dev: printout correct subslice/dualsubslice name
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
2021-05-02 20:20:06 +00:00
Rob Clark f3d2fade82 freedreno: Fix TC last_fence optimization
Grabbing the fence value in fd_fence_repopulate() without waiting on
fd_submit_fence::ready doesn't work with async flushes, since we are
waiting for the first flush to complete (ie. we don't have the kernel-
side fence value yet).  Just simplify it and make the "repopulated"
fence delagate to the original fence.

Fixes: e9a9ac6f77 ("freedreno/drm: Async submit support")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4726
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10567>
2021-05-02 15:17:25 +00:00
Rob Clark c554757bc2 freedreno/drm: Initialize control->fence
Don't rely on getting a zero'd out buffer, we could hit the bo-cache.

Fixes: 7dabd62464 ("freedreno/drm: Userspace fences")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10567>
2021-05-02 15:17:25 +00:00
Vasily Khoruzhick 636a7cf84b lima: switch resource to linear layout if there's to many full updates
Overwriting entire resource multiple times indicates streaming and in this
case it's more efficient to use linear layout to avoid expensive linear->tiled
conversions.

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10572>
2021-05-02 14:55:13 +00:00
Vinson Lee d6356b81a4 glx: Fix macOS build.
In file included from ../src/glx/apple/apple_glx_context.c:49:
../src/glx/glxclient.h:56:10: fatal error: 'loader.h' file not found
         ^~~~~~~~~~

Fixes: 1cb664c15c ("glx: s/dri_message/glx_message/")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4702
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10568>
2021-05-02 14:16:07 +00:00
Bastian Beranek 960c86d678 glx: Assign unique serial number to GLXBadFBConfig error
Since commit f39fd3dce7 a new GLX error is issued in case context creation
fails. This broke wine on certain hardware: While wine installs an error handler
to ignore this kind of error, it does not function because it expects the
dpy->request serial number of the error to be incremented since the installation
of the handler.

Workaround this by artificially increasing the request number. This also
guarantees a unique serial number for the error.

Fixes: f39fd3dce7
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3969
Signed-off-by: Bastian Beranek <bastian.beischer@rwth-aachen.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10565>
2021-05-02 00:36:03 +00:00
Ilia Mirkin 3326861f4f nv50: add indirect compute support
There's no hardware support for anything indirect, so just read the
parameters out.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
2021-05-01 20:04:21 +00:00