Commit Graph

42617 Commits

Author SHA1 Message Date
Jakob Bornecrantz 8fb0ecd0cf i915g: Lazy emit dynamic state 2011-02-24 00:26:02 +00:00
Jakob Bornecrantz b9baad2aff i915g: Lazy emit immediate state 2011-02-24 00:26:02 +00:00
Jakob Bornecrantz 69cfc16cb6 i915g: Disable LIS7 state updates for now 2011-02-24 00:26:02 +00:00
Jakob Bornecrantz 42b8b2be85 i915g: Clean up in i915_state_immediate 2011-02-24 00:26:02 +00:00
Jakob Bornecrantz 481fad1552 i915g: Remove outdated comment 2011-02-24 00:26:02 +00:00
Jakob Bornecrantz fbd681f1a0 i915g: Use dump function in sw winsys 2011-02-24 00:26:02 +00:00
Jakob Bornecrantz fc77dee0bd i915g: Enable mirror repeat wrap mode 2011-02-24 00:26:02 +00:00
Jakob Bornecrantz 4407e5078f i915g: Always set vbo to flush on flushes
Reported-by Chris Wilson <chris@chris-wilson.co.uk>
2011-02-24 00:26:02 +00:00
Chris Wilson 671018aa99 intel: gen3 is particular sensitive to batch size
... and prefers a small batch whereas gen4+ prefer a large batch to
carry more state.

Tuning using openarena/padman indicate that a batch size of just 4096 is
best for those cases.

Bugzilla: https://bugs.freedesktop.org/process_bug.cgi
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-23 23:11:26 +00:00
Chris Wilson 19ac5fa50d i915: And remember assign the new value to the state reg...
Fixes regression from 298ebb78de.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34589
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-23 22:10:43 +00:00
Tom Fogal 4484297505 Fix GLX_USE_TLS define.
It was only getting set in the case of DRI drivers.
2011-02-23 10:40:26 -07:00
Fabian Bieler 0ed5bf668d r600g: Request DWORD aligned vertex buffers.
The spec says that the offsets in the vertex-fetch instructions need to be byte-aligned and makes no specification with regard to the required alignment of the offset and stride in the vertex resource constant register.

However, testing indicates that all three values need to be DWORD aligned.
2011-02-23 11:42:32 -05:00
Wiktor Janas b65e2195c4 st/mesa: fix computing the lowest address for interleaved attribs
Ptr can be very well NULL, so when there are two arrays, with one having
offset 0 (and thus NULL Ptr), and the other having a non-zero offset,
the non-zero value is taken as minimum (because of !low_addr ? start ...).
On 32-bit systems, this somehow works. On 64-bit systems, it leads to crashes.

Signed-off-by: Marek Olšák <maraeo@gmail.com>
2011-02-23 15:19:37 +01:00
Brian Paul 6d1f28d6c0 vbo: added vbo_check_buffers_are_unmapped() debug function 2011-02-22 14:32:37 -07:00
Brian Paul bcd017f16f vbo: removed unused #defines, add comments 2011-02-22 14:23:50 -07:00
Brian Paul eb24a5a9be mesa: move comment, change debug code 2011-02-22 13:37:30 -07:00
Brian Paul d7fcb2ac81 vbo: simplify NeedFlush flag clearing 2011-02-22 13:31:09 -07:00
Brian Paul d8aebc4e4b vbo: use ctx intstead of exec->ctx 2011-02-22 13:24:56 -07:00
Brian Paul cbe47a2459 r300g: fix missing initializers warning 2011-02-22 12:47:18 -07:00
Brian Paul 7898d2ae16 i915g: remove extra semicolons 2011-02-22 12:47:18 -07:00
Andy Skinner 90e227f079 xlib: pass Display pointer to XMesaGarbageCollect()
Fixes an issue when different displays are used on different threads.

Signed-off-by: Brian Paul <brianp@vmware.com>
2011-02-22 12:47:17 -07:00
Kenneth Graunke 2bfc23fb86 i965: Increase Sandybridge point size clamp.
255.875 matches the hardware documentation.  Presumably this was a typo.

Found by inspection.  Not known to fix any issues.

Reviewed-by: Eric Anholt <eric@anholt.net>
2011-02-22 10:52:45 -08:00
Kenneth Graunke 4a3b28113c i965/fs: Correctly set up gl_FragCoord.w on Sandybridge.
pixel_w is the final result; wpos_w is used on gen4 to compute it.

NOTE: This is a candidate for the 7.10 branch.

Reviewed-by: Eric Anholt <eric@anholt.net>
2011-02-22 10:52:44 -08:00
Kenneth Graunke df2aef0e19 i965/fs: Refactor control flow stack handling.
We can't safely use fixed size arrays since Gen6+ supports unlimited
nesting of control flow.

NOTE: This is a candidate for the 7.10 branch.

Reviewed-by: Eric Anholt <eric@anholt.net>
2011-02-22 10:52:44 -08:00
Kenneth Graunke 2c2686b912 i965/fs: Avoid register coalescing away gen6 MATH workarounds.
The code that generates MATH instructions attempts to work around
the hardware ignoring source modifiers (abs and negate) by emitting
moves into temporaries.  Unfortunately, this pass coalesced those
registers, restoring the original problem.  Avoid doing that.

Fixes several OpenGL ES2 conformance failures on Sandybridge.

NOTE: This is a candidate for the 7.10 branch.

Reviewed-by: Eric Anholt <eric@anholt.net>
2011-02-22 10:52:44 -08:00
Kenneth Graunke 72cd7e87d3 i965/fs: Apply source modifier workarounds to POW as well.
Single-operand math already had these workarounds, but POW (the only two
operand function) did not.  It needs them too - otherwise we can hit
assertion failures in brw_eu_emit.c when code is actually generated.

NOTE: This is a candidate for the 7.10 branch.

Reviewed-by: Eric Anholt <eric@anholt.net>
2011-02-22 10:52:44 -08:00
Kenneth Graunke 3e91070ea8 i965: Fix shaders that write to gl_PointSize on Sandybridge.
gl_PointSize (VERT_RESULT_PSIZ) doesn't take up a message register,
as it's part of the header.  Without this fix, writing to gl_PointSize
would cause the SF to read and use the wrong attributes, leading to all
kinds of random looking failure.

Reviewed-by: Eric Anholt <eric@anholt.net>
2011-02-22 10:52:44 -08:00
José Fonseca c6cedd43fe mesa: Avoid undeclared ffs function warning on mingw. 2011-02-22 14:59:09 +00:00
José Fonseca 7aeb610fe1 gallium: s/PIPE_TRANSFER_CPU_READ/PIPE_TRANSFER_READ/ in comments. 2011-02-22 14:14:45 +00:00
José Fonseca 0562f44625 gallium/docs: Update PIPE_TRANSFER_xx docs. Reformat to use definitions. 2011-02-22 14:14:22 +00:00
Keith Whitwell fad8497d3b gallium: new transfer flag: DISCARD_WHOLE_RESOURCE 2011-02-22 14:13:07 +00:00
Marek Olšák 695cdee678 st/mesa: fix crash when using both user and vbo buffers with the same stride
If two buffers had the same stride where one buffer is a user one and
the other is a vbo, it was considered to be one interleaved buffer,
resulting in incorrect rendering and crashes.

This patch makes sure that the interleaved buffer is either user or vbo,
not both.
2011-02-20 22:16:22 +01:00
Marek Olšák 7942e6a5ae st/mesa: fix crash when DrawBuffer->_ColorDrawBuffers[0] is NULL
This fixes the game Tiny and Big.
2011-02-20 22:16:22 +01:00
Chris Wilson 3adc108b4a i965: Trim the interleaved upload to the minimum number of vertices
... should have no impact on a properly formatted draw operation.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-22 11:24:47 +00:00
Chris Wilson b4cbd2b312 i965: Reinstate max-index paranoia
Don't trust the applications not to reference beyond the end of the
vertex buffers.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-22 11:24:45 +00:00
Chris Wilson 3377faffcd i965: Zero the offset into the vbo when uploading non-interleaved
Fixes regression from 559435d915.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-22 11:24:34 +00:00
Jakob Bornecrantz 94ccc31ba4 st/dri: Track drawable context bindings
Needs to track this ourself since because we get into a race condition with
the dri_util.c code on make current when rendering to the front buffer.

This is what happens:
Old context is rendering to the front buffer.

App calls MakeCurrent with a new context. dri_util.c sets
drawable->driContextPriv to the new context and then calls the driver make
current. st/dri make current flushes the old context, which calls back into
st/dri via the flush frontbuffer hook. st/dri calls dri loader flush
frontbuffer, which calls invalidate buffer on the drawable into st/dri.

This is where things gets wrong. st/dri grabs the context from the dri
drawable (which now points to the new context) and calls invalidate
framebuffer to the new context which has not yet set the new drawable as its
framebuffers since we have not called make current yet, it asserts.
2011-02-20 16:31:48 +01:00
Eric Anholt 9e872a5865 i965: Fix VB packet reuse when offset for the new buffer isn't stride aligned.
Fixes regression in scissor-stencil-clear and 5 other tests.
2011-02-21 16:36:09 -08:00
Brian Paul 12f25eb6d5 Revert "mesa: convert macros to inline functions"
This reverts commit e9ff76aa81.

Need to use macros so __FUNCTION__ reports the caller.
2011-02-21 17:01:00 -07:00
Brian Paul e2d108ec82 st/mesa: need to translate clear color according to surface's base format
When clearing a GL_LUMINANCE_ALPHA buffer, for example, we need to convert
the clear color (R,G,B,A) to (R,R,R,A).  We were doing this for texture border
colors but not renderbuffers.  Move the translation function to st_format.c
and share it.

This fixes the piglit fbo-clear-formats test.

NOTE: This is a candidate for the 7.9 and 7.10 branches.
2011-02-21 16:58:42 -07:00
Brian Paul c966c6980c st/mesa: fix the default case in st_format_datatype()
Part of the fix for piglit fbo-clear-formats

NOTE: This is a candidate for the 7.9 and 7.10 branches.
2011-02-21 16:58:42 -07:00
Daniel Vetter 55a3c35243 i915g: add some throttling
Intel classic drivers switched to this, too, so it must be good.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2011-02-21 23:42:54 +00:00
Daniel Vetter 1e966636d0 i915g: s/bool/boolean/ style-fixup in winsys
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2011-02-21 23:42:53 +00:00
Jakob Bornecrantz 593ba7b05b i915g: Fix warning 2011-02-21 23:42:53 +00:00
Jakob Bornecrantz 43e6fe5549 i915g: Add option to lie about caps 2011-02-21 23:42:53 +00:00
Jakob Bornecrantz 27b49e91c9 i915g: Move debug fields to screen 2011-02-21 23:42:53 +00:00
Jakob Bornecrantz fe6800a1bb i915g: Use debug get once options 2011-02-21 23:42:53 +00:00
Jakob Bornecrantz 3c74ecf687 i915g: Rework texture tiling a bit 2011-02-21 23:42:53 +00:00
Jakob Bornecrantz e7e1fd057e i915g: Anisotropic filtering works 2011-02-21 23:42:53 +00:00
Jakob Bornecrantz a641766576 i915g: TODO about point sprites 2011-02-21 23:42:53 +00:00