Commit Graph

159417 Commits

Author SHA1 Message Date
David Heidelberg 86d6c60eab ci/lava: print set-job-env-vars.sh as other setups do
Let's be consistent.
Also needed for parsing device and traces yml file from logs.

Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18422>
2022-09-08 17:13:19 +00:00
David Heidelberg 96243ca6fa ci: print env as other setups do
Let's be consistent.
Also needed for parsing device and traces yml file from logs.

Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18422>
2022-09-08 17:13:19 +00:00
Emma Anholt e1f032acc3 zink: Don't lower indirect derefs of temp arrays.
nir_to_spirv can handle it.  Cuts instructions in a turnip CS shader on
Aztec Ruins from 36k to 3k.

Part of #6115

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18374>
2022-09-08 16:44:28 +00:00
Emma Anholt 09f6acc4b7 zink: Don't upload shader immediate arrays through UBO 0.
Trust the host vulkan driver to load it through whatever way it finds to
be most efficient.  Saves upload on the frontend when other uniforms
change.

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18374>
2022-09-08 16:44:28 +00:00
Mike Blumenkrantz a0f6fecc6a zink: flag all assigned output slots as mapped
this ensures types which consume more than 1 slot are effectively tagged
so that the next stage inputs are also assigned properly

fixes:
spec@arb_enhanced_layouts@execution@component-layout@vs-fs-array-dvec3

cc: mesa-stable

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18444>
2022-09-08 16:10:42 +00:00
James Park c48c53c21f vulkan: Augment _WIN32 stub comparison
Make current check robust to incremental linking.

Compare JMP targets if the first byte is opcode 0xE9.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18400>
2022-09-08 15:37:11 +00:00
Kenneth Graunke 19fc870ac6 intel/compiler: Use subgroup invocation for ICP handle loads
When loading a TCS or GS input, we generate some code to read the URB
handle for a particular input control point (ICP handle), which often
involves indirect addressing due to a non-constant vertex.

For example:

   mov(8) vgrf148+0.0:UW, 76543210V
   shl(8) vgrf149:UD, vgrf148+0.0:UW, 2u
   shl(8) vgrf150:UD, vgrf145:UD, 5u
   add(8) vgrf151:UD, vgrf150:UD, vgrf149:UD
   mov_indirect(8) vgrf147:UD, g2:UD, vgrf151:UD, 96u

Unfortunately, the first load with 76543210V is considered a partial
write because the 8 channels of 16-bit UW data doesn't fill an entire
register, and we can't allocate VGRFs at sub-register granularity.

This causes none of the above math to be CSE'd, even though the first
two instructions are common to *all* input loads, and the rest may be
reused sometimes as well.

To work around this, we stop emitting 76543210V to a temporary, and
instead use nir_system_values[SYSTEM_VALUE_SUBGROUP_INVOCATION], which
already contains this value, and is unconditionally set up for us.
With all input loads using the same register for the sequence, our
CSE pass is able to eliminate the rest of the common math.

shader-db results on Tigerlake:

   total instructions in shared programs: 20748243 -> 20744844 (-0.02%)
   instructions in affected programs: 73410 -> 70011 (-4.63%)
   helped: 242 / HURT: 21
   helped stats (abs) min: 1 max: 37 x̄: 14.17 x̃: 15
   helped stats (rel) min: 0.17% max: 19.58% x̄: 6.13% x̃: 6.32%
   HURT stats (abs)   min: 1 max: 4 x̄: 1.38 x̃: 1
   HURT stats (rel)   min: 0.18% max: 1.31% x̄: 0.58% x̃: 0.58%
   95% mean confidence interval for instructions value: -13.73 -12.12
   95% mean confidence interval for instructions %-change: -6.00% -5.19%
   Instructions are helped.

   total cycles in shared programs: 785828951 -> 785788480 (<.01%)
   cycles in affected programs: 597593 -> 557122 (-6.77%)
   helped: 227 / HURT: 13
   helped stats (abs) min: 6 max: 624 x̄: 182.19 x̃: 185
   helped stats (rel) min: 0.24% max: 18.22% x̄: 7.85% x̃: 7.80%
   HURT stats (abs)   min: 2 max: 153 x̄: 68.08 x̃: 36
   HURT stats (rel)   min: 0.03% max: 7.79% x̄: 2.97% x̃: 1.25%
   95% mean confidence interval for cycles value: -182.55 -154.71
   95% mean confidence interval for cycles %-change: -7.84% -6.69%
   Cycles are helped.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18455>
2022-09-08 15:12:41 +00:00
Georg Lehmann 4d7fe94f3a nir/opt_algebraic: Optimize unpacking of upcasts to 64bit integers.
Foz-DB Navi21:
Totals from 7 (0.01% of 134913) affected shaders:
CodeSize: 213364 -> 213028 (-0.16%)
Instrs: 38347 -> 38319 (-0.07%)
Latency: 780148 -> 779776 (-0.05%)
InvThroughput: 520098 -> 519851 (-0.05%)

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18435>
2022-09-08 14:37:56 +00:00
Tomeu Vizoso 3601c28690 ci: Stop explicitly passing env vars to FDO_DISTRIBUTION_EXEC command
ci-templates will now pass all env vars to the command.

Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18467>
2022-09-08 12:07:19 +00:00
Tomeu Vizoso 7dc8a78001 ci: Install sysvinit-core without --no-remove
As it conflicts now with some packages already installed but not
necessary, such as:

libpam-systemd packagekit packagekit-tools policykit-1 systemd-sysv

Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18467>
2022-09-08 12:07:19 +00:00
Tomeu Vizoso 86e2078be7 ci: Use --no-install-recommends to avoid problems with --no-remove
Some packages that are being installed via recommends are conflicting
with already installed packages, causing this error:

E: Packages need to be removed but remove is disabled.

We dont need these packages, so don't install them.

Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18467>
2022-09-08 12:07:19 +00:00
Tomeu Vizoso 55724c2a5e ci: Uprev ci-templates
Uprev it to:

d5aa3941aa03 ("freebsd: Move from 13.0 to 13.1")

Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18467>
2022-09-08 12:07:19 +00:00
Karmjit Mahil b36e9b6187 pvr: Remove unimplemented push descriptor code.
Push descriptors are part of VK_KHR_push_descriptor.
Not supporting it for now.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18430>
2022-09-08 11:56:43 +00:00
Karol Herbst 54709efd5e nv50: properly flush the TSC cache on 3D
The change didn't make any sense. `s` will always be
`NV50_SHADER_STAGE_COMPUTE`, because it's used to loop over all shader
stages. And the TSC cache on the compute side is already flushed in
`nv50_compute_validate_samplers`.

Fixes spurious `CACHE_ERROR` dmesg messages.

Fixes: ba6ba8c990 ("nv50: adapt texture and constbuf paths for compute shaders")
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: M Henning <drawoc@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18382>
2022-09-08 11:46:51 +00:00
Karol Herbst b23b94fbc9 nv50/ir: fix OP_UNION resolving when used for vector values
When an OP_UNION def takes part in a vector source e.g. for a tex
instruction we failed to clean up the OP_UNION instruction as rep() points
towards the coalesced value instead.

This fixes a regression on nv50 moving to NIR, but also potentially issues
with nvc0.

The main reason this is common in nv50 is, that we lower OP_SLCT to a set,
predicated movs and a union.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6406
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7117
Cc: mesa-stable
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: M Henning <drawoc@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18377>
2022-09-08 11:35:35 +00:00
Frank Binns cbc477d057 pvr: finish render job sample count setup
Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18437>
2022-09-08 11:25:02 +00:00
Thomas H.P. Andersen 1980827aeb util: avoid deprecated builtin has_trivial_destructor
From clang 16 has_trivial_destructor is deprecated.
Use the replacement __is_trivially_destructible if it
is available.

Fixes new warnings with clang 16 like:

../src/compiler/glsl/list.h:58:4: warning: builtin __has_trivial_destructor is deprecated; use __is_trivially_destructible instead [-Wdeprecated-builtins]
../src/util/ralloc.h:551:4: note: expanded from macro 'DECLARE_RZALLOC_CXX_OPERATORS'
   DECLARE_ALLOC_CXX_OPERATORS_TEMPLATE(type, rzalloc_size)
   ^
../src/util/ralloc.h:542:12: note: expanded from macro 'DECLARE_ALLOC_CXX_OPERATORS_TEMPLATE'
      if (!HAS_TRIVIAL_DESTRUCTOR(TYPE))                                 \
           ^
../src/util/macros.h:233:44: note: expanded from macro 'HAS_TRIVIAL_DESTRUCTOR'

Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18423>
2022-09-08 10:53:32 +00:00
Karmjit Mahil 61d265cfce pvr: Finish setting up job resolve info.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18431>
2022-09-08 10:44:57 +00:00
Karmjit Mahil c6113def84 pvr: Set descriptor dirty flag based on other flags.
Set the flag if the descriptor set is updated.
Set the fragment descriptor dirty flag if blend consts are updated.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18429>
2022-09-08 10:36:27 +00:00
Mark Collins dd19da31f2 tu: Expose VK_EXT_tooling_info using common implementation
Signed-off-by: Mark Collins <mark@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18390>
2022-09-08 08:14:40 +00:00
Mark Collins c82249aa68 tu: Clamp priority in DRM submitqueue creation
The kernel driver has a range of valid priority values that can
be supplied to it, submitting any priority value outside these
bounds will result in `-EINVAL`. To avoid this, the priority
value is now clamped to the range that the kernel supports.

Fixes: 0c6fbfca0c
Signed-off-by: Mark Collins <mark@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18389>
2022-09-08 08:04:10 +00:00
Pavel Ondračka c3f51a5dcf r300: allow presubtract when both ADD sources are negative
Current code doesn't handle this, however it is easy to make it work
by moving the negate to the presubtract source. Minor win in shader-db,
mostly with Unigine shaders.

Shader-db RV530:
total instructions in shared programs: 136382 -> 136236 (-0.11%)
instructions in affected programs: 9911 -> 9765 (-1.47%)
total temps in shared programs: 18939 -> 18942 (0.02%)
temps in affected programs: 37 -> 40 (8.11%)

Reviewed-by: Filip Gawin <filip@gawin.net>
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18289>
2022-09-08 06:53:53 +00:00
Gert Wollny 1d8627deed virgl: Add some formats that the CTS uses
Otherwise running the CTS emits lots of warnings about
these formats missing in the drivers format table.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18462>
2022-09-08 06:38:48 +00:00
Rob Clark bbef3cb9d3 egl: Relax locking
Now that we have the rwlock TerminateLock protecting us against
eglTerminate() yanking the rug from under us, drop the BDL across
calls to driver (or at least the main ones that can potentially
block).

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7039
Signed-off-by: Rob Clark <robdclark@chromium.org>
Acked-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18050>
2022-09-07 21:21:38 -07:00
Rob Clark 5d99e8cc03 egl: Introduce rwlock to protect eglTerminate()
eglTerminate() must be serialized against all other EGL calls.  But in
most cases, other EGL calls do not need to be serialized against each
other.  Which fits rather well with a rwlock.

One would be tempted to simply replace the existing BDL with a rwlock,
but several portability and debuggability limitations of the rwlock
implementation prevent that, as described in the TerminateLock comment
block.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Acked-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18050>
2022-09-07 21:21:34 -07:00
Rob Clark 7ba2784b0a egl: Make RefCount atomic
Once we relax the locking, we will be doing _eglPutFoo() outside of the
big display lock.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Acked-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18050>
2022-09-07 21:21:29 -07:00
Rob Clark f1efe037df egl/dri2: Add display lock
In preperation of relaxing eglapi to not hold a lock across driver
calls, but instead only for protecting it's own state, add our own
lock to protect code paths that need locking or have not been audited
yet.  The blocking calls (ClientWaitSyncKHR) or critical path and/or
blocking (MakeCurrent, SwapBuffers*) are lockless, as they have already
been audited for thread safety.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Acked-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18050>
2022-09-07 21:21:25 -07:00
Rob Clark fc5281286d egl/dri2: Make ref_count atomic
In particular, MakeCurrent can be called on multiple threads in
parallel.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18050>
2022-09-07 21:21:21 -07:00
Rob Clark a2d6dee4f0 egl/wgl: Make ref_count atomic
Looks like wgl doesn't have much display state to protect.  But it's
ref_count should be atomic before we start removing locking from eglapi
to protect against MakeCurrent being called in parallel on multiple
threads.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Acked-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18050>
2022-09-07 21:21:16 -07:00
Timothy Arceri f182b1952a glsl: remove GLSL IR inverse comparison optimisations
As per 7d85dc4f35 GLSL IR is not smart enough to handle this
correctly for NANs.

Shader-db radeonsi (RX 6800):

Totals from affected shaders:
SGPRS: 26848 -> 26848 (0.00 %)
VGPRS: 13552 -> 13552 (0.00 %)
Spilled SGPRs: 134 -> 134 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 635000 -> 630988 (-0.63 %) bytes
Max Waves: 5474 -> 5474 (0.00 %)

Shader-db iris (BDW):

total instructions in shared programs: 17538859 -> 17539018 (<.01%)
instructions in affected programs: 29369 -> 29528 (0.54%)
helped: 3
HURT: 126
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.49% max: 0.49% x̄: 0.49% x̃: 0.49%
HURT stats (abs)   min: 1 max: 2 x̄: 1.29 x̃: 1
HURT stats (rel)   min: 0.27% max: 1.32% x̄: 0.61% x̃: 0.54%
95% mean confidence interval for instructions value: 1.13 1.33
95% mean confidence interval for instructions %-change: 0.54% 0.63%
Instructions are HURT.

total loops in shared programs: 4866 -> 4866 (0.00%)
loops in affected programs: 0 -> 0
helped: 0
HURT: 0

total cycles in shared programs: 858548230 -> 858548915 (<.01%)
cycles in affected programs: 1331737 -> 1332422 (0.05%)
helped: 0
HURT: 92
HURT stats (abs)   min: 2 max: 49 x̄: 7.45 x̃: 6
HURT stats (rel)   min: 0.01% max: 1.90% x̄: 0.12% x̃: 0.05%
95% mean confidence interval for cycles value: 5.72 9.17
95% mean confidence interval for cycles %-change: 0.05% 0.19%
Cycles are HURT.

Note: With the addition of "nir/comparison_pre: See through an inot to
apply the optimization", idr's shader-db results are:

All Broadwell and newer Intel platforms had similar results. (Ice Lake shown)
total instructions in shared programs: 19940805 -> 19940802 (<.01%)
instructions in affected programs: 582 -> 579 (-0.52%)
helped: 3 / HURT: 0

total cycles in shared programs: 858431633 -> 858431747 (<.01%)
cycles in affected programs: 4938 -> 5052 (2.31%)
helped: 0 / HURT: 3

All older Intel platforms had similar results. (Haswell shown)
total instructions in shared programs: 16715626 -> 16715670 (<.01%)
instructions in affected programs: 9496 -> 9540 (0.46%)
helped: 0 / HURT: 44

total cycles in shared programs: 881224396 -> 881232314 (<.01%)
cycles in affected programs: 600610 -> 608528 (1.32%)
helped: 6 / HURT: 44

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18006>
2022-09-08 01:01:14 +00:00
Ian Romanick 5473536798 nir/comparison_pre: See through an inot to apply the optimization
This also prevents some small regressions in "glsl: remove GLSL IR
inverse comparison optimisations".

shader-db results:

All Sandy Bridge and newer Intel platforms had similar results. (Ice Lake shown)
total instructions in shared programs: 19941025 -> 19940805 (<.01%)
instructions in affected programs: 52431 -> 52211 (-0.42%)
helped: 188 / HURT: 6

total cycles in shared programs: 858451784 -> 858431633 (<.01%)
cycles in affected programs: 2119134 -> 2098983 (-0.95%)
helped: 183 / HURT: 12

LOST:   2
GAINED: 0

Iron Lake and GM45 had similar results. (Iron Lake shown)
total instructions in shared programs: 8364668 -> 8364670 (<.01%)
instructions in affected programs: 753 -> 755 (0.27%)
helped: 2 / HURT: 4

total cycles in shared programs: 248752572 -> 248752238 (<.01%)
cycles in affected programs: 87290 -> 86956 (-0.38%)
helped: 2 / HURT: 4

fossil-db results:

Skylake, Ice Lake, and Tiger Lake had similar results. (Ice Lake shown)
Instructions in all programs: 144909184 -> 144909130 (-0.0%)
Instructions helped: 6

Cycles in all programs: 9138641740 -> 9138640984 (-0.0%)
Cycles helped: 8

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18006>
2022-09-08 01:01:14 +00:00
Timothy Arceri 61c3438b27 nir: support loop unrolling with inot conditions
Ever since 4246c2869c and 7d85dc4f35 loop unrolling can no
longer depend on inot being eliminated from the loop
terminator condition so we need to be able to handle it.

This change avoids 292 loop unrolling regressions with shader-db
once the following patch is applied.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18006>
2022-09-08 01:01:14 +00:00
Timothy Arceri 96c19d23c9 nir: update nir_is_supported_terminator_condition()
Ever since 4246c2869c and 7d85dc4f35 loop unrolling can no
longer depend on inot being eliminated from the loop
terminator condition so we need to be able to handle it.

Here we simply check to see if the inot contains a simple
terminator condition we previously handled. We also update
the previous users of this function to use a newly name
copy of the previous behaviour
nir_is_terminator_condition_with_two_inputs().

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18006>
2022-09-08 01:01:14 +00:00
Bas Nieuwenhuizen ae7532e0cc amd/common: Disable DCC retile modifiers on RDNA1
Some claims of corruption, modifier-less Mesa already doesn't do
it. Since these modifiers have no purpose besides being displayed
lets just disable in Mesa.

Cc: mesa-stable

Tested-by: Michel Dänzer <mdaenzer@redhat.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18140>
2022-09-07 23:41:28 +00:00
Bas Nieuwenhuizen af4b656817 amd/common: Don't rely on DCN support checks with modifiers.
Going to be a bad time if they disagree, which is bound to happen
sometimes. Not asserting and stuff tends to be a better experience
than crashing.

Cc: mesa-stable

Tested-by: Michel Dänzer <mdaenzer@redhat.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18140>
2022-09-07 23:41:28 +00:00
Jordan Justen b26980a4d4 intel/pci_ids: Drop non-upstream dg2 pci-ids
These pci-ids should be included in
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14523, since
these pci-ids will only be supported by kernels that support the
forked Linux uapi. (Note that !14523 will never be merged into
upstream Mesa.)

Ref: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/drm/i915_pciids.h?h=v6.0-rc3#n695
Fixes: 398a9be94b ("intel/dev: Enable remaining DG2 and ATS-M device IDs")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18386>
2022-09-07 19:04:05 +00:00
Yiwei Zhang 4ae4e4362c venus: double the abort timeout
To avoid bumping abort timeout too much. This change also doubles the
busy wait cycles, which would further reduce unnecessary sleeps for
synchronous calls. Ultimately, after we fix the fencing and push all
roundtrip waiting to the renderer side as well as we fixing the abort
logic, we can live with busy wait alone here.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18472>
2022-09-07 18:48:07 +00:00
Iván Briano 92ee2e6b64 anv: pipelineStageCreationFeedbackCount is allowed to be 0
Fixes: 6601e5d6fc ("anv: implement VK_EXT_pipeline_creation_feedback")

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18451>
2022-09-07 10:49:29 -07:00
Georg Lehmann 28a69b72d8 aco: Use plain VOPC for vcmpx when possible.
Foz-DB Navi21:
Totals from 66947 (49.62% of 134913) affected shaders:
CodeSize: 210383024 -> 210033376 (-0.17%)

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18417>
2022-09-07 16:08:36 +00:00
Konstantin Seurer 9cbc609db3 radv: Deduplicate push constant structs
This patch adds a header that is shared between the accel struct build
kernels and the dispatch code.

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18376>
2022-09-07 15:45:48 +00:00
Mike Blumenkrantz 69d123d88e zink: fix sharedmem ops with bit_size!=32
* the rewrite_bo_access compiler pass already handles 64bit rewrites as-needed
* sharedmem access is not required to be 32bit

thus, this can use a similar methodology as ssbo/ubo vars to index based on bitsize
and handle operations through sized variables

Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18449>
2022-09-07 15:23:03 +00:00
Corentin Noël 13f36d66ad ci: disable the freedreno farm.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18463>
2022-09-07 13:26:31 +00:00
Eric Engestrom 28ed514c3c v3dv: implement VK_EXT_shader_module_identifier
Passes `dEQP-VK.*.shader_module_identifier.*`

Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18458>
2022-09-07 12:51:16 +00:00
Tomeu Vizoso 0704926a9c Revert "Revert "Revert "ci: set venus on lavapipe to manual due to flakes"""
Now the flakiness might have been fixed for good.

This reverts commit e51c5a18ad.

Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18454>
2022-09-07 09:18:49 +00:00
Tomeu Vizoso 9e19a40e56 ci: Crosvm won't remove the control socket file on stop
When sending the stop command to a lingering Crosvm instance, the socket
file will remain and the next instance will fail to start.

Make sure the file is deleted before starting Crosvm with the same path.

Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18454>
2022-09-07 09:18:49 +00:00
Samuel Pitoiset d6321fee5f radv: only expose sparseResidencyImage3D on GFX9+
It's currently broken on Polaris10 and breaks running VKCTS entirely.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18457>
2022-09-07 08:57:13 +00:00
Martin Roukala (né Peres) daafeb9893 radv/ci: run vkcts on the two steam decks in parallel
We just added a new Steam Deck to our CI, which should allow us to
halve the execution time of a full VKCTS run from 1h20 to a more
reasonable 40 minutes.

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18432>
2022-09-07 08:37:59 +00:00
Samuel Pitoiset 8fcb4aa0eb radv: compact MRTs to save PS export memory space
If there are holes between color outputs (e.g. a shader exports MRT1,
but not MRT0), we can remove the holes by moving higher MRTs lower. The
hardware will remap the MRTs to their correct locations if we remove
holes in SPI_SHADER_COL_FORMAT but not CB_SHADER_MASK. This is good for
performance because the hardware will allocate less space for color
MRTs.

This also allows to remove even more unused color exports because we no
longer need to force previous targets to be non-zero. Only SotTR seems
affected from our fossils db.

fossils-db (NAVI21):
Totals from 859 (0.64% of 134913) affected shaders:
VGPRs: 24328 -> 24216 (-0.46%)
CodeSize: 1433276 -> 1422576 (-0.75%)
Instrs: 255275 -> 253728 (-0.61%)
Latency: 1666836 -> 1661544 (-0.32%)
InvThroughput: 346038 -> 343406 (-0.76%)
Copies: 16520 -> 16506 (-0.08%)
PreSGPRs: 25934 -> 25920 (-0.05%)
PreVGPRs: 19903 -> 19662 (-1.21%)

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5786>
2022-09-07 08:17:20 +00:00
Samuel Pitoiset 49c7d28b0b radv: gather MRTs that are written by the fragment shader
This will be used to filter color attachments without exports.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5786>
2022-09-07 08:17:20 +00:00
Erik Faye-Lund 6e990a2f73 docs/zink: remove bptc from required formats for gl4.2
We now have lowering-code in the mesa state-tracker, meaning we no
longer need this feature.

Fixes: e4ff42684b ("mesa/st: enable bptc extension with fallback")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18434>
2022-09-07 08:11:31 +00:00