Commit Graph

87296 Commits

Author SHA1 Message Date
Tim Rowley 75149088be swr: [rasterizer core/memory] StoreTile: AVX512 progress
Fixes to 128-bit formats.

Reviwed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-12-12 17:52:39 -06:00
Matt Turner ac6646129f nir: Move fsat outside of fmin/fmax if second arg is 0 to 1.
instructions in affected programs: 550 -> 544 (-1.09%)
helped: 6

cycles in affected programs: 6952 -> 6850 (-1.47%)
helped: 6

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-12-12 12:39:27 -08:00
Matt Turner 7bed52bb5f i965/fs: Reject copy propagation into SEL if not min/max.
We shouldn't ever see a SEL with conditional mod other than GE (for max)
or L (for min), but we might see one with predication and no conditional
mod.

total instructions in shared programs: 8241806 -> 8241902 (0.00%)
instructions in affected programs: 13284 -> 13380 (0.72%)
HURT: 62

total cycles in shared programs: 84165104 -> 84166244 (0.00%)
cycles in affected programs: 75364 -> 76504 (1.51%)
helped: 10
HURT: 34

Fixes generated code in at least Sanctum 2, Borderlands 2, Goat
Simulator, XCOM: Enemy Unknown, and Shogun 2.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92234
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-12-12 12:38:55 -08:00
Matt Turner 091a8a04ad i965/fs: Add unit tests for copy propagation pass.
Pretty basic, but it's a start.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2016-12-12 12:38:50 -08:00
Matt Turner 6014da50ec i965/fs: Rename opt_copy_propagate -> opt_copy_propagation.
Matches the vec4 backend, cmod propagation, and saturate propagation.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-12-12 12:38:43 -08:00
Nicolai Hähnle ec0a0a60cc radeonsi: shrink the GSVS ring to account for the reduced item sizes
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-12-12 09:05:17 +01:00
Nicolai Hähnle 6fdef7d265 radeonsi: shrink each vertex stream to the actually required size
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-12-12 09:05:13 +01:00
Nicolai Hähnle 2f2e941e2d radeonsi: use a single descriptor for the GSVS ring
We can hardcode all of the fields for swizzling in the geometry shader.

The advantage is that we use fewer descriptor slots and we no longer have to
update any of the (ring) descriptors when the geometry shader changes.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-12-12 09:05:05 +01:00
Nicolai Hähnle 18616e7551 radeonsi: pack GS output components for each vertex stream contiguously
Note that the memory layout of one vertex stream inside one "item" (= memory
written by one GS wave) on the GSVS ring is:

  t0v0c0 ... t15v0c0 t0v1c0 ... t15v1c0 ... t0vLc0 ... t15vLc0
  t0v0c1 ... t15v0c1 t0v1c1 ... t15v1c1 ... t0vLc1 ... t15vLc1
                        ...
  t0v0cL ... t15v0cL t0v1cL ... t15v1cL ... t0vLcL ... t15vLcL
  t16v0c0 ... t31v0c0 t16v1c0 ... t31v1c0 ... t16vLc0 ... t31vLc0
  t16v0c1 ... t31v0c1 t16v1c1 ... t31v1c1 ... t16vLc1 ... t31vLc1
                        ...
  t16v0cL ... t31v0cL t16v1cL ... t31v1cL ... t16vLcL ... t31vLcL

                        ...

  t48v0c0 ... t63v0c0 t48v1c0 ... t63v1c0 ... t48vLc0 ... t63vLc0
  t48v0c1 ... t63v0c1 t48v1c1 ... t63v1c1 ... t48vLc1 ... t63vLc1
                        ...
  t48v0cL ... t63v0cL t48v1cL ... t63v1cL ... t48vLcL ... t63vLcL

where tNN indicates the thread number, vNN the vertex number (in the order of
EMIT_VERTEX), and cNN the output component (vL and cL are the last vertex and
component, respectively).

The vertex streams are laid out sequentially.

The swizzling by 16 threads is hard-coded in the way the VGT generates the
offset passed into the GS copy shader, and the jump every 16 threads is
calculated from VGT_GSVS_RING_OFFSET_n and VGT_GSVS_RING_ITEMSIZE in a way
that makes it difficult to deviate from this layout (at least that's what
I've experimentally confirmed on VI after first trying to go the simpler
route of just interleaving the vertex streams).

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-12-12 09:05:00 +01:00
Nicolai Hähnle edf034ac14 radeonsi: do not write non-existent components through the GSVS ring
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-12-12 09:04:58 +01:00
Nicolai Hähnle af976f12a5 radeonsi: only write values belonging to the stream when emitting GS vertex
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-12-12 09:04:54 +01:00
Nicolai Hähnle bdf1bf1cb5 radeonsi: generate an explicit switch instruction over vertex streams
SimplifyCFG generates a switch instruction anyway when all four streams
are present, but is simultaneously not smart enough to eliminate some
redundant jumps that it generates.

The generated assembly is still a bit silly, probably because the
control flow annotation doesn't know how to handle a switch with uniform
condition.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-12-12 09:04:49 +01:00
Nicolai Hähnle bae929f96e radeonsi: fetch only outputs of current vertex stream from the GSVS ring
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-12-12 09:04:46 +01:00
Nicolai Hähnle dfb69cac33 radeonsi: only export from GS copy shader for vertex stream 0
When running the copy shader for vertex streams != 0, the SX does not need
any data from us (there is no rasterization for the higher vertex streams,
only streamout).

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-12-12 09:04:43 +01:00
Nicolai Hähnle 21f2bb22a3 radeonsi: do not export VS outputs from vertex streams != 0
This affects for GS copy shaders. When an output is meant for vertex
stream != 0, then we don't have to make it available to the pixel
shader.

There is a minor inefficiency here because the GLSL varying packing pass
does not group varyings of the same vertex stream together, but it
shouldn't be important in practice.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-12-12 09:04:36 +01:00
Nicolai Hähnle fc0e009aa7 radeonsi: pull iteration over vertex streams into GS copy shader logic
The iteration is not needed for normal vertex shaders.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-12-12 09:04:33 +01:00
Nicolai Hähnle 180ae18ec5 radeonsi: group streamout writes by vertex stream
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-12-12 09:04:30 +01:00
Nicolai Hähnle d89592836a radeonsi: load the streamout buf descriptors closer to their use
LLVM can still decide to hoist the loads since they're marked invariant.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-12-12 09:04:27 +01:00
Nicolai Hähnle 564f17f0d7 radeonsi: extract writing of a single streamout output
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-12-12 09:04:24 +01:00
Nicolai Hähnle b41dd00235 radeonsi: separate the call to si_llvm_emit_streamout from exports
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-12-12 09:04:22 +01:00
Nicolai Hähnle 5ad6e56ca3 radeonsi: plumb the output vertex_stream through to si_shader_output_values
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-12-12 09:04:19 +01:00
Nicolai Hähnle 2985708fa0 radeonsi: rename members of si_shader_output_values
Be a bit more verbose and avoid confusion in future patches.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-12-12 09:04:16 +01:00
Nicolai Hähnle 88509518b0 radeonsi: fix an off-by-one error in the bounds check for max_vertices
The spec actually says that calling EmitStreamVertex is undefined when
you exceed max_vertices. But we do need to avoid trampling over memory
outside the GSVS ring.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-12-12 09:04:13 +01:00
Nicolai Hähnle 7655bccce8 radeonsi: do not kill GS with memory writes
Vertex emits beyond the specified maximum number of vertices are supposed to
have no effect, which is why we used to always kill GS that reached the limit.

However, if the GS also writes to memory (SSBO, atomics, shader images), then
we must keep going and only skip the vertex emit itself.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-12-12 09:04:10 +01:00
Nicolai Hähnle 7b5b3d63c5 radeonsi: update all GSVS ring descriptors for new buffer allocations
Fixes GL45-CTS.gtf40.GL3Tests.transform_feedback3.transform_feedback3_geometry_instanced.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-12-12 09:04:06 +01:00
Nicolai Hähnle 2eaacba7f2 st/glsl_to_tgsi: plumb the GS output stream qualifier through to TGSI
Allow drivers to emit GS outputs in a smarter way.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-12-12 09:04:03 +01:00
Nicolai Hähnle cc34a6f0bd tgsi/scan: collect information about output usagemasks
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-12-12 09:04:01 +01:00
Nicolai Hähnle cf8e9778fc tgsi/scan: collect information about output vertex streams
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-12-12 09:03:57 +01:00
Nicolai Hähnle 81d0dc5e55 gallium: extract individual streamout output structure
So that we can pass pointers to individual array entries around.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-12-12 09:03:54 +01:00
Nicolai Hähnle 04811354c8 tgsi: add Stream{X,Y,Z,W} fields to tgsi_declaration_semantic
This is for geometry shader outputs. Without it, drivers have no way of
knowing which stream each output is intended for, and have to
conservatively write all outputs to all streams.

Separate stream numbers for each component are required due to output
packing.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-12-12 09:03:51 +01:00
Nicolai Hähnle 173d80b401 glsl: remember per-component vertex streams for packed varyings
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-12-12 09:03:47 +01:00
Grazvydas Ignotas 6092169b96 i965/blorp: fix release build unused variable warning
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
2016-12-12 07:09:33 +01:00
Edward O'Callaghan 5e6b2b05a5 virgl: Fix a strict-aliasing violation in the encoder
As per the C spec, it is illegal to alias pointers to different
types. This results in undefined behaviour after optimization
passes, resulting in very subtle bugs that happen only on a
full moon..

Use a memcpy() as a well defined coercion between the double
to uint64_t interpretations of the memory.

V.2: Use static_assert() instead of assert().
V.3: Use C99 compat STATIC_ASSERT() over C11 static_assert().

Signed-off-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Acked-by: Dave Airlie <airlied@redhat.com>
2016-12-12 16:50:15 +11:00
Kenneth Graunke 35c5a9a64d i965: Print out cycle estimates at the start of block annotations.
We now print

   START B15 <-B14 (42774 cycles)

indicating that we estimate B15 will take 42,774 cycles.  Printing
this should make it easier where time is spent in the program.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-12-11 16:33:05 -08:00
Kenneth Graunke 713cd23d8e mesa: Return LINEAR encoding for winsys FBO depth/stencil.
GetFramebufferAttachmentParameteriv should return GL_LINEAR for the
window system default framebuffer's GL_DEPTH or GL_STENCIL attachments
when there are zero depth or stencil bits.

The GL 4.5 spec's GetFramebufferAttachmentParameteriv section says:

"If the value of FRAMEBUFFER_ATTACHMENT_OBJECT_TYPE is not NONE,
 these queries apply to all other framebuffer types:

 [...]

 If attachment is not a color attachment, or no data storage or texture
 image has been specified for the attachment, then params will contain
 the value LINEAR."

Note that we already return LINEAR for the case where there is an actual
depth or stencil renderbuffer attached.  In the case modified by this
patch, FRAMEBUFFER_ATTACHMENT_OBJECT_TYPE returns FRAMEBUFFER_DEFAULT
rather than NONE.

Fixes a CTS test when run in a visual without depth / stencil buffers:
GL45-CTS.gtf30.GL3Tests.framebuffer_srgb.framebuffer_srgb_default_encoding

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2016-12-11 16:33:05 -08:00
Grazvydas Ignotas b58d1eecc6 intel/aubinator: fix 32bit shift overflow warning
Doesn't look like this can work on 32bit, just rids of annoying
warning.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
2016-12-11 20:04:15 +01:00
Grazvydas Ignotas 3a1b15c392 anv: fix release build unused variable warnings
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
2016-12-11 20:03:14 +01:00
Grazvydas Ignotas 90c29784c6 radv/ac: some fix maybe-uninitialized warnings
Mark some paths unreachable so that compiler knows variables are
initialized in all valid paths.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2016-12-10 21:46:56 +01:00
Grazvydas Ignotas ec08666a28 radv/meta: use VK_NULL_HANDLE for handles
Otherwise we get 32bit warnings because handle is plain uint64_t there
and NULL is not suited to initialize that.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2016-12-10 21:46:56 +01:00
Grazvydas Ignotas 9bff2c9884 radv: fix release build unused variable warnings
Just mark with MAYBE_UNUSED.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2016-12-10 21:46:56 +01:00
Grazvydas Ignotas 15e12ab8fc softpipe: fix release build unused variable warning
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2016-12-10 21:25:45 +01:00
Grazvydas Ignotas c81a89f662 radeonsi: fix release build unused variable warnings
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2016-12-10 21:19:59 +01:00
Chad Versace 42011be1e2 i965/mt: Disable HiZ when sharing depth buffer externally (v2)
intel_miptree_make_shareable() discarded and disabled CCS. Fix it so
that it discards and disables HiZ too.

Fixes dEQP-EGL.functional.image.render_multiple_contexts.gles2_renderbuffer_depth16_depth_buffer
on Skylake.

v2: Actually do what the commit message says. Discard the HiZ buffer.

Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=98329
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: Nanley Chery <nanley.g.chery@intel.com
Cc: Haixia Shi <hshi@chromium.org>
Cc: mesa-stable@lists.freedesktop.org
2016-12-10 08:05:11 -08:00
Chad Versace 1c8be049be i965/mt: Disable aux surfaces after making miptree shareable
The entire goal of intel_miptree_make_shareable() is to permanently
disable the miptree's aux surfaces. So set
intel_mipmap_tree:disable_aux_buffers after the function's done with
discarding down the aux surfaces.

References: https://bugs.freedesktop.org/show_bug.cgi?id=98329
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: Nanley Chery <nanley.g.chery@intel.com
Cc: Haixia Shi <hshi@chromium.org>
Cc: mesa-stable@lists.freedesktop.org
2016-12-10 08:05:11 -08:00
Jason Ekstrand da1c49171d spirv: Use a simpler and more correct implementaiton of tanh()
The new implementation is more correct because it clamps the incoming value
to 10 to avoid floating-point overflow.  It also uses a much reduced
version of the formula which only requires 1 exp() rather than 2.  This
fixes all of the dEQP-VK.glsl.builtin.precision.tanh.* tests.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "13.0" <mesa-dev@lists.freedesktop.org>
2016-12-09 18:38:21 -08:00
Jason Ekstrand 9807f502eb glsl: Use a simpler formula for tanh
The formula we have used in the past is a trivial reduction from the
definition by simply multiplying both the numerator and denominator of the
formula by 2.  However, multiplying by e^x, you can further reduce it.
This allows us to get rid of one side of the clamp and two of exponential
functions which should make it faster.  The new formula still passes the
dEQP precision tests for tanh so it should be fine.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-12-09 18:38:21 -08:00
Edward O'Callaghan efe9d1cde3 anv: Clean up some unused variables
Following on from the spirit of commit 011e5570f.

Signed-off-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-12-10 11:59:59 +11:00
Tim Rowley 2a127b780b swr: [rasterizer common/core/jitter] fetch support for GL_FIXED
v2: use fmul(1/65536) instead of fdiv(65535)

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-12-09 16:20:13 -06:00
Emil Velikov d0d21532f9 configure: cleanup GLX_USE_TLS handling
Mesa requires ax_pthread_ok = yes, thus we can fold/rewrite the
conditional to follow the more common "if test" pattern.

No functional change intended.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2016-12-09 19:22:03 +00:00
Emil Velikov b83153e77b configure: enable glx-tls by default
In the (not too) distant future we'd want to remove this option and
effectively drop the other codepath(s) we have in our dispatch.

Linux distributions have been using --enable-glx-tls for a number of
years. Some/most BSD platforms still don't support this, yet this should
serve as an encouragement to move things forwards.

Note: we had many bug reports were opened due to the wrong default
option. See the list below for details.

v2:
 - Correct default option in help string (Andreas)
 - Add bugzilla references.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70623
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=72902
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=73778
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89043

Cc: Jean-Sébastien Pédron <dumbbell@FreeBSD.org>
Cc: Jonathan Gray <jsg@jsg.id.au>
Cc: mesa-maintainers@lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Andreas Boll <andreas.boll.dev@gmail.com>
2016-12-09 19:21:41 +00:00