Commit Graph

146112 Commits

Author SHA1 Message Date
Emma Anholt 613b9c8c47 ci: Update deqp to vulkan-cts-1.2.7.1.
Brings in some VK fixes for tilers.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13253>
2021-10-13 00:37:59 +00:00
Jason Ekstrand a00f4c6f7d vulkan/wsi/display: Delete the wrapper entrypoints
Acked-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>
2021-10-13 00:06:15 +00:00
Jason Ekstrand 8abeecf505 vulkan/wsi/wayland: Delete the wrapper entrypoints
Acked-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>
2021-10-13 00:06:15 +00:00
Jason Ekstrand 8ade418144 vulkan/wsi/x11: Delete the wrapper entrypoints
Acked-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>
2021-10-13 00:06:15 +00:00
Jason Ekstrand 1680cd907d vulkan/wsi/common: Delete the wrapper entrypoints
Acked-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>
2021-10-13 00:06:15 +00:00
Jason Ekstrand 1f2ef68bab venus: Use the common WSI wrappers
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>
2021-10-13 00:06:15 +00:00
Jason Ekstrand 8c4d78c764 lavapipe: Use the common WSI wrappers
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>
2021-10-13 00:06:15 +00:00
Jason Ekstrand 1f06554df7 panvk: Use the common WSI wrappers
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>
2021-10-13 00:06:15 +00:00
Jason Ekstrand dfed852ddf v3dv: Use the common WSI wrappers
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>
2021-10-13 00:06:15 +00:00
Jason Ekstrand 531437d7f6 turnip: Use the common WSI wrappers
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>
2021-10-13 00:06:15 +00:00
Jason Ekstrand fbfd761461 radv: Use the common WSI wrappers
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>
2021-10-13 00:06:15 +00:00
Jason Ekstrand a64d90026b anv: Use the common WSI wrappers
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>
2021-10-13 00:06:15 +00:00
Jason Ekstrand 75955c6685 vulkan/wsi: Add common wrappers for most entrypoints
For a long time, our Vulkan WSI code has acted as something of a layer.
The WSI code calls into various Vulkan entrypoints inside the driver to
create images, allocate memory, etc.  It then implements the API-facing
interface almost entirely.  The only thing the driver has to provide is
little wrappers that wrap around the WSI calls to expose them through
the API.

However, now that we have a common dispatch framework, we can implement
entrypoints directly in the WSI code.  As long as the driver uses
vk_instance, vk_physical_device, and vk_device, we can provide common
wrappers for the vast majority of entrypoints.  The only exceptions are
vkAcquireNextImage, vkQueuePresent, vkRegisterDeviceEventEXT, and
vkRegisterDisplayEventEXT because those may have to manually poke at
synchronization primitives.  We provide wrappers for vkAcquireNextImage
and vkQueuePresent because some drivers can use the default versions.

For now, we're intentionally avoiding any link-time dependencies between
WSI and the common code.  We only use VK_FROM_HANDLE and associated
inline helpers and vk_physical_device has a pointer to a wsi_device.
Eventually, we may tie the two together closer, but this lets us get 95%
of the way there without reworking the universe.

Acked-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>
2021-10-13 00:06:15 +00:00
Jason Ekstrand 020fbb9ea1 vulkan/wsi: Add a dispatch table for WSI entrypoints
Acked-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>
2021-10-13 00:06:15 +00:00
Jason Ekstrand 916c9335b4 meson: Add and use an idep for Vulkan WSI
Acked-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>
2021-10-13 00:06:15 +00:00
Ella-0 17dcdb000a v3dv: enable VK_KHR_surface_protected_capabilities
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13298>
2021-10-12 22:12:46 +00:00
Eric Engestrom 9aee7855d2 egl: implement EGL_EXT_present_opaque on wayland
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: James Jones <jajones@nvidia.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12373>
2021-10-12 21:40:54 +00:00
Eric Engestrom fe46280748 egl: sync eglext.h & egl.xml from Khronos
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Simon Ser <contact@emersion.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12373>
2021-10-12 21:40:54 +00:00
Emma Anholt d071a241f4 ci/freedreno: Disable the minetest trace due to flaky shader code.
Fixes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4595
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13316>
2021-10-12 20:50:17 +00:00
Nanley Chery d7e836443a iris: Tile cache flush for depth before fast clear
Instead of doing a tile cache flush after slow clears or when the clear
value changes, do it before every fast clear of a HIZ_CCS_WT surface.
This agrees with the Bspec.

Fixes: c85ea824bc ("iris: reduce redundant tile cache flushes")
Reviewed-by: Felix DeGrood <felix.j.degrood@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11539>
2021-10-12 18:05:46 +00:00
Nanley Chery 10be870c72 anv: Tile cache flush for depth before fast clear
Instead of doing a tile cache flush after slow clears, resolves, and
ambiguates, do it before fast clears of HIZ_CCS_WT surfaces. This agrees
with the Bspec.

Reviewed-by: Felix DeGrood <felix.j.degrood@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11539>
2021-10-12 18:05:46 +00:00
Nanley Chery 81e9c25c1b anv: Allow HIZ_CCS_WT with subpass self-dependencies
This unblocks later commits that aim to align the driver with the tile
cache flushing requirements in the Bspec.

Reviewed-by: Felix DeGrood <felix.j.degrood@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11539>
2021-10-12 18:05:46 +00:00
Danylo Piliaiev 4218596671 ir3/freedreno: handle non-uniform a1en instructions
Fixes vkd3d test "test_bindless_samplers_sm51"

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13311>
2021-10-12 17:43:52 +00:00
Danylo Piliaiev f0d469e85f ir3/freedreno: handle non-uniform resinfo
We forgot to handle non-uniform resinfo case.

Fixes vkd3d test "test_bindless_bufinfo_sm51"

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13311>
2021-10-12 17:43:52 +00:00
Timur Kristóf ca6ef505ff aco/optimizer: Skip SDWA on v_lshlrev when unnecessary in apply_extract.
In the following cases:
- lower 16 bits are extracted and the shift amount is 16 or more
- lower 8 bits are extracted and the shift amount is 24 or more
the undesireable upper bits are already shifted out, and therefore
there is no need to add SDWA to the v_lshlrev instruction.

Fossil DB stats on Sienna Cichlid with NGGC on:

Totals from 58239 (45.27% of 128647) affected shaders:
CodeSize: 153498624 -> 153265616 (-0.15%); split: -0.15%, +0.00%
Instrs: 29636304 -> 29578064 (-0.20%); split: -0.20%, +0.00%
Latency: 136931496 -> 136876379 (-0.04%); split: -0.04%, +0.00%
InvThroughput: 21134367 -> 21078861 (-0.26%); split: -0.26%, +0.00%
Copies: 2777550 -> 2777548 (-0.00%); split: -0.00%, +0.00%

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13121>
2021-10-12 16:27:50 +00:00
Timur Kristóf 5de91cfc04 ac/nir/nggc: Write undef to variables in non-repacked ES threads.
This helps the compiler generate a little bit more efficient code.

Fossil DB stats on Sienna Cichlid with NGGC on:

Totals from 4659 (3.62% of 128647) affected shaders:
CodeSize: 7468320 -> 7404484 (-0.85%); split: -0.88%, +0.03%
Instrs: 1423425 -> 1407454 (-1.12%); split: -1.16%, +0.03%
Latency: 5250593 -> 5226163 (-0.47%); split: -0.47%, +0.00%
InvThroughput: 739848 -> 733373 (-0.88%); split: -0.90%, +0.02%
Copies: 200139 -> 190307 (-4.91%); split: -5.13%, +0.22%
Branches: 87925 -> 85998 (-2.19%)

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13121>
2021-10-12 16:27:50 +00:00
Timur Kristóf 783f8f728c ac/nir/cull: Accept NaN and +/- Inf in face culling.
When the determinant that we use for calculating triangle area
is NaN, it's not possible to decide the facing of the triangle.

This can happen when a coordinate of one of the triangle's vertices
is INFINITY. It's better to just accept these triangles in the shader
and let the PA deal with them.

Let's do the same for +/- Infinity too.
Though we haven't seen this yet, it may be troublesome as well.

Fixes: 651a3da1b5
Closes: #5470
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13299>
2021-10-12 15:23:52 +00:00
Bas Nieuwenhuizen 33065149c1 amd/common: Add fallback for misreported clocks for RGP.
Traces with clock = 0 are totally useless due to RGP getting very
confused.

Cc: mesa-stable
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13301>
2021-10-12 12:28:04 +00:00
Connor Abbott f8e9a50322 ir3: Fold ldc src immediates
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>
2021-10-12 11:30:52 +00:00
Connor Abbott 470bf75ff8 ir3: Fix handling cat6 immediates
We were treating them the same as regular cat2/cat3/cat4 immediates, but
that's not right because cat6 sources are only 8 bits.

Our bindless code was handling this before for bindless resources, and
it was disabled for most other things, so this was mostly harmless, but
fixing it will be necessary for handling ldc offsets.

In addition enable tests for this that were just commented out, and add
a custom test making sure that the immediate source is treated as
unsigned.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>
2021-10-12 11:30:52 +00:00
Connor Abbott bf3c8e3705 ir3: Fix check for immediate range
This would incorrectly allow both e.g. 0x2000 and 0xffffe000 to be
encoded as 0x2000.

Fixes: f0a1f3de27 ("freedreno/ir3: cp small negative integers too")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>
2021-10-12 11:30:52 +00:00
Connor Abbott 6dc56f18bc ir3/legalize: handle WAR for special regs
In particular many cat5/cat6 instructions read a1.x, and we need to add
a (ss) before any mova1 instruction afterwards, as the blob does.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>
2021-10-12 11:30:52 +00:00
Connor Abbott 1ed9a2f50c ir3: Handle special regs in regmask
Use the same hack as post-RA scheduling.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>
2021-10-12 11:30:52 +00:00
Connor Abbott a37f9602b7 ir3: Remove separate regmask.h
Inline it into its one user. There's no point in keeping it separate,
and in order to handle special registers it will have to become a bit
more intertwined with core ir3.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>
2021-10-12 11:30:52 +00:00
Connor Abbott 548377bcf3 ir3: Always create barycentrics in the input block
Otherwise, when there are uses in multiple blocks the collect may not
dominate some of the uses.

This is a bugfix, but before it would've mattered only in weird
scenarios with interpolateAt*. When we start moving prefetch textures
into the block before the preamble it will start to matter more, because
it will need to read the barycentrics from a different block than the
bary.f instructions.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>
2021-10-12 11:30:52 +00:00
Connor Abbott 38a84723f1 ir3: Make ir3_create_collect() take a block
There's no reason to make this any different from the other builders,
since it just creates a collect instruction, and in the next commit
we'll need to create a collect in the first block for prefetch textures.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>
2021-10-12 11:30:52 +00:00
Connor Abbott 8fb99b58df ir3: Fix printing branch type
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>
2021-10-12 11:30:52 +00:00
Connor Abbott b516208a55 nir/lower_ubo_vec4: Fix align_mul=8 special case
In order for the load to never straddle the load can't extend past 8
bytes, not 16. For example a vec2 load with align_mul = 8 and
align_offset = 4 can straddle.

Fixes assertion failures when we stop pushing UBOs in the preamble on
a6xx.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>
2021-10-12 11:30:52 +00:00
Connor Abbott 751f425c37 ir3/cp: Fix inlining 32->16 const into meta instructions
We shouldn't return early here, because we still need to actually do the
conversion. Fixes an infinite loop.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>
2021-10-12 11:30:52 +00:00
Connor Abbott ab0a665615 ir3/cp: Add missing const promotion check
We need to check the source type for moves when the destination type is
u16, just like the f16 check above.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>
2021-10-12 11:30:52 +00:00
Joshua Ashton 1d9bd8b262 radv: Do early and late tests for fast clears
We don't know some information regarding DCC image stores and therefore fast clears until we know the surface info.

We should work towards eliminating this, but the cases where this will hit on GFX10_3 is basically 0.

Finally fixes a perf regression in Doom Eternal.

Signed-off-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13283>
2021-10-12 10:59:32 +00:00
Samuel Pitoiset 49c3a88fad radv: implement VK_KHR_format_feature_flags2
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13194>
2021-10-12 10:20:47 +00:00
Samuel Pitoiset 5dee0d9da9 radv: switch to VK_FORMAT_FEATURE_2_XXX/VkFormatProperties3KHR
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13194>
2021-10-12 10:20:47 +00:00
Samuel Pitoiset cd4a52b52c radv: remove duplicated code about NGG passthrough determination
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13243>
2021-10-12 09:09:26 +02:00
Samuel Pitoiset 6bfe65d1dc radv: do not initialize is_ngg_passthrough for geometry shaders
Geometry shaders can't be NGG passthrough at all.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13243>
2021-10-12 09:09:25 +02:00
Samuel Pitoiset b3269444fd aco: cleanup setup_vs_output_info()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13243>
2021-10-12 09:09:23 +02:00
Samuel Pitoiset 849832bc89 radv: stop gathering output GS info for vertex shaders
This has no effect.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13243>
2021-10-12 09:09:21 +02:00
Samuel Pitoiset 595b16013a radv: rename needs_multiview_view_index to uses_view_index
To avoid confusion with radv_pipeline_key::has_multiview_view_index.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13243>
2021-10-12 09:09:19 +02:00
Samuel Pitoiset 960d7bf2d3 radv: remove no-op about the view index in the shader info pass
The view index is always lowered to map the layer ID for fragment
shaders. This was never reached.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13243>
2021-10-12 09:09:17 +02:00
Samuel Pitoiset 61a3e75242 radv,aco: remove nir_intrinsic_load_layer_id
This was never used because the layer ID isn't a system value.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13243>
2021-10-12 09:09:15 +02:00