Move to pass by value since most events are very small in size.
We can look at pass by reference but will need to create multiple
versions to handle temp objects.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Added events for tracking early/late Depth and stencil events,
TE patch info, GS prim info, and FrontEnd/BackEnd DrawEnd events.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
- Do proper culling of wireframe triangles (including non-culling of
degenerates)
- Fix degenerate culling of CCW front-facing triangles in wireframe and
conservative rast
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Alpha from render target 0 should always be used for alpha test for all
render targets, according to GL and DX9 specs. Previously we were using
alpha from the current render target.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Buffer events ourselves and then when that's full or we're destroying
the context then write the contents to file. Previously, we're relying
ofstream to buffer for us.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
* All format combinations coded
* Fully emulated on AVX2 and AVX
* Known issue: the MSAA sample locations need to be adjusted for 8x2
Set ENABLE_AVX512_SIMD16 and USD_8x2_TILE_BACKEND to 1 in knobs.h to enable
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
We don't allow the last thread switch to be inside control flow, to be
sure that we hit the last state exactly once. If the last texturing was
in control flow, fall back to single threaded.
We have two major requirements: Make sure that only the bottom half of the
physical reg space is used, and make sure that none of our values are live
in an accumulator across a switch.
We have had no reason to separate ability to store in an accumulator from
ability to store in B, but with FS threading, we need to be able to force
values to be stored only in the physical regfiles.
This will eventually be generated at the QIR level, so that
vc4_qir_schedule.c can arrange the separation of tex_strb from tex_result
correctly. It will also be important so that register allocation set the
register classes appropriately for values that are live across the switch.
Fixes fallout from acc23b04 ("ralloc: remove memset from ralloc_size").
We were still depending on zero'd allocations in a couple of places.
Signed-off-by: Rob Clark <robdclark@gmail.com>
This adds some performance counters/metrics for SM50/SM52.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Pierre Moreau <pierre.morrow@free.fr>
I'm leaving num_out_sgpr around since it's not in a fast path, and besides
the compiler should be able to optimize it away easily. The alternative
with #if/#endif would be extremely ugly.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
The fix in commit 88f791db75 was insufficient
for radeonsi because the vector case was not handled properly. It seems
piglit only covers the scalar case, unfortunately.
Fixes GL45-CTS.shader_bitfield_operation.[iu]mulExtended.*
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
This setting is for whether color and alpha have different blend
settings, not for whether blending is enabled on a per-RT basis.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
With ARB_clip_control, GL may also do 0..1 depth clipping, not just
-1..1. This removes clip's reliance on driver type. DX users will need
to be updated to set the new clipHalfZ flag to get proper clipping
functionality.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
Most logic op usage is probably going to end up with normalized
textures. Scale the floating point values and convert to integer before
performing the logic operations.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
Jonas Pfeil noticed that we were putting passthrough tlb_z writes early in
the shader, despite QIR and QPU scheduling both trying to delay scoreboard
locking for as long as possible.
The problem was that when trying to pair up QPU instructions, at some
point the passthrough tlb_z would be the last one available and it would
get paired, even if the other half would open up other instructions to be
scheduled and we could have paired tlb_z with something later in the
program. Also, since passthrough z is just a mov, it pairs up really
easily.
The proper fix would probably be to flip the order of scheduling
instructions so we went from bottom to top (also relevant for branch delay
slot scheduling).
However, we can do a quick fix here to just not schedule a TLB lock until
there's nothing but TLB left in the program, at a slight instruction cost
(est .61% cycle count in shader-db) but a major fragment shader
parallelism win.
glmark2 results:
texture:texture-filter=linear: +1.24481% +/- 0.626117% (n=15)
bump:bump-render=height: 1.24991% +/- 0.154793% (n=136,133 -- screensaver
outliers removed)
It's much better to just skip the draw call entirely. Getting this
information out of register allocation will also be useful for
implementing threaded fragment shaders, which will need to retry
non-threaded if RA fails.
Cc: <mesa-stable@lists.freedesktop.org>
Applies on top of v3 of Tom's gallivm change.
v2:
- Tom Stellard: Use enums instread of strings.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>
CC: Tom Stellard <thomas.stellard@amd.com>
CC: Jan Vesely <jan.vesely@rutgers.edu>
Vedran Miletić
Tim Rowley
Jonas Pfeil
Eric Anholt
Rob Clark
Laurent Carlier
Samuel Pitoiset
Marek Olšák
Nicolai Hähnle
Ilia Mirkin
Aaron Watry
Tom Stellard