Commit Graph

86488 Commits

Author SHA1 Message Date
Andres Gomez 5923088d75 dir-locals.el: Adds White Space support
Trailing white spaces will be now always highlighted, not just in
prog-mode.

Also, the White Space package, which is available since GNU Emacs 22,
is loaded and activated locally in prog-mode.

Additionally, using White Space variables, we set highlighting through
faces on wrong indentation and the maximum length of a coding line.

Notice that:
 - The highlighting for the characters beyond the set length of a
   coding line is not activated by default, only for wrong
   indentations.
 - If the White Space package is not available, errors on loading or
   activation are ignored.
 - If the White Space mode is not activated the set variables would
   not have any effect.

v2: Removed too long lines trail highlighting, as suggested by Ilia
    Mirkin.

Signed-off-by: Andres Gomez <agomez@igalia.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-11-14 19:17:49 +02:00
Iago Toral Quiroga 9730f2734b anv/format: support VK_FORMAT_R8G8B8_SRGB
Fixes dEQP-VK.api.image_clearing.clear_color_image.1d_r8g8b8_srgb

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2016-11-14 17:13:42 +01:00
Iago Toral Quiroga 35deeda66f anv/format: handle unsupported formats properly
According to the spec for vkGetPhysicalDeviceImageFormatProperties:

"If format is not a supported image format, or if the combination of format,
 type, tiling, usage, and flags is not supported for images, then
 vkGetPhysicalDeviceImageFormatProperties returns VK_ERROR_FORMAT_NOT_SUPPORTED."

Makes the following Vulkan CTS tests report 'Not Supported' instead of crashing:

dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8_unorm
dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8_snorm
dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8_uscaled
dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8_sscaled
dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8_uint
dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8_sint
dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8_srgb
dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8a8_unorm
dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8a8_snorm
dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8a8_uscaled
dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8a8_sscaled
dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8a8_uint
dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8a8_sint
dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8a8_srgb
dEQP-VK.api.image_clearing.clear_color_image.1d_r4g4_unorm_pack8
dEQP-VK.api.image_clearing.clear_color_image.1d_r8_srgb
dEQP-VK.api.image_clearing.clear_color_image.1d_r8g8_srgb
dEQP-VK.api.image_clearing.clear_color_image.1d_r8g8b8_srgb
dEQP-VK.api.image_clearing.clear_color_image.1d_b5g5r5a1_unorm_pack16

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2016-11-14 17:13:42 +01:00
Vedran Miletić 8e430ff8b0 clover: adapt to new error API since LLVM r286752
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2016-11-14 15:50:29 +00:00
Tim Rowley c8a51fa75d swr: [rasterizer core] remove driverType
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-11-14 09:03:10 -06:00
Tim Rowley ddc898aaf3 swr: [rasterizer archrast] move to pass by value
Move to pass by value since most events are very small in size.

We can look at pass by reference but will need to create multiple
versions to handle temp objects.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-11-14 09:03:04 -06:00
Tim Rowley 23e459b606 swr: [rasterizer core] add mode for aux buffer in the SWR_SURFACE_STATE
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-11-14 09:02:59 -06:00
Tim Rowley e9a3ad164d swr: [rasterizer common] don't bleed NOMINMAX definition after <windows.h>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-11-14 09:02:53 -06:00
Tim Rowley cd8d840ce1 swr: [rasterizer archrast] add events
Added events for tracking early/late Depth and stencil events,
TE patch info, GS prim info, and FrontEnd/BackEnd DrawEnd events.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-11-14 09:02:48 -06:00
Tim Rowley 7c3ca2e704 swr: [rasterizer core] fix culling issues
- Do proper culling of wireframe triangles (including non-culling of
  degenerates)
- Fix degenerate culling of CCW front-facing triangles in wireframe and
  conservative rast

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-11-14 09:02:42 -06:00
Tim Rowley cee66dd2aa swr: [rasterizer core/jitter] fix alpha test bug
Alpha from render target 0 should always be used for alpha test for all
render targets, according to GL and DX9 specs. Previously we were using
alpha from the current render target.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-11-14 09:02:36 -06:00
Tim Rowley 5912552947 swr: [rasterizer core] various code style changes
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-11-14 09:02:31 -06:00
Tim Rowley 584b65ad44 swr: [rasterizer archrast] don't generate empty files
Don't generate files when no events have been generated outside
the header events.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-11-14 09:02:25 -06:00
Tim Rowley e6f7d8a094 swr: [rasterizer archrast] fix open file handle limit issue
Buffer events ourselves and then when that's full or we're destroying
the context then write the contents to file. Previously, we're relying
ofstream to buffer for us.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-11-14 09:02:17 -06:00
Tim Rowley 2c697754a9 swr: [rasterizer archrast] fix double free issue
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-11-14 09:02:11 -06:00
Tim Rowley dc8408920c swr: [rasterizer core] separate frontend/backend stats enables
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-11-14 09:02:04 -06:00
Tim Rowley 937b7d8e5a swr: [rasterizer core] 16-wide tile store nearly completed
* All format combinations coded
* Fully emulated on AVX2 and AVX
* Known issue: the MSAA sample locations need to be adjusted for 8x2

Set ENABLE_AVX512_SIMD16 and USD_8x2_TILE_BACKEND to 1 in knobs.h to enable

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-11-14 09:00:59 -06:00
Emil Velikov f233bcda89 docs: add news item and link release notes for 13.0.1
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2016-11-14 11:39:01 +00:00
Emil Velikov 0a2b7c16c4 docs: add sha256 checksums for 13.0.1
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit b47ce6ddb8)
2016-11-14 11:37:52 +00:00
Emil Velikov eeedb52f75 docs: add release notes for 13.0.1
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit f2f487ebbb)
2016-11-14 11:37:51 +00:00
Juan A. Suarez Romero 7b9a9a0c5d i965/vec4: skip registers already marked as no_spill
Do not evaluate spill costs for registers that were already marked as
no_spill.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-11-14 10:09:30 +01:00
Kenneth Graunke 151aecabe4 glsl: Don't crash on function names with invalid identifiers.
Karol Herbst's fuzzing efforts noticed that we would segfault on:

   void bug() {
      2(0);
   }

We just need to bail if the function name isn't an identifier.

Based on a bug fix by Karol Herbst.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97422
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-11-12 22:08:15 -08:00
Kenneth Graunke 9c676a6427 glsl: Fix assert fails when assignment expressions are in array sizes.
Karol Herbst's fuzzing efforts discovered that we would hit the
following assert:

   assert(dummy_instructions.is_empty());

when processing an illegal array size expression of

   float[(1=1)?1:1] t;

In do_assignment, we realized we needed an rvalue for (1 = 1), and
generated a temporary variable and assignment from the RHS.  We've
already flagged an error (non-lvalue in assignment), and return a bogus
value as the rvalue.  But process_array_size sees the bogus value, which
happened to be a constant expression, and rightly assumes that
processing a constant expression shouldn't have generated any code.
instructions.

To handle this, make do_assignment not generate any temps or assignments
when it's already raised an error - just return an error value directly.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98694
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-11-12 22:08:15 -08:00
Jonas Pfeil 5debfeb86f vc4: Add simulator kernel validation for multithreaded fragment shaders.
This is Jonas Pfeil's code from the kernel, brought back to Mesa by
anholt.
2016-11-12 19:21:46 -08:00
Eric Anholt 96ffee2d02 vc4: Mark threaded FSes as non-singlethread in the CL. 2016-11-12 19:21:46 -08:00
Eric Anholt ace0d810e5 vc4: Flag the last thread switch in the program as the last.
We don't allow the last thread switch to be inside control flow, to be
sure that we hit the last state exactly once.  If the last texturing was
in control flow, fall back to single threaded.
2016-11-12 19:21:46 -08:00
Eric Anholt 67f72c5f5d vc4: Add THRSW nodes after each tex sample setup in multithreaded mode.
This is a suboptimal implementation, but Jonas Pfeil found that it was
still a massive performance gain.
2016-11-12 19:21:46 -08:00
Eric Anholt e3c620e868 vc4: Add some spec citations about texture fifo management. 2016-11-12 18:46:35 -08:00
Eric Anholt fd2aff858b vc4: Use ra14/rb14 as the spilling registers.
This makes the raddr fixups compatible with FS threading.
2016-11-12 18:46:35 -08:00
Eric Anholt 755037173d vc4: Add support for register allocation for threaded shaders.
We have two major requirements: Make sure that only the bottom half of the
physical reg space is used, and make sure that none of our values are live
in an accumulator across a switch.
2016-11-12 18:46:35 -08:00
Eric Anholt fdad4d2402 vc4: Split register class setup for physical files from accumulators. 2016-11-12 18:46:35 -08:00
Eric Anholt 8e704dca7f vc4: Use register allocator CLASS_BIT_R0_R3 to clean up CLASS_B.
We have had no reason to separate ability to store in an accumulator from
ability to store in B, but with FS threading, we need to be able to force
values to be stored only in the physical regfiles.
2016-11-12 18:46:35 -08:00
Eric Anholt 1ee503c74d vc4: Add support for QPU scheduling of thread switch instructions.
This is vaguely based off of Jonas Pfeil's thread switch support branch.
2016-11-12 18:46:35 -08:00
Eric Anholt 4f527f1260 vc4: Add a thread switch QIR instruction.
This will eventually be generated at the QIR level, so that
vc4_qir_schedule.c can arrange the separation of tex_strb from tex_result
correctly.  It will also be important so that register allocation set the
register classes appropriately for values that are live across the switch.
2016-11-12 18:46:35 -08:00
Eric Anholt 93cdae44de vc4: Add a bit of QPU validation for threaded shaders.
These are both bugs we've run into along the way writing multithreaded FS
support.
2016-11-12 18:46:35 -08:00
Eric Anholt 977d8b526b vc4: Fix register class handling of DDX/DDY arguments.
I had this exactly backwards, but apparently the piglit tests were all
landing in r0-r3 anyway.

Cc: "13.0" <mesa-stable@lists.freedesktop.org>
2016-11-12 18:46:35 -08:00
Darren Salt 9b121512ac radv/pipeline: Don't dereference NULL dynamic state pointers
This is a port of commit a4a59172482d50318a5ae7f99021bcf0125e0f53:

   Add guards to prevent dereferencing NULL dynamic pipeline state. Asserts
   of pCreateInfo members are moved to the earliest points at which they
   should not be NULL.

This fixes a segfault, related to pColorBlendState, seen in Talos Principle
which I've observed after startup is completed and when exiting the menus,
depending on when Vulkan rendering is selected.

v2: moved the NULL check in radv_pipeline_init_blend_state to after the
declarations.
Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2016-11-12 15:06:27 +01:00
Rob Clark dfc001dccc freedreno/ir3: fixup ralloc fallout
Fixes fallout from acc23b04 ("ralloc: remove memset from ralloc_size").
We were still depending on zero'd allocations in a couple of places.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-12 08:57:03 -05:00
Steinar H. Gunderson 2e2562cabb Fix races during _mesa_HashWalk().
There is currently no protection against walking a hash (using
_mesa_HashWalk()) and modifying it at the same time, for instance by inserting
or deleting elements. This leads to segfaults in multithreaded code if e.g.
someone calls glTexImage2D (which may have to walk the list of FBOs) while
another thread is calling glDeleteFramebuffers on another thread with the two
contexts sharing lists.

The reason for this is that _mesa_HashWalk() doesn't actually take the mutex
that normally protects the hash; it takes an entirely different mutex.
Thus, walks are only protected against other walks, and there is also no
outer lock taking this. There is an old comment saying that this is to fix
problems with deadlock if the callback needs to take a mutex; we solve this
by changing the mutex to be recursive.

A demonstration Helgrind hit from a real application:

==13412== Possible data race during write of size 8 at 0x3498C6A8 by thread #1
==13412== Locks held: 2, at addresses 0x1AF09530 0x2B3DF400
==13412==    at 0x1F040C99: _mesa_hash_table_remove (hash_table.c:395)
==13412==    by 0x1EE98174: _mesa_HashRemove_unlocked (hash.c:350)
==13412==    by 0x1EE98174: _mesa_HashRemove (hash.c:365)
==13412==    by 0x1EE2372D: _mesa_DeleteFramebuffers (fbobject.c:2669)
==13412==    by 0x6105AA4: movit::ResourcePool::cleanup_unlinked_fbos(void*) (resource_pool.cpp:473)
==13412==    by 0x610615B: movit::ResourcePool::release_fbo(unsigned int) (resource_pool.cpp:442)
[...]
==13412== This conflicts with a previous read of size 8 by thread #20
==13412== Locks held: 2, at addresses 0x1AF09558 0x1AF73318
==13412==    at 0x1F040CD9: _mesa_hash_table_next_entry (hash_table.c:415)
==13412==    by 0x1EE982A8: _mesa_HashWalk (hash.c:426)
==13412==    by 0x1EED6DFD: _mesa_update_fbo_texture.part.33 (teximage.c:2683)
==13412==    by 0x1EED9410: _mesa_update_fbo_texture (teximage.c:3043)
==13412==    by 0x1EED9410: teximage (teximage.c:3073)
==13412==    by 0x1EEDA28F: _mesa_TexImage2D (teximage.c:3105)
==13412==    by 0x166A68: operator() (mixer.cpp:454)

There are many more interactions than just these two possible.

Cc: 11.2 12.0 13.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Steinar H. Gunderson <steinar+mesa@gunderson.no>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-11-12 12:42:07 +11:00
Kenneth Graunke 07566ad4b6 i965: Drop tabs in brw_state.h. 2016-11-11 17:12:46 -08:00
Daniel Scharrer 0b98e885e7 ac/nir/llvm: Fix setting function attributes for intrinsics
This fixes a NULL pointer dereference for intrinsics with more than
one function attribute introduced in commit 2fdaf38.
The fix is ported from the lp_build_intrinsic changes in commit 8bdd52c.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2016-11-11 22:40:32 +01:00
Kenneth Graunke 74d5d393df i965: Update a comment: s/brw_state_cache/brw_program_cache/g
Tim renamed this recently - stop referring to it by the old name.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2016-11-11 13:19:18 -08:00
Laurent Carlier 3ff9f8c532 clover: fix building since llvm r286566
pretty trivial fix
2016-11-11 19:45:22 +00:00
Emil Velikov 6ff948ece1 egl/wayland: fix return value in dri2_wl_swrast_commit_backbuffer
The function returns "void" rather than int. We could rework that, yet
again there will be no benefit since all the callers have no use of it.

Fixes: 9ca6711faa ("Revert "wayland: Block for the frame callback in
get_back_bo not dri2_swap_buffers"")
Reviewed-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2016-11-11 17:33:37 +00:00
Brian Paul 92ec47a6ba glsl: define __STDC_FORMAT_MACROS to get PRIx64 macro
Otherwise, inttypes.h may not define the macro for C++ on MinGW.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98681
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2016-11-11 09:43:29 -07:00
Brian Paul f9052536c9 mesa: fix comment indentation in bind_buffers_check_offset_and_size()
Trivial.
2016-11-11 09:43:29 -07:00
Emil Velikov db45f1eaab glsl: automake: add opt_add_neg_to_sub.h to the sources list
Otherwise it'll be missing in the release tarball.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2016-11-11 14:46:12 +00:00
Timothy Arceri e36f0878cf i965: update gl_PrimitiveIDIn to be a system variable
Now that we have switched to using nir_shader_gather_info() we
can remove the hacks and just use the system variable.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-11-11 20:39:09 +11:00
Timothy Arceri 00620782c9 i965: use nir_shader_gather_info() over do_set_program_inouts()
This takes us one step closer to being able to drop the GLSL IR
optimisation passes during linking in favour of the NIR passes.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-11-11 20:39:09 +11:00
Timothy Arceri e86fc2c285 i965: remove remaining tabs in brw_program_cache.c
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2016-11-11 20:39:09 +11:00