Commit Graph

64691 Commits

Author SHA1 Message Date
Chris Forbes 4a3667993e i965: Enable ARB_gpu_shader5 on Gen7
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-15 19:24:56 +12:00
Chris Forbes abedd05bcd i965/fs: Add support for nonconst sampler indexing in FS visitor
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-15 19:13:33 +12:00
Chris Forbes fbfcd671a1 i965/fs: Add support for non-const sampler indices in generator
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-15 19:13:32 +12:00
Chris Forbes 4ba5171f30 i965/fs: Refactor generate_tex in prep for nonconst sampler indexing
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-15 19:13:32 +12:00
Chris Forbes 2b1204aa96 i965/fs: Use brw_adjust_sampler_state_pointer in fs generator too
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-15 19:13:32 +12:00
Chris Forbes 2cd6169e92 i965/vec4: Add support for nonconst sampler indexing in VS visitor
V2: Set force_writemask_all on ADD; this *is* necessary in the VS case
too.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-15 19:12:45 +12:00
Chris Forbes 301b71557b i965/vec4: Add support for non-const sampler indices in generator
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-15 19:10:32 +12:00
Chris Forbes 86dc34a0b0 i965: Generalize sampler state pointer mangling for non-const
For now, assume that the addressed sampler can be in any of the
16-sampler banks. If we preserved range information this far, we
could avoid emitting these instructions if the sampler were known
to be contained within one bank.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-15 19:10:29 +12:00
Chris Forbes f7146d1a94 i965/vec4: Refactor generate_tex in prep for non-const samplers
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-15 19:10:28 +12:00
Chris Forbes 8ce3fa8e91 i965: Extract helper function for surface state pointer adjustment
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-15 19:10:19 +12:00
Chris Forbes ceaf823e23 docs: Mark off ARB_gpu_shader5 UBO array indexing for i965
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
2014-08-15 18:53:48 +12:00
Chris Forbes 70354ca668 i965/vec4: Add visitor support for nonconst ubo block indexing
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
2014-08-15 18:53:48 +12:00
Chris Forbes a55eae9b6d i965/vec4: Generate indirect sends for nonconstant UBO array access
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
2014-08-15 18:53:48 +12:00
Chris Forbes ad9fce6811 i965/fs: Add visitor support for nonconstant UBO indices
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
2014-08-15 18:53:48 +12:00
Chris Forbes 3fd359b10d i965/fs: Generate indirect sends for nonconstant UBO array accesses
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
2014-08-15 18:53:47 +12:00
Chris Forbes 17e0fa9a06 i965: Adjust set_message_descriptor to handle non-sends
We're about to be using this infrastructure to build descriptors in
src1 of non-send instructions, when preparing to do an indirect send.

Don't accidentally clobber the conditionalmod field of those
instructions with SFID bits, which aren't part of the descriptor.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
2014-08-15 18:53:47 +12:00
Chris Forbes 3512c79789 i965: Add low-level support for indirect sends
This provides a reasonable place to enforce the hardware restriction
that indirect descriptors must be in a0.0

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
2014-08-15 18:53:47 +12:00
Kenneth Graunke 35ca288165 i965/fs: Add pass to rename registers to break live ranges.
The pass breaks live ranges of virtual registers by allocating new
registers when it sees an assignment to a virtual GRF it's already seen
written.

total instructions in shared programs: 4337879 -> 4335014 (-0.07%)
instructions in affected programs:     343865 -> 341000 (-0.83%)
GAINED:                                46
LOST:                                  1

[mattst88]: Make pass not break in presence of control flow.
            invalidate_live_intervals() only if progress.
            Fix up delta_x/delta_y.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2014-08-14 23:50:12 -07:00
Kenneth Graunke 650c331378 i965: Fix INTDIV math assertions on Broadwell.
Commit c66d928f2c ("i965: Enable INTDIV
in SIMD16 mode.") began using generate_math_gen6 to break SIMD16 INTDIV
into two SIMD8 operations.

generate_math_gen6 takes two registers - for unary operations, we pass
ARF null for the second operand.  Prior to Broadwell, real operands were
always GRF.  But now they can be IMM as well.

So, check for != ARF instead of == GRF.

+12 piglits.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-14 23:21:34 -07:00
Kenneth Graunke e84e074248 Revert "i965/vec4: Use MOV, not OR, to set URB write channel mask bits."
This reverts commit af13cf609f, which
appears to cause huge performance problems on Ivybridge.  I'd missed
that the FFTID bits are in the low byte.  The documentation doesn't
indicate that the URB write message header actually wants FFTID - it
just labels those bits as "Reserved."  But it appears necessary.

This does slightly more than revert the original change: originally,
Broadwell had separate code generation, which used MOV, and this patch
only changed it for Gen4-7.  Now that both are unified, reverting this
also makes Broadwell use OR.  Which should be fine.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-14 23:21:28 -07:00
Chris Forbes 417cc8b2c8 docs: Mark off ARB_derivative_control for i965.
Also update 10.3 relnotes to match.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-15 18:04:09 +12:00
Chris Forbes 654b7788eb i965: Enable ARB_derivative_control on Gen7+.
The extension says GL 4.0 is required. We'll meet the spirit
of that restriction by enabling on just those generations which will
soon support GL 4.0 (Gen7+), although it's technically supportable on
all generations.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-15 18:04:06 +12:00
Chris Forbes a396224520 i965/fs: Support fine/coarse derivative opcodes
The quality level (fine/coarse/dont-care) is plumbed through to the
generator as a constant in src1.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-15 18:04:04 +12:00
Chris Forbes 587e6e7898 i965/vec4: Assert that fine/coarse derivative ops don't appear
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-15 18:04:03 +12:00
Chris Forbes eba0c54f62 glsl: Mark program as using dFdy if coarse/fine variant is used
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-15 18:03:53 +12:00
Ilia Mirkin f08d7b8fe1 nv50,nvc0: add support for fine derivatives
The quadop-based method we currently use on all chipsets already
provides the fine version of the derivatives.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-08-14 20:25:33 -04:00
Ilia Mirkin 88b0c6403f mesa/st: add support for emitting fine derivative opcodes
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-08-14 20:25:32 -04:00
Ilia Mirkin 8ee74ce50f gallium: add opcodes/cap for fine derivative support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1)
Reviewed-by: Roland Scheidegger <sroland@vmware.com> (v1)
v2: Reuse opcode gaps as suggested by Marek
2014-08-14 20:25:32 -04:00
Ilia Mirkin 3fa384db0c mesa/program: add new derivative unops to the unexpected list
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-08-14 20:25:32 -04:00
Ilia Mirkin f80c6847e9 glsl: add ARB_derivative control support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-08-14 20:25:32 -04:00
Ilia Mirkin 4a9c36c985 mesa: add ARB_derivative_control extension bit
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-14 20:25:32 -04:00
Ilia Mirkin e474cb4027 mesa: add ARB_texture_barrier support
This extension is identical to NV_texture_barrier. Alias
glTextureBarrier to the existing glTextureBarrierNV and use the existing
NV_texture_barrier extension bit.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-08-14 20:25:32 -04:00
Marek Olšák c3bd130784 docs: document radeonsi BPTC support, sort extensions in 10.3 release notes 2014-08-15 02:05:05 +02:00
Glenn Kennard f23ee74791 r600g: Implement BPTC texture support
Requires Evergreen/Cayman

Signed-off-by: Glenn Kennard <glenn.kennard@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2014-08-15 01:55:13 +02:00
Kristian Høgsberg 221d9c3e9c i965: Rename intelValidateState to intel_update_state
This matches the name of the dd hook.  Also convert a couple of nearby
dd implementations to lowercase + underscore as is now the standard.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-14 13:57:26 -07:00
Kristian Høgsberg 416dd873e8 i965: Assign PS kernel start pointers when we decide which kernels to use
Right now we decide which kernels to use and the GRF start offsets in
one place and emit the kernel pointers later.  The logic of how to map
8, 16 and 32 kernels to kernel start pointers follows the same logic as which
GRF start offsets to use, so lets figure out these two things in one place.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
2014-08-14 13:57:26 -07:00
Grigori Goronzy d7d8260f70 radeonsi: implement BPTC texture support
Passes all piglit tests.

v2: rebased

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2014-08-14 20:45:03 +02:00
Marek Olšák 87a8ed9389 radeonsi: fix buffer invalidation of unbound texture buffer objects
This maintains a list of all TBOs in a pipe_context.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-08-14 20:45:03 +02:00
Marek Olšák 79f28cdb98 r600g: implement invalidation of texture buffer objects
This fixes piglit spec/ARB_texture_buffer_object/data-sync.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-14 20:45:03 +02:00
Marek Olšák da9c3ed304 r600g: fix constant buffer fetches
Somebody forgot to do this. It was uncovered by recent st/mesa changes.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82139

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Tested-by: Andreas Boll <andreas.boll.dev@gmail.com>
2014-08-14 20:45:03 +02:00
Marek Olšák d52202141e r600g: clear constant buffer sizes at the beginning of CS
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-14 20:45:03 +02:00
Pekka Paalanen 08264e5dad egl_dri2: fix EXT_image_dma_buf_import fds
The EGL_EXT_image_dma_buf_import specification was revised (according to
its revision history) on Dec 5th, 2013, for EGL to not take ownership of
the file descriptors.

Do not close the file descriptors passed in to eglCreateImageKHR with
EGL_LINUX_DMA_BUF_EXT target.

It is assumed, that the drivers, which ultimately process the file
descriptors, do not close or modify them in any way either. This avoids
the need to dup(), as it seems we would only need to just close the
dup'd file descriptors right after.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76188
Signed-off-by: Pekka Paalanen <pekka.paalanen@collabora.co.uk>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-14 21:30:57 +03:00
Pekka Paalanen 972e87ca30 i965: fix compiler error in union initiliazer
gcc 4.6.3 chokes with the following error:

brw_vec4.cpp: In member function 'int brw::vec4_visitor::setup_uniforms(int)':
brw_vec4.cpp:1496:37: error: expected primary-expression before '.' token

Apparently C++ does not do named initializers for unions, except maybe
as a gcc extension, which is not present here.

As .f is the first element of the union, just drop it. Fixes the build
error.

Signed-off-by: Pekka Paalanen <pekka.paalanen@collabora.co.uk>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-14 21:30:57 +03:00
Anuj Phogat 9b9dd22f44 i965: Bail on FS copy propagation for scratch writes with source modifiers
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-14 11:03:00 -07:00
Anuj Phogat 7c1ea00eaf i965: Bail on vec4 copy propagation for scratch writes with source modifiers
Fixes Khronos GLES3 CTS test:
dynamic_expression_array_access_vertex

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-14 11:03:00 -07:00
Aras Pranckevicius 2b837576eb glsl: Fixed vectorize pass vs. texture lookups.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82574
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-14 09:40:33 -07:00
Brian Paul 088106fa79 ra: move declarations before code to fix MSVC build
Trivial.
2014-08-14 08:53:45 -06:00
Brian Paul bfb6b76665 svga: remove some unneeded INLINE qualifiers
Trivial.
2014-08-14 08:53:45 -06:00
Emil Velikov 478f82737c docs/autoconf: update to better reflect reality
* --enable-{32,64}-bit is done. Use --build and --host instead.
 * Configure does not add "-g -O2" to C{,XX}FLAGS.
 * Pkg-config has been mandatory for a while now.
 * Avoid using LDFLAGS, refer to pkg-config.
 * --with-expat is deprecated. Use pkg-config.

v2:
 * Note that CC/CXX will need to be set for multilib builds.
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com> (v1)
2014-08-14 15:45:23 +01:00
Jose Fonseca d4a1f3fd27 scons: do not include headers from the sources lists
The SCons documentation is not explicit on the topic yet building mesa
with SCons and MSVC is known to have problems when headers are listed.
So be safe just drop them for now.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82534
Tested-by: Vinson Lee <vlee@freedesktop.org>
Acked-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-08-14 15:38:04 +01:00