Commit Graph

188881 Commits

Author SHA1 Message Date
Mike Blumenkrantz a50c17802a kopper: fix bufferage/swapinterval handling for non-window swapchains
if swapchain creation fails (e.g., insane cts swapchain configs), the
swapchain gets demoted to a non-window image that is still accessed by
the frontend. this image should not ever hit corresponding zink entrypoints
for swapchain-only images, which requires a flag to test swapchain-edness

cc: mesa-stable

Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28904>
2024-04-29 23:08:11 +00:00
JCWasmx86 7352f948be meson: Fix invalid kwarg name
Introduced in !28576

Fixes:  44b080af ("meson: implement split-debug")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28924>
2024-04-29 20:52:12 +00:00
Erik Faye-Lund 8248cc0bf4 docs/panfrost: move details to separate articles
The front-page of the docs is currently fairly intimidating, by diving
into details rather abruptly. Let's try to make it a bit easier to
navigate t by moving the details to their own articles, but linking them
from the front-page.

Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28953>
2024-04-29 13:24:51 +00:00
Erik Faye-Lund da2cc20714 docs/panfrost: compact gpu-table
This table is getting long and terse, let's compact it a bit.

Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28953>
2024-04-29 13:24:51 +00:00
Christian Gmeiner 2cb8e9a856 etnaviv: isa: Add name for full writemask
Is needed to generate a nicer code.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28929>
2024-04-29 13:02:28 +00:00
Christian Gmeiner cb69595037 etnaviv: isa: Rework modeling of left shift for store/load
This makes is easier for the parser to process.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28929>
2024-04-29 13:02:27 +00:00
Christian Gmeiner f8c38ec648 etnaviv: isa: Add more flags to etna_inst
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28929>
2024-04-29 13:02:27 +00:00
Christian Gmeiner a0dad2e705 etnaviv: isa: Switch to enum isa_thread
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28929>
2024-04-29 13:02:27 +00:00
Christian Gmeiner 87e5ad3930 etnaviv: isa: Print dst_full for ALU
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28929>
2024-04-29 13:02:27 +00:00
Christian Gmeiner 0c70dcd6f7 etnaviv: isa: Add clang-format special comments
We want to keep the defines as formated as they are.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28929>
2024-04-29 13:02:27 +00:00
David Rosca bc72126cb4 radeonsi/vcn: Only enable VBAQ with rate control mode
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10020
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28945>
2024-04-29 12:38:33 +00:00
David Rosca b144f50190 radeonsi/vcn: Fix 10bit HEVC VPS general_profile_compatibility_flags
Cc: mesa-stable
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28945>
2024-04-29 12:38:33 +00:00
David Rosca cc0df497f0 radeonsi/vcn: Allocate session buffer in VRAM
It's never mapped so there's no reason for PIPE_USAGE_STAGING.
Improves encoding performance on dGPUs.

Tested with 7900XTX (before 1900fps => after 2100fps):

  ffmpeg -hide_banner -hwaccel vaapi -hwaccel_device /dev/dri/renderD128 \
  -f lavfi -i testsrc=size=640x640,format=nv12 -vf hwupload -c:v av1_vaapi \
  -f null -

Cc: mesa-stable
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28945>
2024-04-29 12:38:33 +00:00
Samuel Pitoiset 0b51868193 radv: remove bogus VkShaderCreateInfoEXT::flags being 0 assert for compute
This was a leftover. Flags can be different than 0, like for required
subgroup size and it should already be correctly supported.

Fixes recent dEQP-VK.shader_object.performance.dispatch_base.

Fixes: 37d7c2172b ("radv: add support for creating/destroying shader objects")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28946>
2024-04-29 11:45:03 +00:00
Christian Gmeiner 8c2a749f67 etnaviv: isa: Drop capturing of python output
Is nicer for meson.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28875>
2024-04-29 11:26:03 +00:00
Samuel Pitoiset 85deb9f706 radv: simplify DB_Z_INFO.NUM_SAMPLES with null ds target on GFX11
According to PAL, the hw uses the smaller value of
DB_Z_INFO.NUM_SAMPLES and PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES when
there is no bound depth/stencil buffer, and it uses 8x to make sure
the used value is MSAA_EXPOSED_SAMPLES.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28952>
2024-04-29 11:02:02 +00:00
Eric Engestrom 45edd99b6b ci: mark microsoft farm as offline
It's having issues right now.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28967>
2024-04-29 12:53:51 +02:00
Kenneth Graunke 674e89953f intel/brw: Use new builder helpers that allocate a VGRF destination
With the previous commit, we now have new builder helpers that will
allocate a temporary destination for us.  So we can eliminate a lot
of the temporary naming and declarations, and build up expressions.

In a number of cases here, the code was confusingly mixing D-type
addresses with UD-immediates, or expecting a UD destination.  But the
underlying values should always be positive anyway.  To accomodate the
type inference restriction that the base types much match, we switch
these over to be purely UD calculations.  It's cleaner to do so anyway.

Compared to the old code, this may in some cases allocate additional
temporary registers for subexpressions.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28957>
2024-04-29 07:51:45 +00:00
Kenneth Graunke 4c2c49f7bc intel/brw: Add builder helpers that allocate temporary destinations
In many cases, we calculate an expression by generating a series of
instructions.  We'd either overwrite the same register repeatedly,
or call vgrf(BRW_TYPE_X) repeatedly to allocate temporaries for each
intermediate step.  In many cases, we overwrote the same register simply
because allocating and naming temporaries for each step was annoying.

This commit adds new builder helpers that will allocate a temporary
destination for you, using simple type interference: unary operations
use the source type, and binary operations require a matching base type
and return the largest of the two types.

The helpers return the destination register, allowing us to write in an
expression-tree style, chaining together builder operations to produce
whole values.  Sort of like nir_builder.  We still optionally will write
out the fs_inst pointer in case the caller wants to do things like set
predicates or saturation.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28957>
2024-04-29 07:51:45 +00:00
Kenneth Graunke 319ba85e10 intel/brw: Add builder helpers for math functions
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28957>
2024-04-29 07:51:45 +00:00
Kenneth Graunke cf8ed9925f intel/brw: Make a helper for finding the largest of two types
Some instructions can operate on mixed types.  Typically this is
something like a binary operation with UD and UW sources resulting
in a UD destination.  In order to make it easier to find the result
type of such operations, let's make a type helper that returns the
larger of the two types (but requires the base type to match).

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28957>
2024-04-29 07:51:45 +00:00
Kenneth Graunke f5473e6edd intel/brw: Don't use inst return value when it isn't needed
We just want to emit an instruction, but we don't need to do anything
further with it, so we don't need to store the resulting inst pointer
anywhere.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28957>
2024-04-29 07:51:45 +00:00
Samuel Pitoiset dfe5e56671 radv/ci: add more flakes
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28963>
2024-04-29 08:34:45 +02:00
David Heidelberg 42b992cfab turnip: rename tu_queue_submit struct to follow ODR
Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28728>
2024-04-28 20:06:33 -07:00
Konstantin Seurer ea863c0c1c nir/print: Do not access invalid indices of load_uniform
load_uniform does not have io_semantics and component.

Fixes: a83fd26 ("nir/print: stop trying to match i/o vars using base/driver_location")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28962>
2024-04-28 16:06:46 +02:00
Karol Herbst cc9141f044 rust/program: remove Program::kernels
This was a terrible method as it cloned the entire list on each call.
Instead consumers should just take the lock and operate on a slice instead
to lower CPU overhead.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28872>
2024-04-27 18:19:53 +00:00
Karol Herbst d8ed73b5f6 rusticl/program: Arc the stored KernelInfo
This way we don't have to constantly copy the full thing at kernel
creation time lowering CPU overhead significantly.

With the previous changes clCreateKernel is basically for free.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28872>
2024-04-27 18:19:53 +00:00
Karol Herbst 672de78d66 core/kernel: skip validating unique kernel signatures
We do not support it at runtime anyway and assert on them to be unique
across devices at build time. This significantly reduces overhead of
clCreateKernel as this is something applications actually rely on being
fast.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28872>
2024-04-27 18:19:52 +00:00
Georg Lehmann 6ab4b2d7a0 spirv: preserve signed zero in modf
fsign's result can be +0.0 or -0.0 for -0.0. We already calculate
the signed zero, it's even faster to replace the fmul(fsign(x), ...) with ior.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28938>
2024-04-26 21:31:53 +00:00
Philipp Zabel c2053c5363 etnaviv: Allow collecing both GPU and NPU specs
If the primary core is a GPU, but a separate NPU exists, collect
NPU specs in addition to GPU specs.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28921>
2024-04-26 19:30:08 +00:00
Philipp Zabel a4653587cc etnaviv: Add a separate NPU pipe
Add a separate pipe for the NPU device when the primary device is a GPU.
In case of compute-only contexts, prefer to use the separate NPU pipe.

This allows to create a compute-only context that uses the NPU pipe on
a screen that has a 3D GPU as primary device.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28921>
2024-04-26 19:30:08 +00:00
Philipp Zabel 108d2103ea etnaviv: Pass npu to etna_screen_create in a separate parameter
Allow to pass both gpu and npu to etna_screen_create() separately,
in preparetion for devices with both 3D GPU and NPU.
Iterate over all cores or until both GPU and NPU are found.

If no 3D GPU was found, screen->gpu will be set to the npu as well,
so nothing changes for NPU-only devices.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28921>
2024-04-26 19:30:08 +00:00
Philipp Zabel 06683288e0 etnaviv: drm: Stop after model query failure
Calling etna_gpu_new() with a nonexisting core can happen when iterating
all cores. Bail immediately if querying the model failed, there is no
use in also failing to query the revision.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28921>
2024-04-26 19:30:08 +00:00
Philipp Zabel ba59882212 etnaviv: drm: Suppress get-param error message for non-existent core
The -ENXIO return value isn't necessarily an error condition.
When iterating over cores, this signals that there are no more
cores to be found.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28921>
2024-04-26 19:30:08 +00:00
Yiwei Zhang 4ec84adbed venus: fix to destroy all pipeline handles on early error paths
For early error returns, all pipeline handles have to be destroyed.
Otherwise the caller will treat those valid handles as successfully
created pipeline objects.

Cc: mesa-stable
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28944>
2024-04-26 17:35:29 +00:00
Michel Dänzer c3be21f177 wsi/wayland: Dispatch event queue in wsi_wl_swapchain_queue_present
With explicit sync, only if it wasn't done earlier for FIFO.

Prevents potentially unbounded memory usage for (wl_buffer.release
events in) the queue, since we don't dispatch the queue anywhere else
with explicit sync.

v2:
* Use wl_display_dispatch_queue_pending instead of
  wl_display_dispatch_queue_timeout. (Sebastian Wick)
* Call it from wsi_wl_swapchain_queue_present instead of
  wsi_wl_swapchain_acquire_next_image_explicit. (Joshua Ashton)

Fixes: 5f7a5a27ef ("wsi: Implement linux-drm-syncobj-v1")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28874>
2024-04-26 15:11:00 +00:00
Matt Turner 2a417e3fc1 intel: Build float64 shader only for Vulkan
It's only used by anv and it requires glslang, which isn't otherwise
required for building iris.

Fixes: b52e25d3a8 ("anv: rewrite internal shaders using OpenCL")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28943>
2024-04-26 14:08:32 +00:00
Eric Engestrom bdbcba5269 v3dv/ci: add rpi5 failure
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28950>
2024-04-26 13:47:37 +00:00
Connor Abbott b4874aa5cf ir3: Use scalar ALU instructions when possible
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22075>
2024-04-26 12:55:14 +00:00
Connor Abbott 32308fe9f1 ir3/nir: Fix imadsh_mix16 definition
The constant-folding definition and comments say that it takes the high
16 bits of the first source and low 16 bits of the second source, but
actually it's the opposite. The algebraic optimization, which actually
happens and needs to be correct, was correct but the comment above it
was wrong.

Note that in the way we use it when lowering multiplications, the
ordering doesn't matter.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22075>
2024-04-26 12:55:14 +00:00
Connor Abbott 17cb1c78bd ir3: Directly use shared registers when possible
Avoid unnecessary copies.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22075>
2024-04-26 12:55:14 +00:00
Connor Abbott 3bec9e684d ir3: Rewrite shared reg handling when translating from NIR
In the future we will have many ALU instructions passing shared
registers to each other, and surrounding them each with moves to/from
shared registers will severely bloat the IR size coming out of NIR and
make more pointless work for copy propagation. Instead, do something
more like the ACO approach and allow values stored in the hash table to
be shared, and move the burden of emitting a mov to non-shared to
ir3_get_src(). We will then use ir3_get_src_shared() or
ir3_get_src_maybe_shared() as appropriate in cases where we can handle
shared registers or where we can handle both.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22075>
2024-04-26 12:55:14 +00:00
Connor Abbott 4828942d0c ir3: Get sources before emitting scan_clusters.macro
We will emit conversion move when getting sources and shared-ness
doesn't match, so it needs to be before emitting the instruction.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22075>
2024-04-26 12:55:14 +00:00
Connor Abbott ce6c4f0320 ir3: Add scalar ALU-specific passes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22075>
2024-04-26 12:55:13 +00:00
Connor Abbott 4c4234501f ir3: Support scalar ALU in the builder
Propagate shared-ness to the the source, and when creating an ALU
instruction with all scalar sources and the instruction is supported on
the scalar ALU, automatically make the destination scalar. This includes
MOV/COV.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22075>
2024-04-26 12:55:13 +00:00
Connor Abbott 823e034db2 ir3: Make type_flags() return a bitmask enum
So that it can further be operated on.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22075>
2024-04-26 12:55:13 +00:00
Connor Abbott ac132b3f62 ir3: Create reduce identity directly
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22075>
2024-04-26 12:55:13 +00:00
Connor Abbott 497fcd26b5 ir3: Add builder support for shared immediates
In addition to replacing existing no-longer-needed usage of the
readfirst macro, we will use this for other NIR ALU instructions that
need to materialize constants when they use the shared ALU.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22075>
2024-04-26 12:55:13 +00:00
Connor Abbott 736570b74d ir3: Add support for ldc.u
This will be important for using shared registers as much as possible.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22075>
2024-04-26 12:55:13 +00:00
Connor Abbott 94c1ff415b ir3: Distinguish lowered shared->normal moves
When we use the scalar ALU we will start inserting moves with different
API-level semantics from readInvocation() or readFirstInvocation(). We
need to distinguish between these moves and lowered readInvocation()
moves, to avoid unnecessarily keeping helper invocations alive when
inserting (eq).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22075>
2024-04-26 12:55:13 +00:00