Commit Graph

163600 Commits

Author SHA1 Message Date
Eric Engestrom 3b07d57ff9 commit_in_branch.py: fix tests
Apparently these were backported since I wrote these tests ^^

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19988>
2022-11-30 17:08:48 +00:00
Connor Abbott 8ba2d612d5 ir3: Don't save/restore disasm string pointer
It's not in the key, so it randomly may or may not be present, and if it
is present then we don't actually save/restore the contents, so we will
save/restore random pointer values from the last run. Turnip already
disables searching the shader cache when assembly is requested, but
still wrote the final ir3_shader_variant which resulted in trying to
save random stale pointers when saving off the executable if a
subsequent compile hit that cache entry.

This fixes flakes in
dEQP-VK.pipeline.pipeline_library.shader_module_identifier.pipeline_from_id.*
for me.

Fixes: 56909868cd ("turnip: implement VK_KHR_pipeline_executable_properties")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20056>
2022-11-30 16:39:59 +00:00
Connor Abbott 515c9a2e07 tu: Fix binding NULL descriptor sets
This fixes the new test
dEQP-VK.pipeline.pipeline_library.graphics_library.misc.other.null_descriptor_set_in_monolithic_pipeline.

Fixes: e9f5de11d4 ("tu: Initial implementation of VK_EXT_graphics_pipeline_library")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20057>
2022-11-30 15:09:24 +00:00
Lionel Landwerlin 863516dd63 radv: enable lower shader call vectorizing
Totals from 5 (71.43% of 7) affected shaders:
MaxWaves: 48 -> 50 (+4.17%)
Instrs: 32012 -> 32070 (+0.18%)
CodeSize: 172672 -> 172932 (+0.15%)
VGPRs: 512 -> 496 (-3.12%)
Latency: 715333 -> 715279 (-0.01%); split: -0.03%, +0.02%
InvThroughput: 149540 -> 146150 (-2.27%); split: -2.29%, +0.02%
VClause: 900 -> 897 (-0.33%)
Copies: 4173 -> 4199 (+0.62%); split: -0.12%, +0.74%
Branches: 1512 -> 1511 (-0.07%)
PreVGPRs: 475 -> 469 (-1.26%)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20075>
2022-11-30 11:13:13 +00:00
Samuel Pitoiset 96332b3433 radv: stop emitting R_00B8A0_COMPUTE_PGM_RSRC3 from the CS preamble
It will be always emitted as part of the compute pipeline.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20054>
2022-11-30 09:05:13 +00:00
Samuel Pitoiset 80072df824 radv: disable VRS entirely on GFX11
Based on registers, VRS changed a lot and it's unclear how to program
it. This disable VK_KHR_fragment_shading_rate, VRS flat shading and
RADV_FORCE_VRS.

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20054>
2022-11-30 09:05:13 +00:00
Samuel Pitoiset 5d552b4f6c radv: do not enable NGG culling on GFX11
RadeonSI disables it as well. It's really unclear if it will help or
not (eg. NGG culling never helped on GFX10).

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20054>
2022-11-30 09:05:13 +00:00
Samuel Pitoiset 84a7138d3c radv: do not enable DCC for MSAA images without FMASK
I don't know how this is supposed to work, especially for fast clears
because CMASK should be cleared to 0xC but FMASK implies CMASK.
This fixes a bunch of MSAA test failures on GFX10.3 with
RADV_DEBUG=nofmask.

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20054>
2022-11-30 09:05:13 +00:00
Samuel Pitoiset 9b637aa9a1 radv: set INTERPOLATE_COMP_Z to 0 on GFX11
Ported from RadeonSI to fix a EQAA bug.

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20054>
2022-11-30 09:05:13 +00:00
Samuel Pitoiset 62715a6d03 radv: set missing SPI_SHADER_PGM_xxx registers on GFX11
Found by inspection.

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20054>
2022-11-30 09:05:13 +00:00
Erik Faye-Lund d0342e28b3 nir: Add helper to create passthrough GS shader
Based on nir_create_passthrough_tcs and d3d12_make_passthrough_gs, this
creates a passthrough geometry shader that can be used by drivers that
needs to emulate some graphics features in the geometry shader.

Reviewed-by: Rob Clark <robclark@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19987>
2022-11-30 08:08:25 +00:00
Lionel Landwerlin 6f2dbe6da1 anv: enable lower_shader_calls vectorizing
On Q2RTX RT shaders :

Totals from 7 (22.58% of 31) affected shaders:
Instrs: 15453 -> 14418 (-6.70%)
Cycles: 232647 -> 224959 (-3.30%)
Send messages: 574 -> 481 (-16.20%)
Spill count: 118 -> 106 (-10.17%)
Fill count: 156 -> 140 (-10.26%)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20058>
2022-11-30 07:23:30 +00:00
Lionel Landwerlin 9d0560fe87 nir/lower_shader_calls: enable vectorizer
We cannot fully use the vectorizer outside of this pass because once
stack load/store operations have been lower to global load/store, the
robustness rule applies to those as they would to application
load/store.

But this is all internal and we know it doesn't require out of bound
checking. So doing the vectorizing here is the best solution. We just
have to teach the vectorizer about our intrinsics.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20058>
2022-11-30 07:23:30 +00:00
Lionel Landwerlin 9c76cda7f0 nir/lower_shader_calls: add a pass to split load/store into scalars
We'll run this pass prior to opt_load_store_vectorize to maximize the
effect of the optimization.

At the moment opt_load_store_vectorize is unable to pack this :

  store vec3
  store vec3
  store vec2

into this :

  store vec4
  store vec3

If your backend can only do vec4 stores max.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20058>
2022-11-30 07:23:30 +00:00
Lionel Landwerlin e84eab42c4 nir/lower_shader_calls: avoid moving loads into loops
This is similar to what opt_gcm is doing. Moving a load inside a loop
will increase memory bandwidth.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20058>
2022-11-30 07:23:30 +00:00
Jessica Clarke 750325730b panfrost/blend: Fix invalid const values leading to NIR validation errors
Using a designated initializer like this leaves padding bits, which form
part of the aliasing u64/f64 member of the union, uninitialised, but a
nir_const_value must always have the unused bits zeroed out. Thus, use
the nir_const_value_for_float helper instead like everywhere else which
will do a memset 0 for us first.

Without this, using the pan_blend shader in a build with validation
enabled fails with:

  NIR validation failed after nir_lower_vars_to_ssa
  ...
            vec4 32 ssa_58 = load_const (0x3f7cfcfd /* 0.988235 */, 0x3f7cfcfd /* 0.988235 */, 0x3f7cfcfd /* 0.988235 */, 0x3f800000 /* 1.000000 */)
  error: memcmp(val, &cmp_val, sizeof(cmp_val)) == 0 (../src/compiler/nir/nir_validate.c:976)

Fixes: 1378c67bcf ("panfrost/blend: Inline blend constants")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20071>
2022-11-30 04:49:17 +00:00
Yiwei Zhang 6148ccef63 venus: fix android wsi with global fencing disabled
Fixes: b21e4a7990 ("venus: put android wsi on the sub-optimal path")

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20049>
2022-11-30 01:13:56 +00:00
Sajeesh Sidharthan 8b99e96dc8 radeonsi/vcn: set current pic index correctly
video corruption observed while running decode test for av1
content in chromeos.

solution is when target buffer is found in render pic list and when
target codec is null, set curr_pic_indx as index to the
pic in render pic list.

Cc: mesa-stable
Signed-off-by: Sajeesh Sidharthan <sajeesh.sidharthan@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20000>
2022-11-29 23:41:37 +00:00
Karol Herbst 5398dd04bf nir/lower_int64: fix shift lowering
Starting with !19748 lowered 64 bit shifts were showing wrong results for
shifts with insignificant bits set.

nir shifts are defined to only look at the least significant bits. The
lowering has take this into account.

So there are two things going on:
1. the `ieq` and `uge` further down depend on `y` being masked.
2. the calculation of `reverse_count` actually depends on a masked `y` as
   well, due to the `(iabs (iadd y -32))` giving a different result for
   shifts > 31;

Fixes: 41f3e9e5f5 ("nir: Implement lowering of 64-bit shift operations")
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19995>
2022-11-29 23:08:53 +00:00
Emma Anholt 83efd336da ci/freedreno: Add another blend_equation_advanced flake.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20066>
2022-11-29 22:42:06 +00:00
Italo Nicola 7dd9bf45b9 panfrost: add GALLIUM_HUD=draw-calls
Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20063>
2022-11-29 22:27:07 +00:00
Connor Abbott 0a0a04bdaa tu: Use right enum for compute active_shader_stages
This is VkShaderStageFlags, not VkPipelineStageFlags. Fixes preloading
descriptors for compute dispatches.

Fixes: d862a2ebcb ("turnip: Only emit descriptor loads for active stages in the pipeline.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20059>
2022-11-29 22:02:20 +00:00
Emma Anholt f2414dc2a0 turnip: Drop the cs argument from tu6_emit_cache_flush*().
It's always draw_cs or cs.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19939>
2022-11-29 19:30:25 +00:00
Emma Anholt 939648bbd0 turnip: Clean up a repeated pattern around tu6_emit_flushes().
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19939>
2022-11-29 19:30:25 +00:00
Emma Anholt 43aae91803 turnip: Make tu_emit_cache_flush_ccu manage flush bits like other paths.
Everyone else sets the cache bits directly then calls tu6_emit_flushes on
them.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19939>
2022-11-29 19:30:25 +00:00
Samuel Pitoiset 07dc402a3f radv: inline gfx10_emit_streamout_{begin,end}()
Instead of having 2 different paths.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Tatsuyuki Ishi <ishitatsuyuki@gmail.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19632>
2022-11-29 16:50:13 +00:00
Roman Stratiienko 09ac29cca9 meson: Enable system_has_kms_drm for android
This allows to build libgbm when  system = 'android'  is set in
the cross_file.

Cc: "22.3" "22.2" mesa-stable
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Acked-by: Mauro Rossi <issor.oruam@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20033>
2022-11-29 15:01:22 +00:00
Rhys Perry ae521aaa2a radv: compile GS copy shader after geometry shader
This affects the pipeline feedback durations: GS copy shader compilation
is now included in the GS compilation duration.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18898>
2022-11-29 14:28:11 +00:00
Rhys Perry 0cb48ec3b7 radv,aco: remove old streamout code
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18898>
2022-11-29 14:28:11 +00:00
Rhys Perry 3a96977542 radv,aco: remove old GS copy shader code
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18898>
2022-11-29 14:28:11 +00:00
Rhys Perry 17bd2721e6 radv,aco: implement GS copy shaders using NIR
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18898>
2022-11-29 14:28:11 +00:00
Rhys Perry 3ab471a87d radv: make radv_use_llvm_for_stage device parameter const
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18898>
2022-11-29 14:28:11 +00:00
Rhys Perry 12becb8839 radv: lower streamout in NIR
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18898>
2022-11-29 14:28:11 +00:00
Rhys Perry 19d0403594 radv,aco: export legacy vertex outputs in NIR
This new behaviour will let us insert exports in GS copy shader control
flow.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18898>
2022-11-29 14:28:11 +00:00
Karmjit Mahil 09eb2a4023 pvr: Add missing valgrind includes and fix unused return value.
On including the header the compiler started throwing warnings
about the return value not being used when setting and getting the
vbits.

This commit adds the missing valgrind related headers and fixes the
warnings caused by including them.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Matt Coster <matt.coster@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20035>
2022-11-29 14:19:41 +00:00
Erik Faye-Lund 8d3475ab8c docs/zink: document missing max-image requirements
This should bring Zink's documentation up to speed with the previous
commit.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19780>
2022-11-29 13:35:46 +00:00
Erik Faye-Lund 2658d02516 mesa/main: verify more texture-limits for GL 4.1
OpenGL 4.1 also increased the minimum 3D and cube texture size as
well as the minimum number of texture-array layers. Let's also
verify these to prevent enbaling too recent GL versions on layered
drivers link Zink, VirGL etc.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19780>
2022-11-29 13:35:46 +00:00
Erik Faye-Lund dc770eb9bb zink: check maxImageDimension1D as well as maxImageDimension2D
According to the docs for PIPE_CAP_MAX_TEXTURE_2D_SIZE, it's the limit
both for 2D *and* 1D textures. So let's take the min of the two vulkan
features here instead of assuming they're the same.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19780>
2022-11-29 13:35:46 +00:00
Erik Faye-Lund 1b892c5a7d freedreno: fix PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS for a6xx
We're reporting 2048 for VkPhysicalDeviceLimits::maxImageArrayLayers on
Turnip, so we should be able to use 2048 for OpenGL as well. And that's
the minimum required value for OpenGL 4.1 support.

According to http://vulkan.gpuinfo.org/, it seems like values of 2048
should be possible for at least as low as some Adreno 4xx GPUs. But
since we don't support recent GL versions on those, we this won't make a
big difference. So let's leave that up to someone who actually knows
what they're doing!

Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19780>
2022-11-29 13:35:46 +00:00
Erik Faye-Lund d15e71ef3c d3d12: fix return-value for PIPE_CAP_MAX_TEXTURE_3D_LEVELS
D3D12_REQ_TEXTURE3D_U_V_OR_W_DIMENSION is 2^11, not 2^10 like the
comment said, and the code assumed. We need to add one to account for
the base-level.

Let's add a static_assert here to prove that this is the right value.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19780>
2022-11-29 13:35:46 +00:00
Erik Faye-Lund acc0039aec d3d12: fix max-array-layers
We used to need this, because we incorrectly multiplied the cube array
sizes by 6. Now that this has been fixed, we can actually support the
OpenGL 4.1 limit for this.

Fixes: 7118b2136e ("d3d12: Don't multiply cube array sizes by 6")
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19780>
2022-11-29 13:35:46 +00:00
Samuel Pitoiset 7e287609e3 radv: use HTILE for VRS image only on GFX10.3
Based on registers, GFX11 no longer uses HTILE.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19962>
2022-11-29 12:19:40 +00:00
Samuel Pitoiset e3d3fb2e69 radv: do not clear VRS_HTILE_ENCODING on GFX11
This field no longer exists.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19962>
2022-11-29 12:19:40 +00:00
Sarah Walker 2673d0f8b2 pvr: Query kernel for free list max size
Signed-off-by: Sarah Walker <sarah.walker@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19976>
2022-11-29 10:10:16 +00:00
Connor Abbott 5e5c42ebb5 tu: Fix fault with variable-count inline uniform blocks
This seems to have been triggered by some recent CTS changes which
changed the random number generation. I'm seeing context faults in
dEQP-VK.binding_model.descriptorset_random.sets4.dynindexed.ubolimitlow.sbolimitlow.sampledimghigh.lowimgnotex.iublimitlow.nouab.comp.noia.0
that are fixed by this.

Fixes: 37cde2c634 ("tu: Rewrite inline uniform implementation")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20039>
2022-11-29 09:42:52 +00:00
Aditya Swarup 6080dce4d8 intel/isl: Add MOCS settings for MTL platforms
Add MOCS settings for Xe platforms based on cache settings for L3/L4
and display.

Rework:
 * Jordan: Use intel_device_info_is_mtl()

BSpec: 45101
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20045>
2022-11-29 00:36:41 -08:00
Mauro Rossi ea10b0fc7a AOSP: Add intel_hasvk vulkan library suffix
Required to correctly install vulkan.intel_hasvk.so module
after commit 50013ca9 ("intel: add a hasvk vulkan driver")

In order to set property ro.hardware.vulkan as 'intel_hasvk' for the correct iGPU parts at init stage,
i915 'graphics version' can only be detected by means of /sys/kernel/debug/dri/0/i915_capabilities
and debugfs needs to be mounted at early-init stage

https://review.lineageos.org/c/LineageOS/android_device_lge_g3-common/+/19875

Cc: "22.3" mesa-stable
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Mauro Rossi <issor.oruam@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20048>
2022-11-29 09:05:17 +01:00
Qiang Yu 3507cdc59c ac/nir: legacy vs/gs use nir_xfb_info to replace pipe_stream_output_info
pipe_stream_output_info is built from nir_xfb_info, why not just use
nir_xfb_info directly.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20015>
2022-11-29 03:28:42 +00:00
Jianxun Zhang 59b29c5fc4 iris: Use devinfo::has_flat_ccs instead of verx10
The assumption that GFX12.5 devices don't have AUX map is
invalid since MTL's introduction.

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20043>
2022-11-29 02:47:44 +00:00
Jianxun Zhang 93baad8047 intel/dev: Set 'has_flat_ccs' flag for DG2
The code paths of flat ccs should be working on DG2 because
they are routed by other conditions like GFXVer so far. But
using this flag is the intended way, and we need to have
this change prior to updating these conditions with the flag.

Ref: 5262475242 ("intel/dev: Add a has_flat_ccs flag")

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20043>
2022-11-29 02:47:44 +00:00