Commit Graph

154044 Commits

Author SHA1 Message Date
Samuel Pitoiset 278e533ec9 radv: update scratch buffer registers on GFX11
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
2022-05-17 10:08:17 +00:00
Samuel Pitoiset 6e4d9729cc radv: use the new format table on GFX11
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
2022-05-17 10:08:17 +00:00
Samuel Pitoiset 2d02e210b5 radv: do not align VGPRS to 8 or 16 on GFX11
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
2022-05-17 10:08:17 +00:00
Tomeu Vizoso 9e031426be panvk/ci: Disable CI for a while
We have been hitting OOM conditions quite often and this is making ti
hard to get stuff merged.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16554>
2022-05-17 09:16:21 +00:00
Tomeu Vizoso e5acf8016d lima/ci: Disable lima-mali450-piglit-gpu:arm64
Due to a kernel regression, these jobs fail most of the time with the
backtrace below.

Disable while we get a fix in our kernel.

2022-05-17 08:00:15.428691: [  374.755841] ------------[ cut here ]------------
2022-05-17 08:00:15.428778: [  374.755883] kernel BUG at kernel/irq_work.c:235!
2022-05-17 08:00:15.429011: [  374.759409] Internal error: Oops - BUG: 0 [#1] PREEMPT SMP
2022-05-17 08:00:15.429077: [  374.764842] Modules linked in: ipv6
2022-05-17 08:00:15.429233: [  374.768294] CPU: 3 PID: 18210 Comm: vp-bad-program Not tainted 5.16.12linux-v5.16-for-mesa-ci-991fec6622591.tar.bz2 #1
2022-05-17 08:00:15.429386: [  374.778900] Hardware name: Libre Computer AML-S805X-AC (DT)
2022-05-17 08:00:15.429536: [  374.784421] pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
2022-05-17 08:00:15.429714: [  374.791320] pc : irq_work_run_list+0x64/0x70
2022-05-17 08:00:15.429780: [  374.795546] lr : irq_work_run+0x38/0x50
2022-05-17 08:00:15.429927: [  374.799342] sp : ffff80000801bf30
2022-05-17 08:00:15.430097: [  374.802618] x29: ffff80000801bf30 x28: ffff000003398e00 x27: ffff00000ed3e400
2022-05-17 08:00:15.430158: [  374.809691] x26: ffff800009678750 x25: ffff0000030d8900 x24: ffff800008846fa0
2022-05-17 08:00:15.430316: [  374.816763] x23: ffff800009909f80 x22: 0000000000000006 x21: ffff00000101e780
2022-05-17 08:00:15.430411: [  374.823836] x20: ffff800009d7c408 x19: ffff8000099089c8 x18: 0000000000000000
2022-05-17 08:00:15.430547: [  374.830908] x17: ffff8000252e9000 x16: ffff80000801c000 x15: 0000000000004000
2022-05-17 08:00:15.430735: [  374.837981] x14: 0000000000000000 x13: 0000000000000000 x12: 0000000000000001
2022-05-17 08:00:15.430797: [  374.845054] x11: 0000000000000001 x10: ffff8000252e9000 x9 : ffff00002ebf90e0
2022-05-17 08:00:15.430962: [  374.852126] x8 : fffffc00000eda08 x7 : ffff000003398e00 x6 : 0000000000001000
2022-05-17 08:00:15.431029: [  374.859199] x5 : 0000000000000000 x4 : ffff00002ebfc910 x3 : ffff00000ed3e430
2022-05-17 08:00:15.431194: [  374.866271] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff00002ebf19c8
2022-05-17 08:00:15.431261: [  374.873345] Call trace:
2022-05-17 08:00:15.431409: [  374.875761]  irq_work_run_list+0x64/0x70
2022-05-17 08:00:15.431557: [  374.879641]  ipi_handler+0x98/0x15c
2022-05-17 08:00:15.431726: [  374.883091]  handle_percpu_devid_irq+0x88/0x140
2022-05-17 08:00:15.431795: [  374.887576]  generic_handle_domain_irq+0x40/0x60
2022-05-17 08:00:15.431958: [  374.892147]  gic_handle_irq+0x48/0xd0
2022-05-17 08:00:15.432025: [  374.895769]  call_on_irq_stack+0x2c/0x60
2022-05-17 08:00:15.432211: [  374.899651]  do_interrupt_handler+0x80/0x84
2022-05-17 08:00:15.432364: [  374.903791]  el1_interrupt+0x34/0x84
2022-05-17 08:00:15.432432: [  374.907327]  el1h_64_irq_handler+0x1c/0x30
2022-05-17 08:00:15.432616: [  374.911380]  el1h_64_irq+0x78/0x7c
2022-05-17 08:00:15.432764: [  374.914744]  irq_work_queue+0x70/0x80
2022-05-17 08:00:15.432832: [  374.918367]  drm_sched_entity_fini+0x290/0x320
2022-05-17 08:00:15.433043: [  374.922766]  lima_sched_context_fini+0x18/0x24
2022-05-17 08:00:15.433161: [  374.927164]  lima_ctx_free+0x7c/0x114
2022-05-17 08:00:15.433228: [  374.930787]  lima_ioctl_ctx_free+0x28/0x40
2022-05-17 08:00:15.433362: [  374.934840]  drm_ioctl_kernel+0xc4/0x170
2022-05-17 08:00:15.433522: [  374.938721]  drm_ioctl+0x21c/0x440
2022-05-17 08:00:15.433587: [  374.942085]  __arm64_sys_ioctl+0xac/0xf0
2022-05-17 08:00:15.433748: [  374.945966]  invoke_syscall+0x48/0x114
2022-05-17 08:00:15.433814: [  374.949675]  el0_svc_common.constprop.0+0x44/0xec
2022-05-17 08:00:15.433977: [  374.954332]  do_el0_svc+0x28/0x90
2022-05-17 08:00:15.434041: [  374.957609]  el0_svc+0x20/0x60
2022-05-17 08:00:15.434204: [  374.960629]  el0t_64_sync_handler+0x1a8/0x1b0
2022-05-17 08:00:15.434269: [  374.964941]  el0t_64_sync+0x1a0/0x1a4
2022-05-17 08:00:15.434492: [  374.968568] Code: a8c27bfd d50323bf d65f03c0 d65f03c0 (d4210000)
2022-05-17 08:00:15.434612: [  374.974607] ---[ end trace 74ef9d6ff9457a3f ]---
2022-05-17 08:00:15.434676: [  374.979174] Kernel panic - not syncing: Oops - BUG: Fatal exception in interrupt
2022-05-17 08:00:15.434888: [  374.986505] SMP: stopping secondary CPUs
2022-05-17 08:00:15.435011: [  374.990391] Kernel Offset: 0x80000 from 0xffff800008000000
2022-05-17 08:00:15.435079: [  374.995818] PHYS_OFFSET: 0x0
2022-05-17 08:00:15.435243: [  374.998665] CPU features: 0x00,00004802,00000846
2022-05-17 08:00:15.435313: [  375.003236] Memory Limit: none
2022-05-17 08:00:15.435488: [  375.006258] ---[ end Kernel panic - not syncing: Oops - BUG: Fatal exception in interrupt ]---

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16554>
2022-05-17 09:16:21 +00:00
Kenneth Graunke b637f6c3db intel/decoder: Fix binding table pointer decoding with large offsets
XeHP supports a 20:5 pointer format, so the offset can legitimately
be more than UINT16_MAX.  Likewise, with 256B binding table mode on
Icelake/Tigerlake, we might have 18:8 pointers that exceed UINT16_MAX.

Thanks to Felix DeGrood for catching this!

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16538>
2022-05-17 08:52:00 +00:00
Pierre-Eric Pelloux-Prayer 8779a5b84c glx: set max values for pbuffer width / height
Without this change the values are always 0. This breaks
Maya which uses this value to create a pbuffer (and then
fails).

This commit is based on b91e1e38e8 which does the same
for EGL.

Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16496>
2022-05-17 07:21:34 +00:00
David Heidelberg d22eeb5ae0 ci/iris: skqp: remove flaking atlastext for TGL
Example:
 - https://gitlab.freedesktop.org/mesa/mesa/-/jobs/22380389#L4349
 - https://mesa.pages.freedesktop.org/-/mesa/-/jobs/22380389/artifacts///results/gles/report.html

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6460
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16407>
2022-05-17 06:57:19 +00:00
David Heidelberg 317496ba8a ci/iris: skqp: add default GLES rendertests for TGL
Import the intact whole rendertest file from skqp (branch
android-cts-12.1_r1) to be able remove the offending test line in the
following commit.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16407>
2022-05-17 06:57:19 +00:00
Dave Airlie a179e1aede aco/radv: drop radv_nir_compiler_options from aco.
Add a new aco input and options structs, then convert from radv
pieces on submit.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16521>
2022-05-17 06:15:25 +00:00
Dave Airlie 8198900071 ac/radv: drop info pointer from the ac and radv shader structs
This was being used for one bool, just pass the bool.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16521>
2022-05-17 06:15:25 +00:00
Mike Blumenkrantz 55845409f2 zink: add tu baseline for a630
oof

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16549>
2022-05-17 06:04:31 +00:00
Mike Blumenkrantz fffafa3635 zink: move get_timestamp to screen
this doesn't need to use a particular context

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16529>
2022-05-17 03:46:56 +00:00
Mike Blumenkrantz 0befc259a6 zink: use copy context to eliminate dependency on EXT_calibrated_timestamps
this is unsupported by a surprising number of drivers

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16529>
2022-05-17 03:46:56 +00:00
Mike Blumenkrantz 9d30d82a9a zink: fix init with MESA_SHADER_CACHE_DISABLE enabled
Fixes: ba2f5cb20a ("zink: check for error when initializing util_queue")

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16533>
2022-05-17 03:31:10 +00:00
Mike Blumenkrantz e303898258 zink: manually validate shaders in debug builds
VVL is great, but there's actually cases where it doesn't catch critical
spirv errors, so add in our own validation pass to make sure things are
okay

this is especially useful for running on nvidia, as their compiler will
either crash on or silently drop illegal instructions

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16462>
2022-05-17 02:55:20 +00:00
Mike Blumenkrantz 8c8e6e953f spirv: fix barrier scope assert
glslang generates barriers with QueueFamily, so this is totally legal

cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16462>
2022-05-17 02:55:20 +00:00
Mike Blumenkrantz 5f83571f92 lavapipe: fix pipeline handling for dynamic render zs state with pipeline library
this is slightly more nuanced: if this is ONLY a fragment state,
pDepthStencilState must exist, but if it's BOTH fragment and output,
then pDepthStencilState must only exist if zs attachment is used

Fixes: d4d5a7abba ("lavapipe: implement EXT_graphics_pipeline_library")

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16457>
2022-05-17 02:44:01 +00:00
Mike Blumenkrantz 0b2d383316 lavapipe: ignore depth/stencil states if attachment is not present
depth and stencil states should only be set if the corresponding attachment
is present, otherwise they should be ignored. this is different from
ignoring the entire VkPipelineDepthStencilStateCreateInfo struct, as
it's possible that only depth or only stencil may be present

cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16457>
2022-05-17 02:44:01 +00:00
Timothy Arceri 77392e4983 vc4: disable GLSL IR loop unrolling
NIR loop unrolling is already enabled so just let it do its job.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16543>
2022-05-17 02:12:21 +00:00
Timothy Arceri b84e003079 r600: switch to NIR loop unrolling
Note the NIR unrolling code was already enabled but we bump the
iteration unroll count to match the GLSL IR limit as per the
comment about loop bugs.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16543>
2022-05-17 02:12:21 +00:00
Timothy Arceri dc2edb8f1d r300: disable GLSL IR loop unrolling
NIR loop unrolling is already enabled so just let it do its job.

Reviewed-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16543>
2022-05-17 02:12:21 +00:00
Timothy Arceri 1663b04592 i915g: switch to NIR loop unrolling
Shader-db stats:

total instructions in shared programs: 406749 -> 406890 (0.03%)
instructions in affected programs: 216 -> 357 (65.28%)
total tex_indirect in shared programs: 12666 -> 12671 (0.04%)
tex_indirect in affected programs: 29 -> 34 (17.24%)
total temps in shared programs: 23447 -> 23451 (0.02%)
temps in affected programs: 296 -> 300 (1.35%)
total const in shared programs: 59400 -> 59455 (0.09%)
const in affected programs: 50 -> 105 (110.00%)
LOST:   0
GAINED: 17

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16543>
2022-05-17 02:12:21 +00:00
Timothy Arceri 11637f516c etnaviv: switch to NIR loop unrolling
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16543>
2022-05-17 02:12:21 +00:00
Timothy Arceri 2a2a2e58d1 d3d12: switch to NIR loop unrolling
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16543>
2022-05-17 02:12:21 +00:00
Timothy Arceri c4295816af asahi: switch to NIR loop unrolling
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16543>
2022-05-17 02:12:21 +00:00
Timothy Arceri 3ceaf589d6 softpipe: switch to NIR loop unrolling
shader-db results:

total instructions in shared programs: 2788746 -> 2788886 (<.01%)
instructions in affected programs: 2126 -> 2266 (6.59%)
total loops in shared programs: 1357 -> 892 (-34.27%)
loops in affected programs: 468 -> 3 (-99.36%)
total temps in shared programs: 288754 -> 288725 (-0.01%)
temps in affected programs: 1623 -> 1594 (-1.79%)
total const in shared programs: 1954525 -> 1954621 (<.01%)
const in affected programs: 207 -> 303 (46.38%)
total imm in shared programs: 101023 -> 100891 (-0.13%)
imm in affected programs: 198 -> 66 (-66.67%)

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16543>
2022-05-17 02:12:21 +00:00
Timothy Arceri 643774cdab i915g: use a valid setting for force_indirect_unrolling
Otherwise we can hit asserts for example nir_deref_mode_must_be()
asserts on !(modes & ~nir_var_all)

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16543>
2022-05-17 02:12:21 +00:00
Timothy Arceri 792c9a0a24 glsl: move validation of sampler indirects to the nir linker
This will allow us to disable the GLSL IR loop unroller in a
following patch and rely on the NIR loop unroller instead.

This allows the piglit test spec@!opengl 2.0@max-samplers border
to pass on the v3d rpi4 driver.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16543>
2022-05-17 02:12:21 +00:00
Timothy Arceri d7a071a28f gallium/drivers: set force_indirect_unrolling_sampler for all required drivers
This is set to true for all drivers that have a GLSL level
of support lower than 4.00. This matches the rule for setting the
GLSL IR option EmitNoIndirectSampler.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16543>
2022-05-17 02:12:21 +00:00
Timothy Arceri ff8ddcb23e nir: add support for forced sampler indirect loop unrolling
Some drivers don't support these indirects and therefore require
loop unrolling if a shader uses a loop induction variable to
access a sampler array.

Here we add a new nir shader compiler option that drivers can set,
this will be the equivalent of the EmitNoIndirectSampler setting
used in the GLSL IR unrolling pass.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16543>
2022-05-17 02:12:21 +00:00
Chia-I Wu cb50fe7110 ir3: fix mem_ctx for ir3_disasm_info::nir
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6494
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16535>
2022-05-16 22:09:13 +00:00
Jason Ekstrand 9e22e2ac88 panvk: Lower blending after lower_var_copies
nir_lower_blend needs store_deref as does
io_arrays_to_elements_no_indirects.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16483>
2022-05-16 21:43:47 +00:00
Jason Ekstrand 4050697a8f panvk: So more nir_lower_tex before descriptor lowering
Some texture lowering generates more txs which means it needs to happen
before we lower descriptors because descriptor lowering is where txs is
actually handled in panvk.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16483>
2022-05-16 21:43:47 +00:00
Jason Ekstrand 36bb62139e bifrost: Run nir_lower_global_vars_to_local before nir_lower_vars_to_scratch
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16483>
2022-05-16 21:43:47 +00:00
Chia-I Wu d3d34ad476 turnip: emit VPC_SO_DISABLE in xfb begin/end
SO was always enabled before this change.  That meant, after a call to
tu_CmdBindTransformFeedbackBuffersEXT to emit VPC_SO_BUFFER_SIZE, any
draw call (from the same render pass, in a different render pass, or in
a different cmdbuf) could potentially cause writes to the SO buffers
regardless of whether the draw is inside xfb begin/end or not.

I choose to emit VPC_SO_DISABLE instead of using stateobjs like
freedreno does only because it is simpler.  It is not clear to me which
is more efficient to HW.

This also fixes double SO writes for gmem rendering.  While
tu6_tile_render_begin was careful to disable SO for the draw pass,
tu6_emit_tile_select re-enabled it.

dEQP-VK.transform_feedback.* still passes.  It fixes
dEQP-GLES3.functional.transform_feedback.* on angle.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16502>
2022-05-16 20:46:59 +00:00
Chia-I Wu 0b7751babf turnip: fix sampledImageIntegerSampleCounts
It seems fine to advertise msaa in sampledImageIntegerSampleCounts.

dEQP-VK.rasterization.rasterization_order_attachment_access.format_integer.*
goes from NotSupported to Pass for more test cases.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16487>
2022-05-16 19:26:46 +00:00
Yonggang Luo 622c6d3e9a radv: Add macros for win32 that accessed
Fixes: 3e85a0c90b ("ac/surface: define gfx11 modifiers")

../../src/amd/common/ac_surface.c: In function 'ac_get_supported_modifiers':
../../src/amd/common/ac_surface.c:421:47: error: 'AMD_FMT_MOD_TILE_GFX11_256K_R_X' undeclared (first use in this function); did you mean 'AMD_FMT_MOD_TILE_GFX9_64K_R_X'?
  421 |       unsigned swizzle_r_x = num_pipes > 16 ? AMD_FMT_MOD_TILE_GFX11_256K_R_X :
      |                                               ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
      |                                               AMD_FMT_MOD_TILE_GFX9_64K_R_X
../../src/amd/common/ac_surface.c:421:47: note: each undeclared identifier is reported only once for each function it appears in
In file included from ../../src/amd/common/ac_surface.c:31:
../../src/amd/common/ac_surface.c:424:61: error: 'AMD_FMT_MOD_TILE_VER_GFX11' undeclared (first use in this function); did you mean 'AMD_FMT_MOD_TILE_VER_GFX10'?
  424 |                               AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX11) |
      |                                                             ^~~~~~~~~~~~~~~~~~~~~~~~~~
../../src/amd/common/ac_drm_fourcc.h:75:21: note: in definition of macro 'AMD_FMT_MOD_SET'
   75 |         ((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT)
      |                     ^~~~~

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Erik Faye-Lund <erik.faye-lund@collabora.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16373>
2022-05-16 18:57:06 +00:00
Yonggang Luo a2aabb1812 radv: Add losing member hw_ip_version_major and hw_ip_version_minor for win32
Fixes: b261ac1ab5 ("ac/gpu_info: print all IP versions reported by the kernel")

```
 ../../src/amd/common/ac_gpu_info.c
../../src/amd/common/ac_gpu_info.c: In function 'ac_query_gpu_info':
../../src/amd/common/ac_gpu_info.c:545:44: error: 'struct drm_amdgpu_info_hw_ip' has no member named 'hw_ip_version_major'
  545 |       info->ip[ip_type].ver_major = ip_info.hw_ip_version_major;
      |                                            ^
../../src/amd/common/ac_gpu_info.c:546:44: error: 'struct drm_amdgpu_info_hw_ip' has no member named 'hw_ip_version_minor'
  546 |       info->ip[ip_type].ver_minor = ip_info.hw_ip_version_minor;
      |                                            ^
```

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Erik Faye-Lund <erik.faye-lund@collabora.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16373>
2022-05-16 18:57:06 +00:00
Yonggang Luo 679ad0905b radv: Fixes compiling error with msvc
Fixes: 11c28d9798 ("ac: add ac_nir_optimize_outputs, a NIR version of ac_optimize_vs_outputs")
```
FAILED: src/amd/common/libamd_common.a.p/ac_nir_opt_outputs.c.obj
"cl" "-Isrc\amd\common\libamd_common.a.p" "-Isrc\amd\common" "-I..\mesa\src\amd\common" "-Iinclude" "-I..\mesa\include" "-Isrc" "-I..\mesa\src" "-Isrc\mapi" "-I..\mesa\src\mapi" "-Isrc\mesa" "-I..\mesa\src\mesa" "-I..\mesa\src\gallium\include" "-Isrc\gallium\auxiliary" "-I..\mesa\src\gallium\auxiliary" "-Isrc\compiler" "-I..\mesa\src\compiler" "-Isrc\amd" "-I..\mesa\src\amd" "-I..\mesa\subprojects\libelf-lfg-win32-1.1.0-freebsd-12.1.0\contrib\elftoolchain\common" "-I..\mesa\subprojects\libelf-lfg-win32-1.1.0-freebsd-12.1.0\contrib\elftoolchain\libelf" "-I..\mesa\subprojects\libelf-lfg-win32-1.1.0-freebsd-12.1.0\sys" "-Isrc\util" "-I..\mesa\src\util" "-Isubprojects\zlib-1.2.11" "-I..\mesa\subprojects\zlib-1.2.11" "-Isrc\compiler\nir" "-I..\mesa\src\compiler\nir" "/MT" "/nologo" "/showIncludes" "/utf-8" "/W3" "/WX" "/std:c11" "/O2" "/Gw" "-D__STDC_CONSTANT_MACROS" "-D__STDC_FORMAT_MACROS" "-D__STDC_LIMIT_MACROS" "-DPACKAGE_VERSION=\"22.2.0-devel\"" "-DPACKAGE_BUGREPORT=\"https://gitlab.freedesktop.org/mesa/mesa/-/issues\"" "-DHAVE_SWRAST" "-DHAVE_D3D12" "-DHAVE_ZINK" "-DVIDEO_CODEC_VC1DEC=0" "-DVIDEO_CODEC_H264DEC=0" "-DVIDEO_CODEC_H264ENC=0" "-DVIDEO_CODEC_H265DEC=0" "-DVIDEO_CODEC_H265ENC=0" "-DHAVE_WINDOWS_PLATFORM" "-DHAVE_SURFACELESS_PLATFORM" "-DUSE_ELF_TLS" "-DUSE_TLS_BEHIND_FUNCTIONS" "-DENABLE_ST_OMX_BELLAGIO=0" "-DENABLE_ST_OMX_TIZONIA=0" "-DEGL_NO_X11" "-D_WINDOWS" "-D_WIN32_WINNT=0x0A00" "-DWINVER=0x0A00" "-DPIPE_SUBSYSTEM_WINDOWS_USER" "-D_USE_MATH_DEFINES" "-DVC_EXTRALEAN" "-D_CRT_SECURE_NO_WARNINGS" "-D_CRT_SECURE_NO_DEPRECATE" "-D_SCL_SECURE_NO_WARNINGS" "-D_SCL_SECURE_NO_DEPRECATE" "-D_ALLOW_KEYWORD_MACROS" "-D_HAS_EXCEPTIONS=0" "-DNOMINMAX" "-DMISSING_64BIT_ATOMICS" "-DHAVE_STRTOF" "-DHAVE_TIMESPEC_GET" "-DHAVE_QSORT_S" "-DHAVE_STRUCT_TIMESPEC" "-DHAVE_ZLIB" "-DHAVE_COMPRESSION" "-DLLVM_AVAILABLE" "-DMESA_LLVM_VERSION_STRING=\"12.0.1\"" "-DLLVM_IS_SHARED=0" "-DDRAW_LLVM_AVAILABLE" "-DMESA_EXECMEM" "-DVK_USE_PLATFORM_WIN32_KHR" "/wd4018" "/wd4056" "/wd4244" "/wd4267" "/wd4305" "/wd4351" "/wd4756" "/wd4800" "/wd4996" "/wd4291" "/wd4146" "/wd4200" "/wd4624" "/wd4309" "/wd4838" "/wd5105" "/we4020" "/we4024" "/Zc:__cplusplus" "-DADDR_FASTCALL=" "/Fdsrc\amd\common\libamd_common.a.p\ac_nir_opt_outputs.c.pdb" /Fosrc/amd/common/libamd_common.a.p/ac_nir_opt_outputs.c.obj "/c" ../mesa/src/amd/common/ac_nir_opt_outputs.c
../mesa/src/amd/common/ac_nir_opt_outputs.c(256): error C2059: syntax error: '}'
[23/987] Compiling C object src/compiler/nir/libnir.a.p/nir_opt_preamble.c.obj
```

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Erik Faye-Lund <erik.faye-lund@collabora.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16373>
2022-05-16 18:57:06 +00:00
Yonggang Luo e8d8a0544d radv: fixes msvc compiling error
Fixes: 5d9ef0efb5 ("radv: Add the fuchsia radix sort")

../mesa/src/amd/vulkan/radix_sort/radv_radix_sort.c(148): error C2220: the following warning is treated as an error
../mesa/src/amd/vulkan/radix_sort/radv_radix_sort.c(148): warning C4098: 'vkDestroyPipeline': 'void' function returning a value
[82/1129] Compiling C++ object src/amd/compiler/libaco.a.p/aco_instruction_selection.cpp.obj

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Erik Faye-Lund <erik.faye-lund@collabora.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16373>
2022-05-16 18:57:06 +00:00
Yonggang Luo 9baaf055e2 llvmpipe: Do not use _Atomic keyword that doesn't support by MSVC
Fixes: 3269d34b29 ("llvmpipe/fence: make the fence id counter atomic")

Fixes:
```
../mesa/src/gallium/drivers/llvmpipe/lp_fence.c
../mesa/src/gallium/drivers/llvmpipe/lp_fence.c(47): error C2143: syntax error: missing ';' before 'type'
```

fence_id initialized to 0

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Erik Faye-Lund <erik.faye-lund@collabora.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16373>
2022-05-16 18:57:06 +00:00
Erik Faye-Lund 57b353ec6a vulkan/wsi: unbreak win32-support
There's no unistd.h on Windows, let's not include it unconditionally.

But we also don't want to deal with DRM modifiers or DMABUFs on Windows,
so let's also ifdef out the rest of that stuff.

Fixes: a8b009aed6 ("vulkan/wsi: fix missing unistd include")
Fixes: c72ff19a9e ("vulkan/wsi: Close file descriptors in wsi_destroy_image")

Reviewed-By: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16373>
2022-05-16 18:57:06 +00:00
Ian Romanick 5c90eb1c53 glsl: Delete lower_extracts code
The single caller of this function (in st_glsl_to_ir.cpp) always passes
false, so this is dead code.

v2: Delete convert_vec_index_to_cond_assign method because all the
callers are deleted too.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16440>
2022-05-16 16:06:01 +00:00
Ian Romanick bd665fdd7f nir: Use nir_vector_extract to generate code for ir_binop_vector_extract
Tiger Lake and Ice Lake had similar results. (Ice Lake shown)
total cycles in shared programs: 861153442 -> 861153533 (<.01%)
cycles in affected programs: 14748 -> 14839 (0.62%)
helped: 5
HURT: 10
helped stats (abs) min: 1 max: 2 x̄: 1.80 x̃: 2
helped stats (rel) min: 0.09% max: 0.18% x̄: 0.16% x̃: 0.17%
HURT stats (abs)   min: 2 max: 18 x̄: 10.00 x̃: 10
HURT stats (rel)   min: 0.17% max: 1.54% x̄: 1.06% x̃: 1.24%
95% mean confidence interval for cycles value: 1.15 10.99
95% mean confidence interval for cycles %-change: 0.25% 1.07%
Cycles are HURT.

Skylake and Broadwell had similar results. (Skylake shown)
total cycles in shared programs: 844405063 -> 844405073 (<.01%)
cycles in affected programs: 1710 -> 1720 (0.58%)
helped: 0
HURT: 4
HURT stats (abs)   min: 2 max: 4 x̄: 2.50 x̃: 2
HURT stats (rel)   min: 0.35% max: 1.16% x̄: 0.88% x̃: 1.00%
95% mean confidence interval for cycles value: 0.91 4.09
95% mean confidence interval for cycles %-change: 0.30% 1.45%
Cycles are HURT.

Haswell and all earlier Intel GPUs had similar results. (Haswell shown)
total instructions in shared programs: 16710016 -> 16709769 (<.01%)
instructions in affected programs: 5842 -> 5595 (-4.23%)
helped: 64
HURT: 0
helped stats (abs) min: 3 max: 4 x̄: 3.86 x̃: 4
helped stats (rel) min: 3.36% max: 7.69% x̄: 4.52% x̃: 4.17%
95% mean confidence interval for instructions value: -3.95 -3.77
95% mean confidence interval for instructions %-change: -4.83% -4.22%
Instructions are helped.

total cycles in shared programs: 881088472 -> 881086722 (<.01%)
cycles in affected programs: 68696 -> 66946 (-2.55%)
helped: 58
HURT: 6
helped stats (abs) min: 10 max: 202 x̄: 36.41 x̃: 18
helped stats (rel) min: 0.81% max: 16.42% x̄: 4.15% x̃: 1.51%
HURT stats (abs)   min: 2 max: 88 x̄: 60.33 x̃: 68
HURT stats (rel)   min: 0.17% max: 7.06% x̄: 4.94% x̃: 5.60%
95% mean confidence interval for cycles value: -42.14 -12.54
95% mean confidence interval for cycles %-change: -4.66% -1.94%
Cycles are helped.

No fossil-db changes on any Intel platform.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16440>
2022-05-16 16:06:01 +00:00
Ian Romanick e944a98826 glsl: Add flag to disable part of do_vec_index_to_cond_assign
As of ca63a5ed3e ("glsl: fix interpolateAtXxx(some_vec[idx], ...)  with
dynamic idx"), this lowering pass does two things.  It converts
ir_binop_vector_extract to an if-ladder to select the dynamically
indexed component, and it extracts a ir_binop_vector_extract from the
source of an interpolateAt function and applies to the result instead.

This change adds a flag to disable the former behavior.  The latter is
still useful, but NIR has better (and soon even better) ways of doing
the former.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16440>
2022-05-16 16:06:01 +00:00
Ian Romanick 4eff1e6481 glsl: Fix mixed tabs and spaces in lower_mat_op_to_vec.cpp
This was originally part of a series that made other changes to this
file, but all of those changes got dropped.  Since the typing was
already done, there's no reason to not fix the formatting.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16440>
2022-05-16 16:06:01 +00:00
Gert Wollny 3749a6ecd2 nir: honor lower_double options for ffloor and ffract
v2: Don't lower ffloor@64 to ffract@64 when both ops are
    to be lowered. Settle on ffloor in opt_algebraic because
    in can be lowered to other ops in lower_double_ops.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>(v1)
Jason Ekstrand <jason.ekstrand@collabora.com> (v1)

Reviewed-by: Emma Anholt <emma@anholt.net> (v1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16431>
2022-05-16 15:03:05 +00:00
Timothy Arceri 9b14636876 glsl: simplify finding cursor in varying packing code
This is simpler and also avoids an assert() when the last
block is empty.

Fixes: e3a45a4778 ("glsl: implement lower_packed_varyings() as a NIR pass")

Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16527>
2022-05-16 14:40:14 +00:00
Timur Kristóf e0bec58340 radv: Fix loading task shader ring buffer addresses.
I forgot to use task_ring_offsets instead of ring_offsets
when I ported this code to the new ABI.

Fixes: a8bdcf3c92
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16500>
2022-05-16 15:28:20 +02:00