Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reworks:
* Fix mesa/mesamaster typo to mesa/mesa main (anholt)
* Use $CI_DEFAULT_BRANCH (eric_engestrom)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
It seems building the doxygen docs has bit-rotted over time, and now
generates a set of empty modules, apart from some basic descriptions.
Since Mesa is mostly implementing externally documented APIs, I don't
think it makes a whole lot of sense trying to fix this, and I think the
presence of these files might confuse users who try them out.
So let's just get rid of this.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10611>
I think between the disk cache unit tests and testing that we can really
serialize/deserialize NIR, this covers what I cared about for testing disk
caching.
Closes: #3597
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10629>
We don't support major 1.2 required extensions like timeline semaphores.
Fixes many complaints in the dEQP-VK.info.vulkan1p2.* group.
We were originally bumped to 1.2 in 75755e0eba ("turnip: Pretend to
support Vulkan 1.2") but hopefully that build issue has been fixed in the
entrypoint reworks since then.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10471>
Gallium wants the depth or stencil component replicated on all .XYZW.
That's easily done on pre-v7 since we can forge all the swizzles we
want, but Bifrost v7 only supports a few combinations, so we have to
combine the user swizzle with our own 'replicate' swizzle to make it
work. Note that v7 has a trick to make border color work when the GRBA
order is chosen: they apply the red border color to the green component.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10612>
In particular, this gives us B8G8R8A8_UNORM storage support which is
useful for writing WSI images from compute shaders. These formats can
only be accessed in a spec-compliant way by decorating the variable
NonReadable in the SPIR-V (writeonly in GLSL). If the client doesn't so
decorate the variable, it'll get the null surface state where reads
return 0 and writes are ignored.
Tested-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10624>
When I last time fixed this, I missed that continuing here would make us
leak pointers in the translate state, which is what made this avoid a
crash in the first place.
That's not great, we need to set *some* pointer in this case. The
obvious option would be NULL, but that means that the translate-code
also needs to support NULL-pointers here.
Instead, let's point to a small, static buffer that contains enough
zero-data for the largest possible vertex attribute. This avoids having
to add more NULL-checks.
Fixes: a8e8204b18 ("gallium/u_vbuf: support NULL-resources")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7773>
The pitch of the chroma plane isn't necessarily half that of the
luma plane, as tiling (and presumably even linear) swizzle modes
apply some alignment.
Fixes: 35e25ea1d0 ("ac/surface: allow non-DCC modifiers for YUV on GFX9+")
Reviewed-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10638>
No handling of Acquire/Release because at the moment scheduler
works as if any barrier is Acq+Rel.
Instead of removing scoped_barrier with scope/mode that for TCS
corresponds to a control_barrier or a memory_barrier_tcs_patch in
ir3_nir_lower_tess_ctrl - remove them in emit_intrinsic_barrier.
And do the same for memory_barrier_tcs_patch and control_barrier.
While in any case hw fence/barrier shouldn't be emitted for them,
they still affect ordering of stores, and in feature ir3 backend
may want to have that information.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9054>
nir_intrinsic_memory_barrier has the same semantic as memoryBarrier()
in GLSL, which is:
GLSL 4.60, 4.10. "Memory Qualifiers":
"The built-in function memoryBarrier() can be used if needed to
guarantee the completion and relative ordering of memory accesses
performed by a single shader invocation."
GLSL 4.60, 8.17. "Shader Memory Control Functions":
"The built-in functions memoryBarrier() and groupMemoryBarrier() wait
for the completion of accesses to all of the above variable types."
Fixes tests:
dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.device.payload_local.image.guard_nonlocal.workgroup.comp
dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.device.payload_nonlocal.workgroup.guard_local.image.comp
Fixes: 819a613a ("freedreno/ir3: moar better scheduler")
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9054>
The build-finished event is also triggered when there's an error. I
somehow got the second argument wrong, and ended up ignoring the case.
This can lead to new exceptions being thrown due to missing files, that
ends up hiding the real problem.
Fixes: 64a4ba9e1c ("docs: add an extension to generate redirects")
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10407>
There's no longer any code reading this, so let's get rid of it. It
always rubbed me a bit the wrong way, because this repeated some
information already present in the context.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10371>
This is required for a bunch of stuff that can occur in any Vulkan
shader stage, not just these few. So let's always emit this cap.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10371>
internal_usage is the memory allocated by the current process (intent)
while system_usage is the memory allocated globally (actual).
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9774>
The pointers won't be used at that point. Just decrement the refcounts.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.eric.pelloux-prayer@amd.com>
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10606>
A lot of space was wasted due to 16-byte alignment for slots. This new
layout tries to match glthread. Highlights:
- the slot size changed to 8 bytes (was 16), so less padding
- the header size changed to 4 bytes (was 8), so some calls can use
the remaining 4 bytes in the slot for parameters
- draw merging merges up to 307 draws (was 256) due to space savings
- parameters in structures are sorted based on implicit type alignment
(uint8_t first, pointers last) to make it easier to utilize the 4 bytes
after the header and to remove holes
- some structures use smaller types for parameters than pipe_context where
it's safe (e.g. clear uses float instead of double for depth)
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.eric.pelloux-prayer@amd.com>
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10606>
This reverts commit 3b1ce49bc1.
It will be completely rewritten, but let's revert this first.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.eric.pelloux-prayer@amd.com>
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10606>
Not that Z32F is especially common, but we shouldn't consider it to
imply that the color buffers are also float, which is what floatMode
is meant to mean.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10491>
The blitter commands don't show up in INTEL_DEBUG=bat, but on
gen4/5 they are emitted on the render engine ring so just change
the XML to reflect that.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10636>
MI_LOAD_REGISTER_MEM is only available on gen7+, so avoid build errors
on earlier generations.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10636>
sparse buffers are not cpu-readable, so any mapping requires that they
use a staging buffer, either the stream uploader for writes or a manual
copy for readback
future work here should attempt to resolve two perf issues:
* sparse allocations should be allocated dynamically using a suballocator
or some other, more useful strategy
* readback shouldn't allocate a huge staging buffer
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10509>
Jordan Justen
Erik Faye-Lund
Emma Anholt
Eric Anholt
Yiwei Zhang
Mike Blumenkrantz
Boris Brezillon
Mauro Rossi
Jason Ekstrand
Lionel Landwerlin
Bas Nieuwenhuizen
Danylo Piliaiev
Dave Airlie
Dave Airlie
Samuel Pitoiset
Marek Olšák
Adam Jackson
Ilia Mirkin