Commit Graph

107224 Commits

Author SHA1 Message Date
Marek Olšák 1e85cfb91a meson: drop the xcb-xrandr version requirement
autotools doesn't have any requirement. This fixes meson on Ubuntu 16.04.

Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
2019-02-03 18:39:57 -05:00
Eric Engestrom 808bf59cac wsi/display: add comment
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Keith Packard <keithp@keithp.com>
2019-02-02 23:08:03 +00:00
Jason Ekstrand 0aa5a97b03 relnotes: Add VK_EXT_buffer_device_address 2019-02-02 08:42:14 -06:00
Jason Ekstrand 48ed2a7bb0 anv: Implement VK_EXT_buffer_device_address
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-02-01 17:09:42 -06:00
Jason Ekstrand e644ed468f intel/fs: Implement nir_intrinsic_global_atomic_*
eviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-02-01 16:11:00 -06:00
Jason Ekstrand a91f392073 intel/fs: Use SENDS for A64 writes on gen9+
eviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-02-01 16:11:00 -06:00
Jason Ekstrand 1c25bf4373 intel/fs: Implement load/store_global with A64 untyped messages
eviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-02-01 16:11:00 -06:00
Jason Ekstrand b4f0d062cd intel/fs: Do the grf127 hack on SIMD8 instructions in SIMD16 mode
Previously, we only applied the fix to shaders with a dispatch mode of
SIMD8 but the code it relies on for SIMD16 mode only applies to SIMD16
instructions.  If you have a SIMD8 instruction in a SIMD16 shader,
neither would trigger and the restriction could still be hit.

Fixes: 232ed89802 "i965/fs: Register allocator shoudn't use grf127..."
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-02-01 16:11:00 -06:00
Jason Ekstrand 79724a0756 intel/fs: Properly handle 64-bit types in LOAD_PAYLOAD
By just assigning dst.type to src[i].type, we ensure that the offset at
the end of the loop actually offsets it by the right number of
registers.  Otherwise, we'll get into a case where we copy with a Q type
and then offset with a D type and things get out of sync.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-02-01 16:10:57 -06:00
Jason Ekstrand f02914a991 intel/fs/cse: Split create_copy_instr into three cases
Previously, we tried to combine all cases where the instruction being
CSE'd writes to more than one MOV worth of registers into one case with
a bit of special casing for LOAD_PAYLOAD.  This commit splits things so
that LOAD_PAYLOAD is entirely it's own case.  This makes tweaking the
LOAD_PAYLOAD case simpler in the next commit.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-02-01 16:10:40 -06:00
Jason Ekstrand f409a08e5f intel/nir: Add global support to lower_mem_access_bit_sizes
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-02-01 16:08:29 -06:00
Oscar Blumberg fea5b8e5ad intel/fs: Fix memory corruption when compiling a CS
Missing check for shader stage in the fs_visitor would corrupt the
cs_prog_data.push information and trigger crashes / corruption later
when uploading the CS state.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-02-01 10:53:33 -08:00
Jason Ekstrand ab940b0d97 spirv: Support LocalSizeId and LocalSizeHintId execution modes
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-02-01 17:34:02 +00:00
Jason Ekstrand 7223590c42 spirv: Handle OpExecutionModeId
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-02-01 17:34:02 +00:00
Jason Ekstrand e68871f6a4 spirv: Handle constants and types before execution modes
We already defer handling the actual execution modes until after we've
created the shader.  This just moves it a tiny bit further so we
actually have constants and types and can handle OpExecutionModeId.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-02-01 17:34:02 +00:00
Jason Ekstrand 7d862ef530 spirv: Rework handling of spec constant workgroup size built-ins
Instead of handling it as part of the handling of constant instructions,
just stash the vtn_value when we see the decoration and handle it
explicitly later.  This will let us re-order handling of constant
instructions without breaking the Vulkan SPIR-V requirement that
decorating a specialization constant as the WorkgroupSize built-in
overrides the workgroup size set as an execution mode.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-02-01 17:34:02 +00:00
Jason Ekstrand 9b37e93e42 spirv: Replace vtn_constant_value with vtn_constant_uint
The uint version is less typing, supports different bit sizes, and is
probably a bit more safe because we're actually verifying that the
SPIR-V value is an integer scalar constant.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-02-01 17:34:02 +00:00
Samuel Pitoiset 5e7f800f32 radv: fix build
Fixes: 9b9ccee4d6 ("radv: take LDS into account for compute shader occupancy stats")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-02-01 15:31:55 +01:00
Timothy Arceri 9b9ccee4d6 radv: take LDS into account for compute shader occupancy stats
Ported from d205faeb6c.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-02-01 22:25:30 +11:00
Timothy Arceri a53d68d318 ac/radv/radeonsi: add ac_get_num_physical_sgprs() helper
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-02-01 22:25:30 +11:00
Gurchetan Singh 574186f0e8 docs: add GL_EXT_texture_compression_s3tc_srgb to release notes
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2019-02-01 10:01:59 +00:00
Gurchetan Singh dc9a15aefb st/mesa: expose EXT_texture_compression_s3tc_srgb
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
2019-02-01 10:01:59 +00:00
Gurchetan Singh a2ab400719 i965: Set flag for EXT_texture_compression_s3tc_srgb
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2019-02-01 10:01:59 +00:00
Gurchetan Singh db24132d80 mesa/main: Expose EXT_texture_compression_s3tc_srgb
Required for the following test:

bin/compressedteximage GL_COMPRESSED_SRGB_ALPHA_S3TC_DXT1_EXT

pass when emulating GL on GLES.

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
2019-02-01 10:01:59 +00:00
Timothy Arceri 0f3a8e1b64 st/glsl_to_nir: remove dead local variables
Without this we do not end up with a deterministic NIR because
temporary register variables are added in random order. NIR must
be deterministic because we use it to produce a sha for the
radeonsi backends disk cache.

This fixes the shader cache for a bunch of shaders.

Another positive is that this results in a large reduction in the
size of the NIR that the state tracker stores to the disk cache.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-02-01 15:56:02 +11:00
Dylan Baker 4052142de7 meson: remove -std=c++11 from intel/tools
for meson all C++ code is already compiled as C++11, so it's
unnecessary. It's also the wrong way to do this, if we really needed
this the correct way is to set:

```meson
executable(
  ...
  override_options : ['cpp_std=c++11'],
)
```

Which ensures not only that the correct syntax for the current
compiler is used, but also that meson doesn't create arguments like
`-std=c++14 ... -std=c++11`

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-01-31 21:42:16 +00:00
Dylan Baker 8e49b32f63 meson: fix style in intel/tools
The `:` in options should always have one space before and after `foo
: bar`, and lists do not get spaces around the braces: `[foo]` not `[
foo ]`

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-01-31 21:42:16 +00:00
Dylan Baker d93d53fa72 meson: remove build_by_default : true
Which is and has always been the default. This is largely an artifact
of how the building of these tools was controlled when the meson build
was originally created.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-01-31 21:42:16 +00:00
Emil Velikov 1240c3cb10 docs: update calendar, add news item and link release notes for 18.3.3
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2019-01-31 21:17:38 +00:00
Emil Velikov 83160c6c05 docs: add sha256 checksums for 18.3.3
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 7475d7727f)
2019-01-31 21:15:20 +00:00
Emil Velikov 4d0732dc39 docs: add release notes for 18.3.3
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 190a79f462)
[Emil: drop VERSION hunk]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

 Conflicts:
	VERSION
2019-01-31 21:14:56 +00:00
Neha Bhende 69d736b17a st/mesa: Fix topogun-1.06-orc-84k-resize.trace crash
We need to initialize all fields in rs->prim explicitly while
creating new rastpos stage.

Fixes: bac8534267 ("st/mesa: allow glDrawElements to work with GL_SELECT
feedback")

v2: Initializing all fields in rs->prim as per Ilia.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2019-01-31 12:21:59 -07:00
Dylan Baker c812c740e6 android,autotools,i965: Fix location of float64_glsl.h
Android.mk and autotools disagree about where generated files should
go, which wasn't a problem until we wanted to build a dist
tarball. This corrects the problem by changing the output and include
paths to be the same on android and autotools (meson already has the
correct include path).

Fixes: 7d7b30835c
       ("automake: Fix path to generated source")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2019-01-31 19:04:30 +00:00
Marek Olšák d49c16a597 gallium: allow more PIPE_RESOURCE_ driver flags
radeonsi has 8 and will probably have 9 soon.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-01-31 13:10:42 -05:00
Eric Anholt ab4d5775b0 v3d: Fix image_load_store clamping of signed integer stores.
This was copy-and-paste fail, that oddly showed up in the CTS's
reinterprets of r32f, rgba8, and srgba8 to rgba8i, but not r32ui and r32i
to rgba8i or reinterprets to other signed int formats.

Fixes: 6281f26f06 ("v3d: Add support for shader_image_load_store.")
2019-01-31 08:39:40 -08:00
Eric Anholt db2ae51121 mesa: Skip partial InvalidateFramebuffer of packed depth/stencil.
One of the CTS cases tries to invalidate just stencil of packed
depth/stencil, and we incorrectly lost the depth contents.

Fixes dEQP-GLES3.functional.fbo.invalidate.whole.unbind_read_stencil
Fixes: 0c42b5f3cb ("mesa: wire up InvalidateFramebuffer")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-01-31 08:37:46 -08:00
Rob Clark 39cfdf9930 freedreno: more fixing release tarball
Fixes: aa0fed10d3 freedreno: move ir3 to common location
Signed-off-by: Rob Clark <robdclark@gmail.com>
2019-01-31 09:59:18 -05:00
Rob Clark e252656d14 freedreno: fix release tarball
Fixes: b4476138d5 freedreno: move drm to common location
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Signed-off-by: Rob Clark <robdclark@gmail.com>
2019-01-31 09:59:18 -05:00
Emmanuel Gil Peyrot 0d4dd59ae5 docs: make bugs.html easier to find
Thanks to Yann Kervran for the report and suggestions.

Signed-off-by: Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-01-31 14:31:48 +00:00
Dave Airlie 9279a28f07 virgl: ARB_query_buffer_object support
v1.1: fix size define.

Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-01-31 11:23:38 +10:00
Dave Airlie 38658c6d4d virgl: enable elapsed time queries
GL underneath always has GL_TIME_ELAPSED so always enable these.

Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-01-31 11:23:30 +10:00
Dylan Baker da48cba61e automake: Add --enable-autotools to distcheck flags
Fixes: e68777c87c
       ("autotools: Deprecate the use of autotools")
Reviewed-by: Matt Turner <mattst88@gmail.com>
2019-01-30 19:32:44 +00:00
Marek Olšák ffbd37d8e9 radeonsi: fix a comment typo in si_fine_fence_set 2019-01-30 14:32:05 -05:00
Marek Olšák f4eb746ef7 r600: add -Wstrict-overflow=0 to meson to silence the warning
same as radeonsi
2019-01-30 12:49:45 -05:00
Marek Olšák d50bef9831 winsys/amdgpu: remove amdgpu_drm.h definitions
trivial
2019-01-30 12:38:56 -05:00
Marek Olšák 16672f16da radeonsi: unify error paths in si_texture_create_object 2019-01-30 12:35:22 -05:00
Marek Olšák 2361558eb7 radeonsi: merge & rename texture BO metadata functions 2019-01-30 12:35:22 -05:00
Marek Olšák 1c12d56e4d radeonsi: enable dithered alpha-to-coverage for better quality
same as AMDVLK.

GL_NV_alpha_to_coverage_dither_control allows controlling this behavior.
The default is implementation-dependent.
2019-01-30 12:35:22 -05:00
Dylan Baker b4986d2e0c gallium: wrap u_screen in extern "C" for c++
Some drivers (notabily SWR) are written in C++, and as such they need
access to C headers with extern "C". So lets add that.
2019-01-30 15:12:27 +00:00
Gert Wollny 45903cddc3 mesa/core: Enable EXT_texture_sRGB_R8 also for desktop GL
As of Nov/30/2018 the extension is also valid for OpenGL >= 1.2, so
enable it accordingly and also add the required view class entry.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-01-30 11:32:40 +00:00