mirror of https://gitlab.freedesktop.org/mesa/mesa
etnaviv/nn: Pipe through input/accumulation buffer depth from hwdb
Stop hard coding accumulation buffer depth and input buffer depth to the values for VIPNano-QI. This is allows to calculate correct tile sizes for other cores. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Tomeu Vizoso <tomeu@tomeuvizoso.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28956>
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@ -92,6 +92,8 @@ struct etna_core_npu_info {
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unsigned on_chip_sram_size; /* Size of on-chip SRAM */
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unsigned axi_sram_size; /* Size of SRAM behind AXI */
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unsigned nn_zrl_bits; /* Number of bits for zero run-length compression */
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unsigned nn_input_buffer_depth; /* Input buffer size, determines tile size */
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unsigned nn_accum_buffer_depth; /* Accumulation buffer size, determines tile size */
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};
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struct etna_core_info {
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@ -112,6 +112,8 @@ etna_query_feature_db(struct etna_core_info *info)
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info->npu.on_chip_sram_size = db->VIP_SRAM_SIZE;
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info->npu.axi_sram_size = db->AXI_SRAM_SIZE;
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info->npu.nn_zrl_bits = db->NN_ZRL_BITS;
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info->npu.nn_accum_buffer_depth = db->NNAccumBufferDepth;
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info->npu.nn_input_buffer_depth = db->NNInputBufferDepth;
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}
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return true;
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@ -157,6 +157,10 @@ struct etna_specs {
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unsigned axi_sram_size;
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/* Number of bits for zero run-length compression */
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unsigned nn_zrl_bits;
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/* Input buffer size, determines tile size */
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unsigned nn_input_buffer_depth;
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/* Accumulation buffer size, determines tile size */
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unsigned nn_accum_buffer_depth;
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};
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/* Compiled Gallium state. All the different compiled state atoms are woven
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@ -510,20 +510,19 @@ etna_ml_lower_add(struct etna_ml_subgraph *subgraph,
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operation->weight_scale);
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}
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#define ACCUM_BUFFER_DEPTH 64
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#define INPUT_BUFFER_DEPTH 12
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#define MAX_TILE_WIDTH 64
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static unsigned
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calc_superblocks(struct etna_context *ctx, const struct etna_operation *operation, unsigned tile_y, unsigned interleave_mode)
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{
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unsigned nn_core_count = ctx->screen->specs.nn_core_count;
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unsigned nn_accum_buffer_depth = ctx->screen->specs.nn_accum_buffer_depth;
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unsigned output_channels = operation->addition ? 1 : operation->output_channels;
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unsigned kernels_per_core = DIV_ROUND_UP(output_channels, nn_core_count);
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unsigned foo = (ACCUM_BUFFER_DEPTH * interleave_mode) / tile_y;
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unsigned foo = (nn_accum_buffer_depth * interleave_mode) / tile_y;
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if (operation->weight_width == 1)
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foo = MIN2(foo, ACCUM_BUFFER_DEPTH / 3);
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foo = MIN2(foo, nn_accum_buffer_depth / 3);
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foo = MIN2(foo, kernels_per_core);
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foo = MIN2(foo, 127);
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@ -591,6 +590,8 @@ calc_addition_sizes(unsigned *input_width, unsigned *input_height, unsigned *inp
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static unsigned
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calculate_tiling(struct etna_context *ctx, const struct etna_operation *operation, unsigned *tile_width_out, unsigned *tile_height_out)
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{
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unsigned nn_input_buffer_depth = ctx->screen->specs.nn_input_buffer_depth;
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unsigned nn_accum_buffer_depth = ctx->screen->specs.nn_accum_buffer_depth;
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unsigned input_width = operation->input_width;
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unsigned input_height = operation->input_height;
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unsigned input_channels = operation->input_channels;
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@ -614,8 +615,8 @@ calculate_tiling(struct etna_context *ctx, const struct etna_operation *operatio
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tile_width = MIN2(output_width, 64);
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interleave_mode = calc_interleave_mode(tile_width, operation->weight_height);
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tile_height = INPUT_BUFFER_DEPTH * interleave_mode - operation->weight_height + 1;
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tile_height = MIN2(tile_height, interleave_mode * ACCUM_BUFFER_DEPTH);
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tile_height = nn_input_buffer_depth * interleave_mode - operation->weight_height + 1;
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tile_height = MIN2(tile_height, interleave_mode * nn_accum_buffer_depth);
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tile_height = MIN2(tile_height, output_height);
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if (operation->stride > 1 && tile_height % 2 > 0)
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@ -870,6 +870,8 @@ etna_get_specs(struct etna_screen *screen)
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screen->specs.on_chip_sram_size = info->npu.on_chip_sram_size;
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screen->specs.axi_sram_size = info->npu.axi_sram_size;
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screen->specs.nn_zrl_bits = info->npu.nn_zrl_bits;
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screen->specs.nn_input_buffer_depth = info->npu.nn_input_buffer_depth;
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screen->specs.nn_accum_buffer_depth = info->npu.nn_accum_buffer_depth;
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if (etna_core_has_feature(info, ETNA_FEATURE_NN_XYDP0))
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screen->specs.nn_core_version = 8;
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