mirror of https://gitlab.freedesktop.org/mesa/mesa
307 lines
11 KiB
C
307 lines
11 KiB
C
/*
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* Copyright (c) 2012-2015 Etnaviv Project
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sub license,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef H_ETNA_INTERNAL
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#define H_ETNA_INTERNAL
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#include <assert.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include "hw/common.xml.h"
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#include "hw/common_3d.xml.h"
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#include "hw/state.xml.h"
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#include "hw/state_3d.xml.h"
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#include "drm/etnaviv_drmif.h"
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#define ETNA_NUM_INPUTS (16)
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#define ETNA_NUM_VARYINGS 16
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#define ETNA_NUM_LOD (14)
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#define ETNA_NUM_LAYERS (6)
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#define ETNA_MAX_UNIFORMS (256)
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#define ETNA_MAX_CONST_BUF 16
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#define ETNA_MAX_PIXELPIPES 2
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/* All RS operations must have width%16 = 0 */
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#define ETNA_RS_WIDTH_MASK (16 - 1)
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/* RS tiled operations must have height%4 = 0 */
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#define ETNA_RS_HEIGHT_MASK (3)
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/* PE render targets must be aligned to 64 bytes */
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#define ETNA_PE_ALIGNMENT (64)
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/* These demarcate the margin (fixp16) between the computed sizes and the
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value sent to the chip. These have been set to the numbers used by the
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Vivante driver on gc2000. They used to be -1 for scissor right and bottom. I
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am not sure whether older hardware was relying on these or they were just a
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guess. But if so, these need to be moved to the _specs structure.
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*/
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#define ETNA_SE_SCISSOR_MARGIN_RIGHT (0x1119)
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#define ETNA_SE_SCISSOR_MARGIN_BOTTOM (0x1111)
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#define ETNA_SE_CLIP_MARGIN_RIGHT (0xffff)
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#define ETNA_SE_CLIP_MARGIN_BOTTOM (0xffff)
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/* GPU chip 3D specs */
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struct etna_specs {
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/* HALTI (gross architecture) level. -1 for pre-HALTI. */
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int halti : 8;
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/* supports SUPERTILE (64x64) tiling? */
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unsigned can_supertile : 1;
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/* needs z=(z+w)/2, for older GCxxx */
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unsigned vs_need_z_div : 1;
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/* supports trigonometric instructions */
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unsigned has_sin_cos_sqrt : 1;
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/* has SIGN/FLOOR/CEIL instructions */
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unsigned has_sign_floor_ceil : 1;
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/* can use VS_RANGE, PS_RANGE registers*/
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unsigned has_shader_range_registers : 1;
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/* has the new sin/cos/log functions */
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unsigned has_new_transcendentals : 1;
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/* has the new dp2/dpX_norm instructions, among others */
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unsigned has_halti2_instructions : 1;
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/* has no limit on the number of constant sources per instruction */
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unsigned has_no_oneconst_limit : 1;
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/* has V4_COMPRESSION */
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unsigned v4_compression : 1;
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/* supports single-buffer rendering with multiple pixel pipes */
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unsigned single_buffer : 1;
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/* has unified uniforms memory */
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unsigned has_unified_uniforms : 1;
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/* can load shader instructions from memory */
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unsigned has_icache : 1;
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/* ASTC texture support (and has associated states) */
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unsigned tex_astc : 1;
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/* has BLT engine instead of RS */
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unsigned use_blt : 1;
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/* can use any kind of wrapping mode on npot textures */
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unsigned npot_tex_any_wrap : 1;
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/* supports seamless cube map */
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unsigned seamless_cube_map : 1;
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/* number of bits per TS tile */
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unsigned bits_per_tile;
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/* clear value for TS (dependent on bits_per_tile) */
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uint32_t ts_clear_value;
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/* base of vertex texture units */
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unsigned vertex_sampler_offset;
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/* number of fragment sampler units */
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unsigned fragment_sampler_count;
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/* number of vertex sampler units */
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unsigned vertex_sampler_count;
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/* size of vertex shader output buffer */
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unsigned vertex_output_buffer_size;
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/* maximum number of vertex element configurations */
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unsigned vertex_max_elements;
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/* size of a cached vertex (?) */
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unsigned vertex_cache_size;
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/* number of shader cores */
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unsigned shader_core_count;
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/* number of vertex streams */
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unsigned stream_count;
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/* vertex shader memory address*/
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uint32_t vs_offset;
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/* pixel shader memory address*/
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uint32_t ps_offset;
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/* vertex shader uniforms address*/
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uint32_t vs_uniforms_offset;
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/* pixel shader uniforms address*/
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uint32_t ps_uniforms_offset;
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/* vertex/fragment shader max instructions */
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uint32_t max_instructions;
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/* maximum number of varyings */
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unsigned max_varyings;
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/* maximum number of registers */
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unsigned max_registers;
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/* maximum vertex uniforms */
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unsigned max_vs_uniforms;
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/* maximum pixel uniforms */
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unsigned max_ps_uniforms;
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/* maximum texture size */
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unsigned max_texture_size;
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/* maximum texture size */
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unsigned max_rendertarget_size;
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/* available pixel pipes */
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unsigned pixel_pipes;
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/* number of constants */
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unsigned num_constants;
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/* number of NN cores */
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unsigned nn_core_count;
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/* architecture version of NN cores */
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unsigned nn_core_version;
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/* number of MAD units per NN core */
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unsigned nn_mad_per_core;
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/* number of TP cores */
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unsigned tp_core_count;
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/* Size of on-chip SRAM */
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unsigned on_chip_sram_size;
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/* Size of SRAM behind AXI */
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unsigned axi_sram_size;
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/* Number of bits for zero run-length compression */
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unsigned nn_zrl_bits;
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/* Input buffer size, determines tile size */
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unsigned nn_input_buffer_depth;
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/* Accumulation buffer size, determines tile size */
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unsigned nn_accum_buffer_depth;
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};
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/* Compiled Gallium state. All the different compiled state atoms are woven
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* together and uploaded only when it is necessary to synchronize the state,
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* for example before rendering. */
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/* Compiled pipe_blend_color */
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struct compiled_blend_color {
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float color[4];
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uint32_t PE_ALPHA_BLEND_COLOR;
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uint32_t PE_ALPHA_COLOR_EXT0;
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uint32_t PE_ALPHA_COLOR_EXT1;
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};
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/* Compiled pipe_stencil_ref */
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struct compiled_stencil_ref {
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uint32_t PE_STENCIL_CONFIG[2];
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uint32_t PE_STENCIL_CONFIG_EXT[2];
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};
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/* Compiled pipe_viewport_state */
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struct compiled_viewport_state {
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uint32_t PA_VIEWPORT_SCALE_X;
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uint32_t PA_VIEWPORT_SCALE_Y;
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uint32_t PA_VIEWPORT_SCALE_Z;
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uint32_t PA_VIEWPORT_OFFSET_X;
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uint32_t PA_VIEWPORT_OFFSET_Y;
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uint32_t PA_VIEWPORT_OFFSET_Z;
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uint32_t SE_SCISSOR_LEFT;
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uint32_t SE_SCISSOR_TOP;
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uint32_t SE_SCISSOR_RIGHT;
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uint32_t SE_SCISSOR_BOTTOM;
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uint32_t PE_DEPTH_NEAR;
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uint32_t PE_DEPTH_FAR;
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};
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/* Compiled pipe_framebuffer_state */
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struct compiled_framebuffer_state {
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uint32_t GL_MULTI_SAMPLE_CONFIG;
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uint32_t PE_COLOR_FORMAT;
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uint32_t PE_DEPTH_CONFIG;
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struct etna_reloc PE_DEPTH_ADDR;
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struct etna_reloc PE_PIPE_DEPTH_ADDR[ETNA_MAX_PIXELPIPES];
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uint32_t PE_DEPTH_STRIDE;
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uint32_t PE_HDEPTH_CONTROL;
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uint32_t PE_DEPTH_NORMALIZE;
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struct etna_reloc PE_COLOR_ADDR;
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struct etna_reloc PE_PIPE_COLOR_ADDR[ETNA_MAX_PIXELPIPES];
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uint32_t PE_COLOR_STRIDE;
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uint32_t PE_MEM_CONFIG;
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uint32_t RA_MULTISAMPLE_UNK00E04;
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uint32_t RA_MULTISAMPLE_UNK00E10[VIVS_RA_MULTISAMPLE_UNK00E10__LEN];
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uint32_t RA_CENTROID_TABLE[VIVS_RA_CENTROID_TABLE__LEN];
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uint32_t TS_MEM_CONFIG;
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uint32_t TS_DEPTH_CLEAR_VALUE;
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struct etna_reloc TS_DEPTH_STATUS_BASE;
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struct etna_reloc TS_DEPTH_SURFACE_BASE;
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uint32_t TS_COLOR_CLEAR_VALUE;
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uint32_t TS_COLOR_CLEAR_VALUE_EXT;
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struct etna_reloc TS_COLOR_STATUS_BASE;
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struct etna_reloc TS_COLOR_SURFACE_BASE;
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uint32_t PE_LOGIC_OP;
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uint32_t PS_CONTROL;
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uint32_t PS_CONTROL_EXT;
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bool msaa_mode; /* adds input (and possible temp) to PS */
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};
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/* Compiled context->create_vertex_elements_state */
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struct compiled_vertex_elements_state {
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unsigned num_elements;
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uint32_t FE_VERTEX_ELEMENT_CONFIG[VIVS_FE_VERTEX_ELEMENT_CONFIG__LEN];
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uint32_t NFE_GENERIC_ATTRIB_CONFIG0[VIVS_NFE_GENERIC_ATTRIB__LEN];
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uint32_t NFE_GENERIC_ATTRIB_SCALE[VIVS_NFE_GENERIC_ATTRIB__LEN];
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uint32_t NFE_GENERIC_ATTRIB_CONFIG1[VIVS_NFE_GENERIC_ATTRIB__LEN];
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unsigned num_buffers;
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uint32_t NFE_VERTEX_STREAMS_VERTEX_DIVISOR[VIVS_NFE_VERTEX_STREAMS__LEN];
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uint32_t FE_VERTEX_STREAM_CONTROL[VIVS_NFE_VERTEX_STREAMS__LEN];
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};
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/* Compiled context->set_vertex_buffer result */
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struct compiled_set_vertex_buffer {
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struct etna_reloc FE_VERTEX_STREAM_BASE_ADDR;
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};
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/* Compiled linked VS+PS shader state */
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struct compiled_shader_state {
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uint32_t RA_CONTROL;
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uint32_t PA_ATTRIBUTE_ELEMENT_COUNT;
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uint32_t PA_CONFIG;
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uint32_t PA_SHADER_ATTRIBUTES[VIVS_PA_SHADER_ATTRIBUTES__LEN];
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uint32_t VS_END_PC;
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uint32_t VS_OUTPUT_COUNT; /* number of outputs if point size per vertex disabled */
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uint32_t VS_OUTPUT_COUNT_PSIZE; /* number of outputs of point size per vertex enabled */
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uint32_t VS_INPUT_COUNT;
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uint32_t VS_TEMP_REGISTER_CONTROL;
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uint32_t VS_OUTPUT[4];
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uint32_t VS_INPUT[4];
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uint32_t VS_LOAD_BALANCING;
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uint32_t VS_START_PC;
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uint32_t PS_END_PC;
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uint32_t PS_OUTPUT_REG;
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uint32_t PS_INPUT_COUNT;
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uint32_t PS_INPUT_COUNT_MSAA; /* Adds an input */
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uint32_t PS_TEMP_REGISTER_CONTROL;
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uint32_t PS_TEMP_REGISTER_CONTROL_MSAA; /* Adds a temporary if needed to make space for extra input */
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uint32_t PS_START_PC;
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uint32_t GL_VARYING_TOTAL_COMPONENTS;
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uint32_t GL_VARYING_NUM_COMPONENTS[2];
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uint32_t GL_VARYING_COMPONENT_USE[2];
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uint32_t GL_HALTI5_SH_SPECIALS;
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uint32_t FE_HALTI5_ID_CONFIG;
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unsigned vs_inst_mem_size;
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unsigned ps_inst_mem_size;
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uint32_t *VS_INST_MEM;
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uint32_t *PS_INST_MEM;
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struct etna_reloc PS_INST_ADDR;
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struct etna_reloc VS_INST_ADDR;
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unsigned writes_z:1;
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unsigned uses_discard:1;
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};
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/* Helpers to assist creating and setting bitarrays (eg, for varyings).
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* field_size must be a power of two, and <= 32. */
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#define DEFINE_ETNA_BITARRAY(name, num, field_size) \
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uint32_t name[(num) * (field_size) / 32]
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static inline void
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etna_bitarray_set(uint32_t *array, size_t array_size, size_t field_size,
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size_t index, uint32_t value)
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{
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size_t shift = (index * field_size) % 32;
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size_t offset = (index * field_size) / 32;
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assert(index < array_size * 32 / field_size);
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assert(value < 1 << field_size);
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array[offset] |= value << shift;
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}
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#define etna_bitarray_set(array, field_size, index, value) \
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etna_bitarray_set((array), ARRAY_SIZE(array), field_size, index, value)
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#endif
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