2017-10-20 17:35:48 +01:00
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/*
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* Copyright © 2017 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "nir_builder.h"
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2018-01-26 07:06:11 +00:00
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#include "util/format_rgb9e5.h"
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2017-10-20 17:35:48 +01:00
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static inline nir_ssa_def *
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2021-05-04 19:08:09 +01:00
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nir_shift_imm(nir_builder *b, nir_ssa_def *value, int left_shift)
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2017-10-20 17:35:48 +01:00
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{
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if (left_shift > 0)
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return nir_ishl(b, value, nir_imm_int(b, left_shift));
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else if (left_shift < 0)
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return nir_ushr(b, value, nir_imm_int(b, -left_shift));
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else
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return value;
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}
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2021-05-01 16:45:28 +01:00
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static inline nir_ssa_def *
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nir_shift(nir_builder *b, nir_ssa_def *value, nir_ssa_def *left_shift)
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{
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return nir_bcsel(b,
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nir_ige(b, left_shift, nir_imm_int(b, 0)),
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nir_ishl(b, value, left_shift),
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nir_ushr(b, value, nir_ineg(b, left_shift)));
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}
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2017-10-20 17:35:48 +01:00
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static inline nir_ssa_def *
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nir_mask_shift(struct nir_builder *b, nir_ssa_def *src,
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uint32_t mask, int left_shift)
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{
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2021-05-04 19:08:09 +01:00
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return nir_shift_imm(b, nir_iand(b, src, nir_imm_int(b, mask)), left_shift);
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2017-10-20 17:35:48 +01:00
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}
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static inline nir_ssa_def *
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nir_mask_shift_or(struct nir_builder *b, nir_ssa_def *dst, nir_ssa_def *src,
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uint32_t src_mask, int src_left_shift)
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{
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return nir_ior(b, nir_mask_shift(b, src, src_mask, src_left_shift), dst);
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}
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2018-08-13 18:04:25 +01:00
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static inline nir_ssa_def *
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2018-12-11 21:40:54 +00:00
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nir_format_mask_uvec(nir_builder *b, nir_ssa_def *src, const unsigned *bits)
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2018-08-13 18:04:25 +01:00
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{
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2019-03-26 23:59:03 +00:00
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nir_const_value mask[NIR_MAX_VEC_COMPONENTS];
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memset(mask, 0, sizeof(mask));
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2018-08-13 18:04:25 +01:00
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for (unsigned i = 0; i < src->num_components; i++) {
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assert(bits[i] < 32);
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2019-03-26 23:59:03 +00:00
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mask[i].u32 = (1u << bits[i]) - 1;
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2018-08-13 18:04:25 +01:00
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}
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return nir_iand(b, src, nir_build_imm(b, src->num_components, 32, mask));
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}
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static inline nir_ssa_def *
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nir_format_sign_extend_ivec(nir_builder *b, nir_ssa_def *src,
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const unsigned *bits)
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{
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assert(src->num_components <= 4);
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nir_ssa_def *comps[4];
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for (unsigned i = 0; i < src->num_components; i++) {
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nir_ssa_def *shift = nir_imm_int(b, src->bit_size - bits[i]);
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comps[i] = nir_ishr(b, nir_ishl(b, nir_channel(b, src, i), shift), shift);
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}
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return nir_vec(b, comps, src->num_components);
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}
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2017-10-20 17:35:48 +01:00
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static inline nir_ssa_def *
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2018-08-13 17:41:41 +01:00
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nir_format_unpack_int(nir_builder *b, nir_ssa_def *packed,
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const unsigned *bits, unsigned num_components,
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bool sign_extend)
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2017-10-20 17:35:48 +01:00
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{
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assert(num_components >= 1 && num_components <= 4);
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2018-08-13 17:41:41 +01:00
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const unsigned bit_size = packed->bit_size;
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2017-10-20 17:35:48 +01:00
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nir_ssa_def *comps[4];
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2018-08-13 17:41:41 +01:00
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if (bits[0] >= bit_size) {
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assert(bits[0] == bit_size);
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2017-10-20 17:35:48 +01:00
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assert(num_components == 1);
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return packed;
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}
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2019-01-02 22:50:20 +00:00
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unsigned next_chan = 0;
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2017-10-20 17:35:48 +01:00
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unsigned offset = 0;
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for (unsigned i = 0; i < num_components; i++) {
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2018-08-13 17:41:41 +01:00
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assert(bits[i] < bit_size);
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assert(offset + bits[i] <= bit_size);
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2019-01-02 22:50:20 +00:00
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nir_ssa_def *chan = nir_channel(b, packed, next_chan);
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2018-08-13 17:41:41 +01:00
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nir_ssa_def *lshift = nir_imm_int(b, bit_size - (offset + bits[i]));
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nir_ssa_def *rshift = nir_imm_int(b, bit_size - bits[i]);
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if (sign_extend)
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2019-01-02 22:50:20 +00:00
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comps[i] = nir_ishr(b, nir_ishl(b, chan, lshift), rshift);
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2018-08-13 17:41:41 +01:00
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else
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2019-01-02 22:50:20 +00:00
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comps[i] = nir_ushr(b, nir_ishl(b, chan, lshift), rshift);
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2017-10-20 17:35:48 +01:00
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offset += bits[i];
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2019-01-02 22:50:20 +00:00
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if (offset >= bit_size) {
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next_chan++;
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offset -= bit_size;
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}
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2017-10-20 17:35:48 +01:00
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}
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return nir_vec(b, comps, num_components);
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}
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2018-08-13 17:41:41 +01:00
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static inline nir_ssa_def *
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nir_format_unpack_uint(nir_builder *b, nir_ssa_def *packed,
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const unsigned *bits, unsigned num_components)
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{
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return nir_format_unpack_int(b, packed, bits, num_components, false);
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}
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static inline nir_ssa_def *
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nir_format_unpack_sint(nir_builder *b, nir_ssa_def *packed,
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const unsigned *bits, unsigned num_components)
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{
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return nir_format_unpack_int(b, packed, bits, num_components, true);
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}
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2017-10-20 17:35:48 +01:00
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static inline nir_ssa_def *
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nir_format_pack_uint_unmasked(nir_builder *b, nir_ssa_def *color,
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const unsigned *bits, unsigned num_components)
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{
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assert(num_components >= 1 && num_components <= 4);
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nir_ssa_def *packed = nir_imm_int(b, 0);
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unsigned offset = 0;
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for (unsigned i = 0; i < num_components; i++) {
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2021-05-04 19:08:09 +01:00
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packed = nir_ior(b, packed, nir_shift_imm(b, nir_channel(b, color, i),
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2017-10-20 17:35:48 +01:00
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offset));
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offset += bits[i];
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}
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assert(offset <= packed->bit_size);
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return packed;
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}
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2021-05-01 16:45:28 +01:00
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static inline nir_ssa_def *
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nir_format_pack_uint_unmasked_ssa(nir_builder *b, nir_ssa_def *color,
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nir_ssa_def *bits)
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{
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nir_ssa_def *packed = nir_imm_int(b, 0);
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nir_ssa_def *offset = nir_imm_int(b, 0);
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for (unsigned i = 0; i < bits->num_components; i++) {
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packed = nir_ior(b, packed, nir_ishl(b, nir_channel(b, color, i), offset));
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offset = nir_iadd(b, offset, nir_channel(b, bits, i));
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}
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return packed;
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}
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2017-10-20 17:35:48 +01:00
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static inline nir_ssa_def *
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nir_format_pack_uint(nir_builder *b, nir_ssa_def *color,
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const unsigned *bits, unsigned num_components)
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{
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2018-08-13 18:04:25 +01:00
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return nir_format_pack_uint_unmasked(b, nir_format_mask_uvec(b, color, bits),
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2017-10-20 17:35:48 +01:00
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bits, num_components);
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}
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2018-01-26 06:52:37 +00:00
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2018-01-26 19:34:04 +00:00
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static inline nir_ssa_def *
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2018-08-13 20:57:22 +01:00
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nir_format_bitcast_uvec_unmasked(nir_builder *b, nir_ssa_def *src,
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unsigned src_bits, unsigned dst_bits)
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2018-01-26 19:34:04 +00:00
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{
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2018-08-13 20:57:22 +01:00
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assert(src->bit_size >= src_bits && src->bit_size >= dst_bits);
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2018-01-26 19:34:04 +00:00
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assert(src_bits == 8 || src_bits == 16 || src_bits == 32);
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assert(dst_bits == 8 || dst_bits == 16 || dst_bits == 32);
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if (src_bits == dst_bits)
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return src;
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const unsigned dst_components =
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DIV_ROUND_UP(src->num_components * src_bits, dst_bits);
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assert(dst_components <= 4);
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2018-07-14 03:49:36 +01:00
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nir_ssa_def *dst_chan[4] = {0};
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2018-01-26 19:34:04 +00:00
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if (dst_bits > src_bits) {
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unsigned shift = 0;
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unsigned dst_idx = 0;
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for (unsigned i = 0; i < src->num_components; i++) {
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nir_ssa_def *shifted = nir_ishl(b, nir_channel(b, src, i),
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nir_imm_int(b, shift));
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if (shift == 0) {
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dst_chan[dst_idx] = shifted;
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} else {
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dst_chan[dst_idx] = nir_ior(b, dst_chan[dst_idx], shifted);
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}
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shift += src_bits;
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if (shift >= dst_bits) {
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dst_idx++;
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shift = 0;
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}
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}
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} else {
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nir_ssa_def *mask = nir_imm_int(b, ~0u >> (32 - dst_bits));
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unsigned src_idx = 0;
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unsigned shift = 0;
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for (unsigned i = 0; i < dst_components; i++) {
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2020-08-21 19:21:33 +01:00
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dst_chan[i] = nir_iand(b, nir_ushr_imm(b, nir_channel(b, src, src_idx),
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shift),
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2018-01-26 19:34:04 +00:00
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mask);
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shift += dst_bits;
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if (shift >= src_bits) {
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src_idx++;
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shift = 0;
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}
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}
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}
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return nir_vec(b, dst_chan, dst_components);
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}
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2018-08-13 22:13:50 +01:00
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static inline nir_ssa_def *
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2018-12-11 21:40:54 +00:00
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_nir_format_norm_factor(nir_builder *b, const unsigned *bits,
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2018-08-13 22:13:50 +01:00
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unsigned num_components,
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bool is_signed)
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{
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2019-03-26 23:59:03 +00:00
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nir_const_value factor[NIR_MAX_VEC_COMPONENTS];
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memset(factor, 0, sizeof(factor));
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2018-08-13 22:13:50 +01:00
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for (unsigned i = 0; i < num_components; i++) {
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2020-02-26 06:29:03 +00:00
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assert(bits[i] <= 32);
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factor[i].f32 = (1ull << (bits[i] - is_signed)) - 1;
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2018-08-13 22:13:50 +01:00
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}
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return nir_build_imm(b, num_components, 32, factor);
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}
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static inline nir_ssa_def *
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2018-12-11 21:40:54 +00:00
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nir_format_unorm_to_float(nir_builder *b, nir_ssa_def *u, const unsigned *bits)
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2018-08-13 22:13:50 +01:00
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{
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nir_ssa_def *factor =
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_nir_format_norm_factor(b, bits, u->num_components, false);
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return nir_fdiv(b, nir_u2f32(b, u), factor);
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}
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static inline nir_ssa_def *
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2018-12-11 21:40:54 +00:00
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nir_format_snorm_to_float(nir_builder *b, nir_ssa_def *s, const unsigned *bits)
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2018-08-13 22:13:50 +01:00
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{
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nir_ssa_def *factor =
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_nir_format_norm_factor(b, bits, s->num_components, true);
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return nir_fmax(b, nir_fdiv(b, nir_i2f32(b, s), factor),
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nir_imm_float(b, -1.0f));
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}
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static inline nir_ssa_def *
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2018-12-11 21:40:54 +00:00
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nir_format_float_to_unorm(nir_builder *b, nir_ssa_def *f, const unsigned *bits)
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2018-08-13 22:13:50 +01:00
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{
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nir_ssa_def *factor =
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_nir_format_norm_factor(b, bits, f->num_components, false);
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/* Clamp to the range [0, 1] */
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f = nir_fsat(b, f);
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return nir_f2u32(b, nir_fround_even(b, nir_fmul(b, f, factor)));
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}
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static inline nir_ssa_def *
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2018-12-11 21:40:54 +00:00
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nir_format_float_to_snorm(nir_builder *b, nir_ssa_def *f, const unsigned *bits)
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2018-08-13 22:13:50 +01:00
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{
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nir_ssa_def *factor =
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_nir_format_norm_factor(b, bits, f->num_components, true);
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/* Clamp to the range [-1, 1] */
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f = nir_fmin(b, nir_fmax(b, f, nir_imm_float(b, -1)), nir_imm_float(b, 1));
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return nir_f2i32(b, nir_fround_even(b, nir_fmul(b, f, factor)));
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}
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2018-12-11 21:49:28 +00:00
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/* Converts a vector of floats to a vector of half-floats packed in the low 16
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* bits.
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*/
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static inline nir_ssa_def *
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nir_format_float_to_half(nir_builder *b, nir_ssa_def *f)
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|
{
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nir_ssa_def *zero = nir_imm_float(b, 0);
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nir_ssa_def *f16comps[4];
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for (unsigned i = 0; i < f->num_components; i++)
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f16comps[i] = nir_pack_half_2x16_split(b, nir_channel(b, f, i), zero);
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return nir_vec(b, f16comps, f->num_components);
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}
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2018-01-26 06:52:37 +00:00
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static inline nir_ssa_def *
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nir_format_linear_to_srgb(nir_builder *b, nir_ssa_def *c)
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{
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nir_ssa_def *linear = nir_fmul(b, c, nir_imm_float(b, 12.92f));
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nir_ssa_def *curved =
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nir_fsub(b, nir_fmul(b, nir_imm_float(b, 1.055f),
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nir_fpow(b, c, nir_imm_float(b, 1.0 / 2.4))),
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nir_imm_float(b, 0.055f));
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return nir_fsat(b, nir_bcsel(b, nir_flt(b, c, nir_imm_float(b, 0.0031308f)),
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linear, curved));
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}
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static inline nir_ssa_def *
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nir_format_srgb_to_linear(nir_builder *b, nir_ssa_def *c)
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{
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nir_ssa_def *linear = nir_fdiv(b, c, nir_imm_float(b, 12.92f));
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nir_ssa_def *curved =
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nir_fpow(b, nir_fdiv(b, nir_fadd(b, c, nir_imm_float(b, 0.055f)),
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nir_imm_float(b, 1.055f)),
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nir_imm_float(b, 2.4f));
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return nir_fsat(b, nir_bcsel(b, nir_fge(b, nir_imm_float(b, 0.04045f), c),
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linear, curved));
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}
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2018-01-26 06:32:16 +00:00
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2018-12-11 21:49:28 +00:00
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/* Clamps a vector of uints so they don't extend beyond the given number of
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* bits per channel.
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*/
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static inline nir_ssa_def *
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nir_format_clamp_uint(nir_builder *b, nir_ssa_def *f, const unsigned *bits)
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{
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if (bits[0] == 32)
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return f;
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2019-03-26 23:59:03 +00:00
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nir_const_value max[NIR_MAX_VEC_COMPONENTS];
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memset(max, 0, sizeof(max));
|
2018-12-11 21:49:28 +00:00
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for (unsigned i = 0; i < f->num_components; i++) {
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assert(bits[i] < 32);
|
2019-03-26 23:59:03 +00:00
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max[i].u32 = (1 << bits[i]) - 1;
|
2018-12-11 21:49:28 +00:00
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}
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return nir_umin(b, f, nir_build_imm(b, f->num_components, 32, max));
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}
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/* Clamps a vector of sints so they don't extend beyond the given number of
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* bits per channel.
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*/
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static inline nir_ssa_def *
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nir_format_clamp_sint(nir_builder *b, nir_ssa_def *f, const unsigned *bits)
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{
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if (bits[0] == 32)
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return f;
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|
2019-03-26 23:59:03 +00:00
|
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|
nir_const_value min[NIR_MAX_VEC_COMPONENTS], max[NIR_MAX_VEC_COMPONENTS];
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|
|
memset(min, 0, sizeof(min));
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memset(max, 0, sizeof(max));
|
2018-12-11 21:49:28 +00:00
|
|
|
for (unsigned i = 0; i < f->num_components; i++) {
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|
|
|
assert(bits[i] < 32);
|
2019-03-26 23:59:03 +00:00
|
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max[i].i32 = (1 << (bits[i] - 1)) - 1;
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|
|
min[i].i32 = -(1 << (bits[i] - 1));
|
2018-12-11 21:49:28 +00:00
|
|
|
}
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|
|
f = nir_imin(b, f, nir_build_imm(b, f->num_components, 32, max));
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|
|
f = nir_imax(b, f, nir_build_imm(b, f->num_components, 32, min));
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|
|
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|
|
|
return f;
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|
|
}
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|
|
2018-01-26 06:32:16 +00:00
|
|
|
static inline nir_ssa_def *
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nir_format_unpack_11f11f10f(nir_builder *b, nir_ssa_def *packed)
|
|
|
|
{
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|
|
|
nir_ssa_def *chans[3];
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|
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chans[0] = nir_mask_shift(b, packed, 0x000007ff, 4);
|
2018-08-16 15:21:10 +01:00
|
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|
chans[1] = nir_mask_shift(b, packed, 0x003ff800, -7);
|
2018-01-26 06:32:16 +00:00
|
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|
chans[2] = nir_mask_shift(b, packed, 0xffc00000, -17);
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|
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|
for (unsigned i = 0; i < 3; i++)
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chans[i] = nir_unpack_half_2x16_split_x(b, chans[i]);
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|
|
|
|
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|
return nir_vec(b, chans, 3);
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|
}
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|
|
|
|
static inline nir_ssa_def *
|
2018-08-13 23:31:19 +01:00
|
|
|
nir_format_pack_11f11f10f(nir_builder *b, nir_ssa_def *color)
|
2018-01-26 06:32:16 +00:00
|
|
|
{
|
|
|
|
/* 10 and 11-bit floats are unsigned. Clamp to non-negative */
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|
|
nir_ssa_def *clamped = nir_fmax(b, color, nir_imm_float(b, 0));
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|
|
|
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|
|
nir_ssa_def *undef = nir_ssa_undef(b, 1, color->bit_size);
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|
|
nir_ssa_def *p1 = nir_pack_half_2x16_split(b, nir_channel(b, clamped, 0),
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|
|
|
nir_channel(b, clamped, 1));
|
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|
|
nir_ssa_def *p2 = nir_pack_half_2x16_split(b, nir_channel(b, clamped, 2),
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|
|
undef);
|
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|
|
|
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|
|
/* A 10 or 11-bit float has the same exponent as a 16-bit float but with
|
|
|
|
* fewer mantissa bits and no sign bit. All we have to do is throw away
|
|
|
|
* the sign bit and the bottom mantissa bits and shift it into place.
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|
|
|
*/
|
|
|
|
nir_ssa_def *packed = nir_imm_int(b, 0);
|
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|
|
packed = nir_mask_shift_or(b, packed, p1, 0x00007ff0, -4);
|
|
|
|
packed = nir_mask_shift_or(b, packed, p1, 0x7ff00000, -9);
|
|
|
|
packed = nir_mask_shift_or(b, packed, p2, 0x00007fe0, 17);
|
|
|
|
|
|
|
|
return packed;
|
|
|
|
}
|
2018-01-26 07:06:11 +00:00
|
|
|
|
|
|
|
static inline nir_ssa_def *
|
|
|
|
nir_format_pack_r9g9b9e5(nir_builder *b, nir_ssa_def *color)
|
|
|
|
{
|
|
|
|
/* See also float3_to_rgb9e5 */
|
|
|
|
|
|
|
|
/* First, we need to clamp it to range. */
|
|
|
|
nir_ssa_def *clamped = nir_fmin(b, color, nir_imm_float(b, MAX_RGB9E5));
|
|
|
|
|
|
|
|
/* Get rid of negatives and NaN */
|
|
|
|
clamped = nir_bcsel(b, nir_ult(b, nir_imm_int(b, 0x7f800000), color),
|
|
|
|
nir_imm_float(b, 0), clamped);
|
|
|
|
|
|
|
|
/* maxrgb.u = MAX3(rc.u, gc.u, bc.u); */
|
|
|
|
nir_ssa_def *maxu = nir_umax(b, nir_channel(b, clamped, 0),
|
|
|
|
nir_umax(b, nir_channel(b, clamped, 1),
|
|
|
|
nir_channel(b, clamped, 2)));
|
|
|
|
|
|
|
|
/* maxrgb.u += maxrgb.u & (1 << (23-9)); */
|
|
|
|
maxu = nir_iadd(b, maxu, nir_iand(b, maxu, nir_imm_int(b, 1 << 14)));
|
|
|
|
|
|
|
|
/* exp_shared = MAX2((maxrgb.u >> 23), -RGB9E5_EXP_BIAS - 1 + 127) +
|
|
|
|
* 1 + RGB9E5_EXP_BIAS - 127;
|
|
|
|
*/
|
|
|
|
nir_ssa_def *exp_shared =
|
2020-08-21 19:21:33 +01:00
|
|
|
nir_iadd(b, nir_umax(b, nir_ushr_imm(b, maxu, 23),
|
2018-01-26 07:06:11 +00:00
|
|
|
nir_imm_int(b, -RGB9E5_EXP_BIAS - 1 + 127)),
|
|
|
|
nir_imm_int(b, 1 + RGB9E5_EXP_BIAS - 127));
|
|
|
|
|
|
|
|
/* revdenom_biasedexp = 127 - (exp_shared - RGB9E5_EXP_BIAS -
|
|
|
|
* RGB9E5_MANTISSA_BITS) + 1;
|
|
|
|
*/
|
|
|
|
nir_ssa_def *revdenom_biasedexp =
|
|
|
|
nir_isub(b, nir_imm_int(b, 127 + RGB9E5_EXP_BIAS +
|
|
|
|
RGB9E5_MANTISSA_BITS + 1),
|
|
|
|
exp_shared);
|
|
|
|
|
|
|
|
/* revdenom.u = revdenom_biasedexp << 23; */
|
|
|
|
nir_ssa_def *revdenom =
|
|
|
|
nir_ishl(b, revdenom_biasedexp, nir_imm_int(b, 23));
|
|
|
|
|
|
|
|
/* rm = (int) (rc.f * revdenom.f);
|
|
|
|
* gm = (int) (gc.f * revdenom.f);
|
|
|
|
* bm = (int) (bc.f * revdenom.f);
|
|
|
|
*/
|
|
|
|
nir_ssa_def *mantissa =
|
|
|
|
nir_f2i32(b, nir_fmul(b, clamped, revdenom));
|
|
|
|
|
|
|
|
/* rm = (rm & 1) + (rm >> 1);
|
|
|
|
* gm = (gm & 1) + (gm >> 1);
|
|
|
|
* bm = (bm & 1) + (bm >> 1);
|
|
|
|
*/
|
2020-08-21 19:21:33 +01:00
|
|
|
mantissa = nir_iadd(b, nir_iand_imm(b, mantissa, 1),
|
|
|
|
nir_ushr_imm(b, mantissa, 1));
|
2018-01-26 07:06:11 +00:00
|
|
|
|
|
|
|
nir_ssa_def *packed = nir_channel(b, mantissa, 0);
|
|
|
|
packed = nir_mask_shift_or(b, packed, nir_channel(b, mantissa, 1), ~0, 9);
|
|
|
|
packed = nir_mask_shift_or(b, packed, nir_channel(b, mantissa, 2), ~0, 18);
|
|
|
|
packed = nir_mask_shift_or(b, packed, exp_shared, ~0, 27);
|
|
|
|
|
|
|
|
return packed;
|
|
|
|
}
|